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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.09 99.81 96.99 100.00 100.00 98.60 99.70 98.52


Total test records in report: 1037
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T792 /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1384042407 May 09 02:03:52 PM PDT 24 May 09 02:04:16 PM PDT 24 2654212304 ps
T793 /workspace/coverage/default/15.sram_ctrl_smoke.4015195427 May 09 01:53:14 PM PDT 24 May 09 01:53:28 PM PDT 24 14962657147 ps
T794 /workspace/coverage/default/0.sram_ctrl_bijection.2700858672 May 09 01:49:40 PM PDT 24 May 09 02:15:33 PM PDT 24 23389862438 ps
T795 /workspace/coverage/default/41.sram_ctrl_regwen.3937963280 May 09 02:01:01 PM PDT 24 May 09 02:21:54 PM PDT 24 10996954834 ps
T796 /workspace/coverage/default/12.sram_ctrl_max_throughput.1883782310 May 09 01:52:31 PM PDT 24 May 09 01:52:44 PM PDT 24 1473037831 ps
T797 /workspace/coverage/default/31.sram_ctrl_stress_pipeline.2271151388 May 09 01:58:10 PM PDT 24 May 09 02:03:15 PM PDT 24 52424490736 ps
T798 /workspace/coverage/default/23.sram_ctrl_multiple_keys.56031004 May 09 01:55:32 PM PDT 24 May 09 02:16:23 PM PDT 24 14705501196 ps
T799 /workspace/coverage/default/37.sram_ctrl_max_throughput.3800889615 May 09 02:00:04 PM PDT 24 May 09 02:02:25 PM PDT 24 1370854374 ps
T800 /workspace/coverage/default/23.sram_ctrl_smoke.2859743666 May 09 01:55:31 PM PDT 24 May 09 01:55:37 PM PDT 24 711286905 ps
T801 /workspace/coverage/default/16.sram_ctrl_executable.240921018 May 09 01:53:37 PM PDT 24 May 09 02:07:01 PM PDT 24 36542665765 ps
T802 /workspace/coverage/default/22.sram_ctrl_partial_access.2360373904 May 09 01:55:22 PM PDT 24 May 09 01:56:08 PM PDT 24 3792739559 ps
T803 /workspace/coverage/default/13.sram_ctrl_stress_pipeline.1390855270 May 09 01:52:41 PM PDT 24 May 09 01:58:50 PM PDT 24 86567486599 ps
T804 /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.286936550 May 09 01:59:34 PM PDT 24 May 09 02:00:03 PM PDT 24 1107816837 ps
T805 /workspace/coverage/default/10.sram_ctrl_mem_walk.2044546235 May 09 01:52:17 PM PDT 24 May 09 01:54:25 PM PDT 24 2021101852 ps
T806 /workspace/coverage/default/19.sram_ctrl_executable.250605067 May 09 01:54:27 PM PDT 24 May 09 02:00:29 PM PDT 24 22608836951 ps
T807 /workspace/coverage/default/42.sram_ctrl_partial_access.1987360180 May 09 02:01:11 PM PDT 24 May 09 02:01:24 PM PDT 24 1011426047 ps
T808 /workspace/coverage/default/9.sram_ctrl_ram_cfg.1992170718 May 09 01:51:57 PM PDT 24 May 09 01:52:03 PM PDT 24 655516045 ps
T809 /workspace/coverage/default/18.sram_ctrl_smoke.223130953 May 09 01:53:55 PM PDT 24 May 09 01:56:49 PM PDT 24 1356940254 ps
T810 /workspace/coverage/default/16.sram_ctrl_ram_cfg.1699508569 May 09 01:53:37 PM PDT 24 May 09 01:53:42 PM PDT 24 704457432 ps
T811 /workspace/coverage/default/35.sram_ctrl_mem_walk.1469782943 May 09 01:59:34 PM PDT 24 May 09 02:03:51 PM PDT 24 21882028049 ps
T812 /workspace/coverage/default/42.sram_ctrl_alert_test.66845589 May 09 02:01:35 PM PDT 24 May 09 02:01:36 PM PDT 24 14003026 ps
T813 /workspace/coverage/default/48.sram_ctrl_max_throughput.1536629279 May 09 02:03:27 PM PDT 24 May 09 02:03:57 PM PDT 24 764562135 ps
T814 /workspace/coverage/default/26.sram_ctrl_smoke.2037943541 May 09 01:56:22 PM PDT 24 May 09 01:56:29 PM PDT 24 793646016 ps
T815 /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.2887286311 May 09 02:02:32 PM PDT 24 May 09 02:03:12 PM PDT 24 2944392976 ps
T816 /workspace/coverage/default/15.sram_ctrl_mem_walk.797594164 May 09 01:53:25 PM PDT 24 May 09 01:58:58 PM PDT 24 86054746769 ps
T817 /workspace/coverage/default/3.sram_ctrl_multiple_keys.4235270619 May 09 01:50:12 PM PDT 24 May 09 01:54:40 PM PDT 24 11558783011 ps
T818 /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.3330961831 May 09 01:54:07 PM PDT 24 May 09 01:54:18 PM PDT 24 717827362 ps
T819 /workspace/coverage/default/12.sram_ctrl_stress_pipeline.880992773 May 09 01:52:34 PM PDT 24 May 09 01:56:08 PM PDT 24 7539842759 ps
T820 /workspace/coverage/default/25.sram_ctrl_max_throughput.3747066126 May 09 01:56:14 PM PDT 24 May 09 01:57:14 PM PDT 24 1491580464 ps
T821 /workspace/coverage/default/35.sram_ctrl_lc_escalation.342887057 May 09 01:59:22 PM PDT 24 May 09 02:00:06 PM PDT 24 7053768770 ps
T81 /workspace/coverage/default/49.sram_ctrl_mem_partial_access.2626216488 May 09 02:03:51 PM PDT 24 May 09 02:05:57 PM PDT 24 1583956959 ps
T822 /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.2539037101 May 09 01:51:56 PM PDT 24 May 09 01:52:57 PM PDT 24 4718166382 ps
T823 /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.2559769866 May 09 02:03:18 PM PDT 24 May 09 02:03:44 PM PDT 24 3504412759 ps
T824 /workspace/coverage/default/31.sram_ctrl_alert_test.2779147512 May 09 01:58:19 PM PDT 24 May 09 01:58:20 PM PDT 24 13268325 ps
T825 /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.1719759975 May 09 01:59:10 PM PDT 24 May 09 02:06:52 PM PDT 24 80298533549 ps
T826 /workspace/coverage/default/5.sram_ctrl_ram_cfg.2387388154 May 09 01:50:51 PM PDT 24 May 09 01:50:57 PM PDT 24 1350891047 ps
T827 /workspace/coverage/default/47.sram_ctrl_max_throughput.740813957 May 09 02:02:54 PM PDT 24 May 09 02:05:08 PM PDT 24 1619371885 ps
T828 /workspace/coverage/default/34.sram_ctrl_ram_cfg.2412897364 May 09 01:59:09 PM PDT 24 May 09 01:59:14 PM PDT 24 682259813 ps
T829 /workspace/coverage/default/23.sram_ctrl_partial_access.2395358675 May 09 01:55:32 PM PDT 24 May 09 01:55:55 PM PDT 24 3436983904 ps
T830 /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.3621343238 May 09 01:58:11 PM PDT 24 May 09 01:58:28 PM PDT 24 2803835520 ps
T831 /workspace/coverage/default/49.sram_ctrl_multiple_keys.844348351 May 09 02:03:41 PM PDT 24 May 09 02:34:57 PM PDT 24 11029889248 ps
T832 /workspace/coverage/default/49.sram_ctrl_stress_pipeline.1047756860 May 09 02:03:43 PM PDT 24 May 09 02:06:30 PM PDT 24 3746662447 ps
T833 /workspace/coverage/default/14.sram_ctrl_bijection.2082373606 May 09 01:52:52 PM PDT 24 May 09 02:31:19 PM PDT 24 296993997263 ps
T834 /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.600316191 May 09 02:01:15 PM PDT 24 May 09 02:01:22 PM PDT 24 2789810239 ps
T835 /workspace/coverage/default/49.sram_ctrl_smoke.2389582858 May 09 02:03:43 PM PDT 24 May 09 02:04:13 PM PDT 24 1432643333 ps
T836 /workspace/coverage/default/33.sram_ctrl_stress_all.3236442290 May 09 01:58:58 PM PDT 24 May 09 03:32:20 PM PDT 24 202842104468 ps
T837 /workspace/coverage/default/37.sram_ctrl_stress_pipeline.1365388851 May 09 02:00:06 PM PDT 24 May 09 02:02:44 PM PDT 24 18999331134 ps
T838 /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.1682082577 May 09 01:53:37 PM PDT 24 May 09 02:02:28 PM PDT 24 45638515592 ps
T839 /workspace/coverage/default/5.sram_ctrl_access_during_key_req.3106518608 May 09 01:50:50 PM PDT 24 May 09 02:03:50 PM PDT 24 47220695287 ps
T840 /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.707092115 May 09 01:58:40 PM PDT 24 May 09 02:03:29 PM PDT 24 13419995749 ps
T841 /workspace/coverage/default/38.sram_ctrl_max_throughput.792017011 May 09 02:00:21 PM PDT 24 May 09 02:00:43 PM PDT 24 2924253724 ps
T842 /workspace/coverage/default/29.sram_ctrl_mem_partial_access.3100602179 May 09 01:57:37 PM PDT 24 May 09 01:58:53 PM PDT 24 9067462326 ps
T82 /workspace/coverage/default/21.sram_ctrl_mem_partial_access.2248172461 May 09 01:55:08 PM PDT 24 May 09 01:57:38 PM PDT 24 18965199921 ps
T843 /workspace/coverage/default/5.sram_ctrl_executable.1599214163 May 09 01:50:53 PM PDT 24 May 09 02:04:57 PM PDT 24 11205972647 ps
T844 /workspace/coverage/default/2.sram_ctrl_ram_cfg.3276203156 May 09 01:49:59 PM PDT 24 May 09 01:50:04 PM PDT 24 679310271 ps
T845 /workspace/coverage/default/3.sram_ctrl_lc_escalation.2859318228 May 09 01:50:20 PM PDT 24 May 09 01:51:55 PM PDT 24 26744182930 ps
T846 /workspace/coverage/default/4.sram_ctrl_max_throughput.1770734842 May 09 01:50:29 PM PDT 24 May 09 01:50:48 PM PDT 24 700188164 ps
T847 /workspace/coverage/default/48.sram_ctrl_bijection.3352190307 May 09 02:03:27 PM PDT 24 May 09 02:21:51 PM PDT 24 61853438301 ps
T848 /workspace/coverage/default/49.sram_ctrl_max_throughput.3557258786 May 09 02:03:43 PM PDT 24 May 09 02:03:52 PM PDT 24 1425596938 ps
T849 /workspace/coverage/default/47.sram_ctrl_bijection.2173793939 May 09 02:02:53 PM PDT 24 May 09 02:27:44 PM PDT 24 21321812616 ps
T850 /workspace/coverage/default/12.sram_ctrl_regwen.2572760767 May 09 01:52:32 PM PDT 24 May 09 02:10:23 PM PDT 24 48557070256 ps
T851 /workspace/coverage/default/4.sram_ctrl_ram_cfg.3788240186 May 09 01:50:41 PM PDT 24 May 09 01:50:46 PM PDT 24 1401892556 ps
T852 /workspace/coverage/default/22.sram_ctrl_ram_cfg.1076802514 May 09 01:55:22 PM PDT 24 May 09 01:55:26 PM PDT 24 1248542401 ps
T853 /workspace/coverage/default/46.sram_ctrl_mem_partial_access.4016066753 May 09 02:02:53 PM PDT 24 May 09 02:05:03 PM PDT 24 1594960043 ps
T854 /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.1539754742 May 09 02:03:28 PM PDT 24 May 09 02:05:53 PM PDT 24 817680887 ps
T855 /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2867148694 May 09 01:52:09 PM PDT 24 May 09 01:52:23 PM PDT 24 262155145 ps
T856 /workspace/coverage/default/3.sram_ctrl_alert_test.2008023705 May 09 01:50:23 PM PDT 24 May 09 01:50:25 PM PDT 24 12873724 ps
T857 /workspace/coverage/default/41.sram_ctrl_partial_access.367141979 May 09 02:01:03 PM PDT 24 May 09 02:01:21 PM PDT 24 4331572827 ps
T858 /workspace/coverage/default/21.sram_ctrl_mem_walk.651042487 May 09 01:55:09 PM PDT 24 May 09 02:00:06 PM PDT 24 55122737037 ps
T859 /workspace/coverage/default/35.sram_ctrl_stress_pipeline.1726583886 May 09 01:59:23 PM PDT 24 May 09 02:03:14 PM PDT 24 19839459690 ps
T860 /workspace/coverage/default/49.sram_ctrl_alert_test.759429240 May 09 02:03:53 PM PDT 24 May 09 02:03:55 PM PDT 24 40516569 ps
T861 /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.4274859200 May 09 01:57:37 PM PDT 24 May 09 02:02:33 PM PDT 24 5408305482 ps
T862 /workspace/coverage/default/13.sram_ctrl_ram_cfg.1147068976 May 09 01:52:40 PM PDT 24 May 09 01:52:46 PM PDT 24 1601651807 ps
T863 /workspace/coverage/default/21.sram_ctrl_ram_cfg.1352196042 May 09 01:54:57 PM PDT 24 May 09 01:55:02 PM PDT 24 1405606236 ps
T864 /workspace/coverage/default/0.sram_ctrl_executable.3804903404 May 09 01:49:40 PM PDT 24 May 09 02:11:27 PM PDT 24 25892735266 ps
T865 /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.3490271582 May 09 01:52:31 PM PDT 24 May 09 01:53:19 PM PDT 24 4852297112 ps
T866 /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.1131779931 May 09 01:58:00 PM PDT 24 May 09 01:58:16 PM PDT 24 701856167 ps
T867 /workspace/coverage/default/25.sram_ctrl_bijection.830654725 May 09 01:56:05 PM PDT 24 May 09 02:06:52 PM PDT 24 17622679623 ps
T868 /workspace/coverage/default/18.sram_ctrl_stress_all.1164082885 May 09 01:54:17 PM PDT 24 May 09 02:15:13 PM PDT 24 25743694433 ps
T869 /workspace/coverage/default/28.sram_ctrl_stress_all.1767623400 May 09 01:57:27 PM PDT 24 May 09 02:35:18 PM PDT 24 118041906007 ps
T870 /workspace/coverage/default/23.sram_ctrl_stress_pipeline.4156631479 May 09 01:55:32 PM PDT 24 May 09 02:00:49 PM PDT 24 11766098534 ps
T871 /workspace/coverage/default/34.sram_ctrl_mem_walk.2760224944 May 09 01:59:09 PM PDT 24 May 09 02:03:15 PM PDT 24 8049903016 ps
T872 /workspace/coverage/default/24.sram_ctrl_max_throughput.1985033628 May 09 01:55:52 PM PDT 24 May 09 01:57:20 PM PDT 24 1424120775 ps
T873 /workspace/coverage/default/30.sram_ctrl_mem_walk.1174530773 May 09 01:57:59 PM PDT 24 May 09 02:00:12 PM PDT 24 24644565785 ps
T874 /workspace/coverage/default/18.sram_ctrl_alert_test.2847687088 May 09 01:54:21 PM PDT 24 May 09 01:54:23 PM PDT 24 37477038 ps
T875 /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.1695236309 May 09 02:02:35 PM PDT 24 May 09 02:06:53 PM PDT 24 5170745255 ps
T876 /workspace/coverage/default/6.sram_ctrl_partial_access.964687370 May 09 01:50:59 PM PDT 24 May 09 01:51:17 PM PDT 24 1906789287 ps
T877 /workspace/coverage/default/7.sram_ctrl_alert_test.1684039149 May 09 01:51:36 PM PDT 24 May 09 01:51:37 PM PDT 24 16482045 ps
T878 /workspace/coverage/default/28.sram_ctrl_mem_partial_access.2341604900 May 09 01:57:16 PM PDT 24 May 09 01:58:34 PM PDT 24 4815297780 ps
T879 /workspace/coverage/default/0.sram_ctrl_partial_access.3667120374 May 09 01:49:42 PM PDT 24 May 09 01:50:39 PM PDT 24 6594933119 ps
T880 /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.432379053 May 09 01:49:40 PM PDT 24 May 09 01:54:04 PM PDT 24 22637220630 ps
T881 /workspace/coverage/default/32.sram_ctrl_multiple_keys.1064549560 May 09 01:58:20 PM PDT 24 May 09 02:20:43 PM PDT 24 36708531661 ps
T882 /workspace/coverage/default/46.sram_ctrl_bijection.1118507021 May 09 02:02:31 PM PDT 24 May 09 02:31:10 PM PDT 24 23951024842 ps
T883 /workspace/coverage/default/29.sram_ctrl_stress_all.1732052749 May 09 01:57:50 PM PDT 24 May 09 03:09:28 PM PDT 24 102008733672 ps
T884 /workspace/coverage/default/27.sram_ctrl_bijection.1206009867 May 09 01:56:35 PM PDT 24 May 09 02:13:34 PM PDT 24 59020214034 ps
T885 /workspace/coverage/default/17.sram_ctrl_max_throughput.1147003662 May 09 01:53:47 PM PDT 24 May 09 01:55:46 PM PDT 24 3751064983 ps
T886 /workspace/coverage/default/31.sram_ctrl_mem_walk.3896248310 May 09 01:58:20 PM PDT 24 May 09 02:03:22 PM PDT 24 74586701942 ps
T887 /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.4145065404 May 09 01:57:08 PM PDT 24 May 09 02:03:55 PM PDT 24 16308959555 ps
T888 /workspace/coverage/default/2.sram_ctrl_bijection.1270826311 May 09 01:50:01 PM PDT 24 May 09 02:24:26 PM PDT 24 117355576846 ps
T889 /workspace/coverage/default/47.sram_ctrl_mem_walk.367965364 May 09 02:03:18 PM PDT 24 May 09 02:05:54 PM PDT 24 34369638459 ps
T890 /workspace/coverage/default/24.sram_ctrl_access_during_key_req.4046277383 May 09 01:55:53 PM PDT 24 May 09 02:06:57 PM PDT 24 57534375423 ps
T891 /workspace/coverage/default/5.sram_ctrl_smoke.2264896333 May 09 01:50:42 PM PDT 24 May 09 01:50:52 PM PDT 24 2931123286 ps
T892 /workspace/coverage/default/21.sram_ctrl_access_during_key_req.366359059 May 09 01:54:58 PM PDT 24 May 09 01:57:18 PM PDT 24 4088988914 ps
T893 /workspace/coverage/default/35.sram_ctrl_mem_partial_access.1517448778 May 09 01:59:33 PM PDT 24 May 09 02:02:04 PM PDT 24 4665653309 ps
T894 /workspace/coverage/default/27.sram_ctrl_ram_cfg.2162377214 May 09 01:56:45 PM PDT 24 May 09 01:56:50 PM PDT 24 3359147766 ps
T895 /workspace/coverage/default/45.sram_ctrl_partial_access.3638456343 May 09 02:02:12 PM PDT 24 May 09 02:02:25 PM PDT 24 1682402830 ps
T896 /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.487635882 May 09 01:54:26 PM PDT 24 May 09 01:54:41 PM PDT 24 705463874 ps
T897 /workspace/coverage/default/11.sram_ctrl_stress_all.3244289308 May 09 01:52:34 PM PDT 24 May 09 02:32:08 PM PDT 24 55126778490 ps
T898 /workspace/coverage/default/12.sram_ctrl_bijection.1669178821 May 09 01:52:34 PM PDT 24 May 09 02:16:58 PM PDT 24 92638991273 ps
T899 /workspace/coverage/default/29.sram_ctrl_regwen.1764849327 May 09 01:57:37 PM PDT 24 May 09 02:25:15 PM PDT 24 5907137552 ps
T900 /workspace/coverage/default/48.sram_ctrl_stress_all.3090235743 May 09 02:03:29 PM PDT 24 May 09 02:35:39 PM PDT 24 41493243465 ps
T901 /workspace/coverage/default/21.sram_ctrl_executable.1505109504 May 09 01:54:59 PM PDT 24 May 09 02:22:47 PM PDT 24 10797924366 ps
T902 /workspace/coverage/default/48.sram_ctrl_ram_cfg.3746349917 May 09 02:03:27 PM PDT 24 May 09 02:03:33 PM PDT 24 366748170 ps
T903 /workspace/coverage/default/6.sram_ctrl_stress_all.2109402441 May 09 01:51:13 PM PDT 24 May 09 02:44:24 PM PDT 24 530890334568 ps
T904 /workspace/coverage/default/35.sram_ctrl_ram_cfg.2921431714 May 09 01:59:34 PM PDT 24 May 09 01:59:38 PM PDT 24 1104113859 ps
T905 /workspace/coverage/default/14.sram_ctrl_access_during_key_req.392730804 May 09 01:53:02 PM PDT 24 May 09 01:57:33 PM PDT 24 25774101537 ps
T906 /workspace/coverage/default/23.sram_ctrl_max_throughput.819575113 May 09 01:55:32 PM PDT 24 May 09 01:57:10 PM PDT 24 755066169 ps
T907 /workspace/coverage/default/45.sram_ctrl_ram_cfg.1852048539 May 09 02:02:25 PM PDT 24 May 09 02:02:29 PM PDT 24 353337032 ps
T908 /workspace/coverage/default/36.sram_ctrl_alert_test.3204460102 May 09 01:59:52 PM PDT 24 May 09 01:59:54 PM PDT 24 85945786 ps
T909 /workspace/coverage/default/25.sram_ctrl_stress_pipeline.1808172414 May 09 01:56:15 PM PDT 24 May 09 01:59:04 PM PDT 24 9269423421 ps
T910 /workspace/coverage/default/19.sram_ctrl_stress_pipeline.4163200595 May 09 01:54:19 PM PDT 24 May 09 02:00:19 PM PDT 24 10808925246 ps
T911 /workspace/coverage/default/17.sram_ctrl_stress_all.2759672083 May 09 01:53:56 PM PDT 24 May 09 02:41:41 PM PDT 24 345642328289 ps
T912 /workspace/coverage/default/14.sram_ctrl_mem_walk.451381643 May 09 01:53:04 PM PDT 24 May 09 01:55:41 PM PDT 24 12458216243 ps
T913 /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.1241281130 May 09 01:49:41 PM PDT 24 May 09 01:49:59 PM PDT 24 5032243747 ps
T914 /workspace/coverage/default/42.sram_ctrl_bijection.3149093939 May 09 02:01:13 PM PDT 24 May 09 02:18:25 PM PDT 24 110380041421 ps
T915 /workspace/coverage/default/49.sram_ctrl_lc_escalation.2278275266 May 09 02:03:52 PM PDT 24 May 09 02:04:48 PM PDT 24 7801716062 ps
T916 /workspace/coverage/default/0.sram_ctrl_mem_walk.3903632115 May 09 01:49:43 PM PDT 24 May 09 01:53:47 PM PDT 24 17909816960 ps
T917 /workspace/coverage/default/33.sram_ctrl_partial_access.2632890965 May 09 01:58:40 PM PDT 24 May 09 01:59:13 PM PDT 24 18146535869 ps
T918 /workspace/coverage/default/38.sram_ctrl_lc_escalation.1575523925 May 09 02:00:22 PM PDT 24 May 09 02:01:28 PM PDT 24 23056601928 ps
T919 /workspace/coverage/default/27.sram_ctrl_stress_all.792318020 May 09 01:56:58 PM PDT 24 May 09 02:26:55 PM PDT 24 389255503792 ps
T920 /workspace/coverage/default/1.sram_ctrl_bijection.2263555897 May 09 01:49:53 PM PDT 24 May 09 01:59:27 PM PDT 24 28286112255 ps
T921 /workspace/coverage/default/35.sram_ctrl_smoke.1735450732 May 09 01:59:22 PM PDT 24 May 09 02:01:36 PM PDT 24 5159230338 ps
T922 /workspace/coverage/default/33.sram_ctrl_lc_escalation.3678908057 May 09 01:58:49 PM PDT 24 May 09 02:00:41 PM PDT 24 18237952563 ps
T923 /workspace/coverage/default/20.sram_ctrl_stress_pipeline.2044882238 May 09 01:54:38 PM PDT 24 May 09 01:57:37 PM PDT 24 10529330017 ps
T924 /workspace/coverage/default/40.sram_ctrl_lc_escalation.2187181605 May 09 02:00:52 PM PDT 24 May 09 02:01:50 PM PDT 24 20420804715 ps
T925 /workspace/coverage/default/31.sram_ctrl_lc_escalation.1707072058 May 09 01:58:11 PM PDT 24 May 09 01:58:56 PM PDT 24 8084650447 ps
T926 /workspace/coverage/default/43.sram_ctrl_bijection.2623538872 May 09 02:01:34 PM PDT 24 May 09 02:13:24 PM PDT 24 10834922206 ps
T927 /workspace/coverage/default/33.sram_ctrl_stress_pipeline.2078300053 May 09 01:58:39 PM PDT 24 May 09 02:03:51 PM PDT 24 22184747129 ps
T928 /workspace/coverage/default/9.sram_ctrl_executable.2737329632 May 09 01:51:56 PM PDT 24 May 09 01:54:55 PM PDT 24 3664454105 ps
T929 /workspace/coverage/default/28.sram_ctrl_lc_escalation.4267155743 May 09 01:57:05 PM PDT 24 May 09 01:58:00 PM PDT 24 9626156990 ps
T930 /workspace/coverage/default/48.sram_ctrl_smoke.2046485969 May 09 02:03:18 PM PDT 24 May 09 02:03:29 PM PDT 24 2319673919 ps
T931 /workspace/coverage/default/25.sram_ctrl_mem_walk.3339243351 May 09 01:56:25 PM PDT 24 May 09 02:01:39 PM PDT 24 36558727051 ps
T932 /workspace/coverage/default/31.sram_ctrl_multiple_keys.2398482261 May 09 01:58:11 PM PDT 24 May 09 02:21:43 PM PDT 24 25831450141 ps
T933 /workspace/coverage/default/23.sram_ctrl_access_during_key_req.975276545 May 09 01:55:40 PM PDT 24 May 09 02:21:01 PM PDT 24 59181110313 ps
T934 /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.2233448754 May 09 01:54:49 PM PDT 24 May 09 01:55:11 PM PDT 24 812907349 ps
T935 /workspace/coverage/default/45.sram_ctrl_executable.941011395 May 09 02:02:27 PM PDT 24 May 09 02:12:49 PM PDT 24 28770153514 ps
T936 /workspace/coverage/default/1.sram_ctrl_mem_walk.1205176412 May 09 01:49:55 PM PDT 24 May 09 01:55:15 PM PDT 24 74732696531 ps
T937 /workspace/coverage/default/30.sram_ctrl_max_throughput.731533507 May 09 01:58:01 PM PDT 24 May 09 01:58:10 PM PDT 24 2811002363 ps
T938 /workspace/coverage/default/13.sram_ctrl_access_during_key_req.4134021122 May 09 01:52:42 PM PDT 24 May 09 01:58:22 PM PDT 24 6917541442 ps
T939 /workspace/coverage/default/34.sram_ctrl_multiple_keys.3896580533 May 09 01:58:59 PM PDT 24 May 09 02:30:33 PM PDT 24 28470218860 ps
T940 /workspace/coverage/default/40.sram_ctrl_max_throughput.1095440532 May 09 02:00:42 PM PDT 24 May 09 02:03:06 PM PDT 24 2944373205 ps
T941 /workspace/coverage/default/23.sram_ctrl_regwen.2458858602 May 09 01:55:43 PM PDT 24 May 09 02:11:52 PM PDT 24 5790404476 ps
T62 /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3543061496 May 09 02:31:07 PM PDT 24 May 09 02:31:39 PM PDT 24 15459134728 ps
T88 /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1542063972 May 09 02:31:04 PM PDT 24 May 09 02:31:09 PM PDT 24 27162739 ps
T63 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3216526154 May 09 02:30:52 PM PDT 24 May 09 02:30:55 PM PDT 24 238067827 ps
T64 /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3548388434 May 09 02:31:06 PM PDT 24 May 09 02:31:11 PM PDT 24 34075935 ps
T89 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2751562579 May 09 02:30:55 PM PDT 24 May 09 02:30:59 PM PDT 24 22435196 ps
T942 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2663515950 May 09 02:31:03 PM PDT 24 May 09 02:31:10 PM PDT 24 345378029 ps
T90 /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.83409100 May 09 02:31:03 PM PDT 24 May 09 02:31:07 PM PDT 24 14205261 ps
T65 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2122807642 May 09 02:31:03 PM PDT 24 May 09 02:31:08 PM PDT 24 350494980 ps
T66 /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1596330571 May 09 02:31:07 PM PDT 24 May 09 02:31:39 PM PDT 24 3813782790 ps
T95 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1846122116 May 09 02:31:05 PM PDT 24 May 09 02:31:12 PM PDT 24 2197921350 ps
T943 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2784155575 May 09 02:30:58 PM PDT 24 May 09 02:31:06 PM PDT 24 748388181 ps
T94 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3049827880 May 09 02:30:56 PM PDT 24 May 09 02:31:00 PM PDT 24 14101636 ps
T67 /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1410327910 May 09 02:31:07 PM PDT 24 May 09 02:31:39 PM PDT 24 14193200840 ps
T944 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1782582138 May 09 02:31:05 PM PDT 24 May 09 02:31:13 PM PDT 24 346404961 ps
T68 /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3569254921 May 09 02:31:00 PM PDT 24 May 09 02:32:16 PM PDT 24 64040343880 ps
T69 /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.952697605 May 09 02:31:03 PM PDT 24 May 09 02:32:08 PM PDT 24 70402801308 ps
T70 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1219816502 May 09 02:31:11 PM PDT 24 May 09 02:31:19 PM PDT 24 21981787 ps
T96 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.4265893916 May 09 02:31:13 PM PDT 24 May 09 02:31:22 PM PDT 24 244946769 ps
T71 /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.249605134 May 09 02:31:03 PM PDT 24 May 09 02:31:38 PM PDT 24 15380298086 ps
T945 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3091473729 May 09 02:31:07 PM PDT 24 May 09 02:31:13 PM PDT 24 14443333 ps
T946 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1509046809 May 09 02:31:01 PM PDT 24 May 09 02:31:08 PM PDT 24 98515948 ps
T947 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3089400005 May 09 02:30:57 PM PDT 24 May 09 02:31:02 PM PDT 24 295975494 ps
T948 /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1555366131 May 09 02:31:08 PM PDT 24 May 09 02:31:48 PM PDT 24 18415715332 ps
T73 /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3730624893 May 09 02:31:03 PM PDT 24 May 09 02:31:54 PM PDT 24 7188831776 ps
T949 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.4087115234 May 09 02:31:00 PM PDT 24 May 09 02:31:04 PM PDT 24 35842786 ps
T950 /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2176388478 May 09 02:31:06 PM PDT 24 May 09 02:31:12 PM PDT 24 44219184 ps
T97 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3162834195 May 09 02:30:56 PM PDT 24 May 09 02:31:02 PM PDT 24 252636091 ps
T83 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2311785580 May 09 02:30:55 PM PDT 24 May 09 02:30:59 PM PDT 24 35639852 ps
T111 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.545498322 May 09 02:30:55 PM PDT 24 May 09 02:30:59 PM PDT 24 370344540 ps
T112 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2481022850 May 09 02:31:09 PM PDT 24 May 09 02:31:16 PM PDT 24 83206925 ps
T951 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2253905011 May 09 02:31:08 PM PDT 24 May 09 02:31:14 PM PDT 24 14018229 ps
T952 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.269786528 May 09 02:31:07 PM PDT 24 May 09 02:31:16 PM PDT 24 411020074 ps
T74 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2520113405 May 09 02:31:06 PM PDT 24 May 09 02:31:12 PM PDT 24 26705837 ps
T953 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1473336554 May 09 02:31:13 PM PDT 24 May 09 02:31:23 PM PDT 24 151431228 ps
T954 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1637113771 May 09 02:30:53 PM PDT 24 May 09 02:30:58 PM PDT 24 1474525216 ps
T955 /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3323327505 May 09 02:31:07 PM PDT 24 May 09 02:31:13 PM PDT 24 38457059 ps
T956 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3160330126 May 09 02:31:03 PM PDT 24 May 09 02:31:10 PM PDT 24 110790419 ps
T957 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3541541172 May 09 02:30:56 PM PDT 24 May 09 02:30:59 PM PDT 24 48446067 ps
T958 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1840553896 May 09 02:31:16 PM PDT 24 May 09 02:31:26 PM PDT 24 355841982 ps
T959 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3877909499 May 09 02:31:08 PM PDT 24 May 09 02:31:15 PM PDT 24 19496835 ps
T960 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.952467867 May 09 02:31:04 PM PDT 24 May 09 02:31:10 PM PDT 24 886465626 ps
T961 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3004368440 May 09 02:31:07 PM PDT 24 May 09 02:31:16 PM PDT 24 1561916394 ps
T75 /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.349587580 May 09 02:31:11 PM PDT 24 May 09 02:31:47 PM PDT 24 6244829652 ps
T962 /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2166214569 May 09 02:31:04 PM PDT 24 May 09 02:31:09 PM PDT 24 24354672 ps
T107 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1867418657 May 09 02:31:06 PM PDT 24 May 09 02:31:12 PM PDT 24 255988763 ps
T119 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.524708614 May 09 02:31:05 PM PDT 24 May 09 02:31:12 PM PDT 24 467976182 ps
T963 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3636617577 May 09 02:31:06 PM PDT 24 May 09 02:31:15 PM PDT 24 1437117143 ps
T964 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.591524871 May 09 02:31:09 PM PDT 24 May 09 02:31:15 PM PDT 24 14979227 ps
T108 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1598332887 May 09 02:30:57 PM PDT 24 May 09 02:31:03 PM PDT 24 536175176 ps
T113 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3857218427 May 09 02:31:13 PM PDT 24 May 09 02:31:22 PM PDT 24 144595189 ps
T965 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1213337968 May 09 02:31:05 PM PDT 24 May 09 02:31:10 PM PDT 24 17249509 ps
T966 /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3511420147 May 09 02:30:56 PM PDT 24 May 09 02:31:00 PM PDT 24 16778345 ps
T76 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2801693746 May 09 02:30:56 PM PDT 24 May 09 02:31:00 PM PDT 24 17268262 ps
T967 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1113343671 May 09 02:31:15 PM PDT 24 May 09 02:31:24 PM PDT 24 68603850 ps
T968 /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.4131410285 May 09 02:31:07 PM PDT 24 May 09 02:31:14 PM PDT 24 17328133 ps
T969 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1511665302 May 09 02:31:09 PM PDT 24 May 09 02:31:19 PM PDT 24 1439310029 ps
T970 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1620287530 May 09 02:30:56 PM PDT 24 May 09 02:31:03 PM PDT 24 134172607 ps
T971 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2680070256 May 09 02:31:09 PM PDT 24 May 09 02:31:18 PM PDT 24 369086002 ps
T86 /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1895988100 May 09 02:31:10 PM PDT 24 May 09 02:32:09 PM PDT 24 7718902905 ps
T972 /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2584540468 May 09 02:31:08 PM PDT 24 May 09 02:31:14 PM PDT 24 239211446 ps
T973 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2644726240 May 09 02:31:17 PM PDT 24 May 09 02:31:24 PM PDT 24 12602261 ps
T974 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3233375142 May 09 02:31:07 PM PDT 24 May 09 02:31:16 PM PDT 24 941395260 ps
T975 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.369705895 May 09 02:31:13 PM PDT 24 May 09 02:31:25 PM PDT 24 1427829850 ps
T84 /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1859326279 May 09 02:31:11 PM PDT 24 May 09 02:32:09 PM PDT 24 7376413774 ps
T85 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2383989959 May 09 02:31:10 PM PDT 24 May 09 02:31:18 PM PDT 24 30461423 ps
T976 /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.824045609 May 09 02:30:58 PM PDT 24 May 09 02:31:02 PM PDT 24 19584167 ps
T977 /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2882076396 May 09 02:31:10 PM PDT 24 May 09 02:31:43 PM PDT 24 3813679310 ps
T978 /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3621563746 May 09 02:31:16 PM PDT 24 May 09 02:31:23 PM PDT 24 39218064 ps
T979 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2738736185 May 09 02:30:56 PM PDT 24 May 09 02:30:59 PM PDT 24 11273747 ps
T980 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.4025237734 May 09 02:31:12 PM PDT 24 May 09 02:31:20 PM PDT 24 19775657 ps
T981 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3987452170 May 09 02:31:13 PM PDT 24 May 09 02:31:22 PM PDT 24 26818195 ps
T982 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.124138670 May 09 02:31:09 PM PDT 24 May 09 02:31:15 PM PDT 24 15951844 ps
T115 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3595077248 May 09 02:31:13 PM PDT 24 May 09 02:31:22 PM PDT 24 163188942 ps
T983 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1051663893 May 09 02:31:13 PM PDT 24 May 09 02:31:23 PM PDT 24 818372478 ps
T984 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2980310687 May 09 02:30:54 PM PDT 24 May 09 02:30:57 PM PDT 24 97096249 ps
T985 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3641873562 May 09 02:30:56 PM PDT 24 May 09 02:31:01 PM PDT 24 303514631 ps
T986 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3432337463 May 09 02:31:03 PM PDT 24 May 09 02:31:07 PM PDT 24 17358155 ps
T114 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2440627009 May 09 02:30:56 PM PDT 24 May 09 02:31:02 PM PDT 24 330619576 ps
T987 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1776913313 May 09 02:31:07 PM PDT 24 May 09 02:31:14 PM PDT 24 17184039 ps
T109 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.888182862 May 09 02:31:08 PM PDT 24 May 09 02:31:15 PM PDT 24 82721549 ps
T988 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2044520333 May 09 02:31:03 PM PDT 24 May 09 02:31:09 PM PDT 24 68752880 ps
T118 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.338223840 May 09 02:31:06 PM PDT 24 May 09 02:31:12 PM PDT 24 388995307 ps
T120 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.4039610842 May 09 02:31:02 PM PDT 24 May 09 02:31:07 PM PDT 24 322393844 ps
T989 /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.4230261151 May 09 02:31:16 PM PDT 24 May 09 02:31:51 PM PDT 24 14777579686 ps
T990 /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.4068962371 May 09 02:31:06 PM PDT 24 May 09 02:32:07 PM PDT 24 14380536184 ps
T991 /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3714037877 May 09 02:31:07 PM PDT 24 May 09 02:32:05 PM PDT 24 7359373959 ps
T992 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.126974300 May 09 02:30:56 PM PDT 24 May 09 02:31:00 PM PDT 24 97235755 ps
T993 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.126268814 May 09 02:30:54 PM PDT 24 May 09 02:30:57 PM PDT 24 15047086 ps
T994 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1332830027 May 09 02:31:07 PM PDT 24 May 09 02:31:16 PM PDT 24 1549966810 ps
T995 /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.344094086 May 09 02:31:08 PM PDT 24 May 09 02:31:14 PM PDT 24 24281722 ps
T996 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1505340690 May 09 02:31:15 PM PDT 24 May 09 02:31:23 PM PDT 24 14992300 ps
T997 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2543193935 May 09 02:31:14 PM PDT 24 May 09 02:31:23 PM PDT 24 22891724 ps
T998 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.643667 May 09 02:31:03 PM PDT 24 May 09 02:31:09 PM PDT 24 112447494 ps
T999 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1864436960 May 09 02:30:56 PM PDT 24 May 09 02:30:59 PM PDT 24 58240974 ps
T1000 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1460547940 May 09 02:30:53 PM PDT 24 May 09 02:30:58 PM PDT 24 1467501490 ps
T1001 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3916597312 May 09 02:31:13 PM PDT 24 May 09 02:31:22 PM PDT 24 132807715 ps
T1002 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2123564452 May 09 02:31:07 PM PDT 24 May 09 02:31:17 PM PDT 24 370402500 ps
T1003 /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3280042241 May 09 02:31:13 PM PDT 24 May 09 02:31:21 PM PDT 24 177807699 ps
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