Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	339505296	1			T1	431398		T2	328126		T3	20000
instr_valid_dis	292783027	1			T1	431398		T2	328126		T3	20000
instr_en	33521206	1			T4	48394		T10	277698		T14	180504

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	17398419	1			T1	97578		T4	111096		T10	12734
sram_ifetch_valid_disable	289741947	1			T1	152742		T2	328126		T3	20000
sram_ifetch_enable	32364930	1			T1	181078		T4	260092		T10	63890

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	339505296	1			T1	431398		T2	328126		T3	20000
hw_debug_en_valid_off	289691923	1			T1	168806		T2	328126		T3	20000
hw_debug_en_on	35224157	1			T1	254212		T4	242038		T10	101986

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	289741947	1			T1	152742		T2	328126		T3	20000
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	272027582	1			T1	152742		T2	328126		T3	20000
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	13037483	1			T4	48394		T10	201074		T14	51710
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4823174	1			T1	30702		T4	218		T14	47162
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1872976	1			T1	30702		T4	218		T14	15486
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2215686	1			T14	19496		T9	14274		T24	185562
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	9048787	1			T1	66876		T4	110878		T10	12734
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	3599010	1			T1	66876		T4	110878		T48	98136
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	4756361	1			T10	12734		T9	10478		T24	44336
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	11504895	1			T1	58260		T4	88012		T10	45362
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3936834	1			T1	58260		T4	88012		T10	74
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	5890250	1			T10	45288		T14	18474		T122	8652

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	12705100	1			T10	63890		T14	109298		T67	51028
lc_exec_en	14670475	1			T1	129076		T4	43148		T10	43890
valid_exec_dis	288433895	1			T1	275560		T2	328126		T3	20000
invalid_exec_dis	49763349	1			T1	278656		T4	371188		T10	76624