Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.09	99.81	96.99	100.00	100.00	98.60	99.70	98.52

Total tests in report: 1038

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
80.54	80.54	97.66	97.66	80.00	80.00	79.76	79.76	71.43	71.43	90.42	90.42	94.80	94.80	49.72	49.72	/workspace/coverage/default/2.sram_ctrl_regwen.2310670897
88.78	8.24	97.75	0.09	87.53	7.53	92.90	13.14	71.43	0.00	93.80	3.38	96.58	1.78	81.45	31.73	/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.2139031500
94.62	5.84	99.06	1.31	90.00	2.47	96.52	3.62	100.00	28.57	96.90	3.10	96.73	0.15	83.12	1.67	/workspace/coverage/default/32.sram_ctrl_lc_escalation.547710998
95.58	0.96	99.44	0.37	92.21	2.21	97.44	0.92	100.00	0.00	98.59	1.69	97.33	0.59	84.04	0.93	/workspace/coverage/default/2.sram_ctrl_sec_cm.2325538368
96.30	0.72	99.44	0.00	92.60	0.39	97.44	0.00	100.00	0.00	98.59	0.00	97.33	0.00	88.68	4.64	/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.4031097840
96.81	0.51	99.44	0.00	92.86	0.26	98.44	0.99	100.00	0.00	98.87	0.28	97.33	0.00	90.72	2.04	/workspace/coverage/default/18.sram_ctrl_regwen.1962600088
97.23	0.42	99.44	0.00	92.86	0.00	98.44	0.00	100.00	0.00	98.87	0.00	97.47	0.15	93.51	2.78	/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.3392911425
97.59	0.36	99.44	0.00	92.99	0.13	98.97	0.53	100.00	0.00	98.87	0.00	97.47	0.00	95.36	1.86	/workspace/coverage/default/38.sram_ctrl_stress_all.400541993
97.86	0.27	99.44	0.00	93.25	0.26	99.04	0.07	100.00	0.00	98.87	0.00	98.66	1.19	95.73	0.37	/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.508949871
98.04	0.18	99.44	0.00	93.38	0.13	99.08	0.04	100.00	0.00	98.87	0.00	99.41	0.74	96.10	0.37	/workspace/coverage/default/1.sram_ctrl_access_during_key_req.2008360848
98.17	0.13	99.44	0.00	93.38	0.00	99.08	0.00	100.00	0.00	98.87	0.00	99.41	0.00	97.03	0.93	/workspace/coverage/default/36.sram_ctrl_stress_all.1115756019
98.29	0.12	99.53	0.09	93.38	0.00	99.82	0.75	100.00	0.00	98.87	0.00	99.41	0.00	97.03	0.00	/workspace/coverage/default/5.sram_ctrl_ram_cfg.3900446086
98.40	0.11	99.53	0.00	93.38	0.00	99.82	0.00	100.00	0.00	98.87	0.00	99.41	0.00	97.77	0.74	/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3921879846
98.50	0.11	99.81	0.28	93.77	0.39	99.89	0.07	100.00	0.00	98.87	0.00	99.41	0.00	97.77	0.00	/workspace/coverage/default/41.sram_ctrl_alert_test.3976896793
98.56	0.05	99.81	0.00	93.77	0.00	99.89	0.00	100.00	0.00	98.87	0.00	99.41	0.00	98.14	0.37	/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2855266652
98.59	0.04	99.81	0.00	94.03	0.26	99.89	0.00	100.00	0.00	98.87	0.00	99.41	0.00	98.14	0.00	/workspace/coverage/default/15.sram_ctrl_stress_all.791369493
98.62	0.03	99.81	0.00	94.16	0.13	99.96	0.07	100.00	0.00	98.87	0.00	99.41	0.00	98.14	0.00	/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2385332879
98.65	0.03	99.81	0.00	94.16	0.00	99.96	0.00	100.00	0.00	98.87	0.00	99.41	0.00	98.33	0.19	/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3643281977
98.68	0.03	99.81	0.00	94.16	0.00	99.96	0.00	100.00	0.00	98.87	0.00	99.41	0.00	98.52	0.19	/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.4208142939
98.70	0.02	99.81	0.00	94.16	0.00	99.96	0.00	100.00	0.00	98.87	0.00	99.55	0.15	98.52	0.00	/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1032328403
98.72	0.02	99.81	0.00	94.16	0.00	99.96	0.00	100.00	0.00	98.87	0.00	99.70	0.15	98.52	0.00	/workspace/coverage/default/13.sram_ctrl_access_during_key_req.4000441107
98.72	0.01	99.81	0.00	94.16	0.00	100.00	0.04	100.00	0.00	98.87	0.00	99.70	0.00	98.52	0.00	/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.2213578451

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3011717613
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1920334605
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2242093639
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.450105639
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.557493932
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3032091802
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2352204013
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1966620460
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2589697538
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3868755753
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2959613092
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3961119432
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2838304971
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2904461197
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2135045538
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1908873436
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2451029023
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3331878737
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.221328660
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.573928920
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.952737992
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2185096556
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1064135714
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1007750781
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.996416182
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2916159837
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2238610415
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1303431529
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3777533198
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3340693081
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1648902881
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2476923875
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.889573040
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2626666766
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3954702809
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2218812733
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.4292063646
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1461766852
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1381011423
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1399744141
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.53390730
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.4032000215
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3621317408
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.431581292
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1642391338
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2859111118
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1530281325
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1159411681
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.4064891162
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2277313635
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1850511487
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1712108748
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2216173717
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1637993174
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2326735842
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1636917658
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2233472326
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2892074616
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2968303454
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1247405669
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3573630162
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2472825716
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2680175474
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.691460162
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.600042421
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2189921132
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2547791119
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2828173371
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3353845404
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2889578506
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1916289633
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.419357227
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3826503157
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.453406553
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2532377884
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1504406087
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2114352961
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.939312730
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1631107818
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.479852786
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3261422229
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1029802104
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3833158655
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3692136876
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.4151396085
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2822267554
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3566837696
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2269834780
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.4168307448
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.4256513440
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3773811470
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.651182099
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2969153837
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1698454559
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3593032246
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1659411149
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.327629508
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3052477454
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.49887407
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.159205292
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1046938742
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1817755074
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1053355036
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.388944595
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1818422833
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1642411552
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.356621588
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.278813525
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3458356488
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2764716339
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.4087731948
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1117087079
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2032486489
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2943868295
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1764611221
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.305800621
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2503646791
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.736913082
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.754435622
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2771245841
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.772030935
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3908752303
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3252967737
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.4044883678
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3616903960
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3775072561
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2601503211
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3172479978
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.2315347142
/workspace/coverage/default/0.sram_ctrl_alert_test.2904553800
/workspace/coverage/default/0.sram_ctrl_bijection.1513835187
/workspace/coverage/default/0.sram_ctrl_executable.2942207286
/workspace/coverage/default/0.sram_ctrl_lc_escalation.4151340344
/workspace/coverage/default/0.sram_ctrl_max_throughput.808763618
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.1365050895
/workspace/coverage/default/0.sram_ctrl_mem_walk.317563377
/workspace/coverage/default/0.sram_ctrl_multiple_keys.3008496898
/workspace/coverage/default/0.sram_ctrl_partial_access.2016318192
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.988418820
/workspace/coverage/default/0.sram_ctrl_ram_cfg.2327821030
/workspace/coverage/default/0.sram_ctrl_regwen.2834643796
/workspace/coverage/default/0.sram_ctrl_sec_cm.3195812530
/workspace/coverage/default/0.sram_ctrl_smoke.1278450553
/workspace/coverage/default/0.sram_ctrl_stress_all.1284318201
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.731110302
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.2337360997
/workspace/coverage/default/1.sram_ctrl_alert_test.1565797673
/workspace/coverage/default/1.sram_ctrl_bijection.2567940762
/workspace/coverage/default/1.sram_ctrl_executable.3574670970
/workspace/coverage/default/1.sram_ctrl_lc_escalation.596258490
/workspace/coverage/default/1.sram_ctrl_max_throughput.4111651795
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.2199680685
/workspace/coverage/default/1.sram_ctrl_mem_walk.425519515
/workspace/coverage/default/1.sram_ctrl_multiple_keys.2588489185
/workspace/coverage/default/1.sram_ctrl_partial_access.405970522
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.27274033
/workspace/coverage/default/1.sram_ctrl_ram_cfg.1994529838
/workspace/coverage/default/1.sram_ctrl_regwen.3042939752
/workspace/coverage/default/1.sram_ctrl_sec_cm.2391369342
/workspace/coverage/default/1.sram_ctrl_smoke.4021847774
/workspace/coverage/default/1.sram_ctrl_stress_all.515854398
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3511014991
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.2579723620
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3194507031
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.683122063
/workspace/coverage/default/10.sram_ctrl_alert_test.1278977597
/workspace/coverage/default/10.sram_ctrl_bijection.81096438
/workspace/coverage/default/10.sram_ctrl_executable.3533073238
/workspace/coverage/default/10.sram_ctrl_lc_escalation.3661854673
/workspace/coverage/default/10.sram_ctrl_max_throughput.4019689331
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.971044848
/workspace/coverage/default/10.sram_ctrl_mem_walk.1610412052
/workspace/coverage/default/10.sram_ctrl_multiple_keys.2297913284
/workspace/coverage/default/10.sram_ctrl_partial_access.1141712798
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.132656295
/workspace/coverage/default/10.sram_ctrl_ram_cfg.181462107
/workspace/coverage/default/10.sram_ctrl_regwen.1489547921
/workspace/coverage/default/10.sram_ctrl_smoke.3038845025
/workspace/coverage/default/10.sram_ctrl_stress_all.2715120842
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3844523182
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.2859683108
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2520839036
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.390970957
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/workspace/coverage/default/41.sram_ctrl_smoke.3125473968
/workspace/coverage/default/41.sram_ctrl_stress_all.2258805020
/workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.3253373285
/workspace/coverage/default/41.sram_ctrl_stress_pipeline.2104910651
/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.2454634965
/workspace/coverage/default/42.sram_ctrl_access_during_key_req.3280960391
/workspace/coverage/default/42.sram_ctrl_alert_test.3547965014
/workspace/coverage/default/42.sram_ctrl_bijection.3576846248
/workspace/coverage/default/42.sram_ctrl_executable.1338921498
/workspace/coverage/default/42.sram_ctrl_lc_escalation.1880263267
/workspace/coverage/default/42.sram_ctrl_max_throughput.2273623209
/workspace/coverage/default/42.sram_ctrl_mem_partial_access.3180104891
/workspace/coverage/default/42.sram_ctrl_mem_walk.3124068580
/workspace/coverage/default/42.sram_ctrl_multiple_keys.1817623411
/workspace/coverage/default/42.sram_ctrl_partial_access.4032812010
/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.2741332753
/workspace/coverage/default/42.sram_ctrl_ram_cfg.620130023
/workspace/coverage/default/42.sram_ctrl_regwen.3131437987
/workspace/coverage/default/42.sram_ctrl_smoke.799689033
/workspace/coverage/default/42.sram_ctrl_stress_all.975840016
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.916866807
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.2017764713
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.1497343862
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.22501591
/workspace/coverage/default/43.sram_ctrl_alert_test.535779046
/workspace/coverage/default/43.sram_ctrl_bijection.2920057387
/workspace/coverage/default/43.sram_ctrl_executable.3272164682
/workspace/coverage/default/43.sram_ctrl_lc_escalation.2681295960
/workspace/coverage/default/43.sram_ctrl_max_throughput.421810885
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.3101254315
/workspace/coverage/default/43.sram_ctrl_mem_walk.1178839580
/workspace/coverage/default/43.sram_ctrl_multiple_keys.2967122816
/workspace/coverage/default/43.sram_ctrl_partial_access.1483637963
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.4071589080
/workspace/coverage/default/43.sram_ctrl_ram_cfg.144381129
/workspace/coverage/default/43.sram_ctrl_regwen.1049469528
/workspace/coverage/default/43.sram_ctrl_smoke.148650770
/workspace/coverage/default/43.sram_ctrl_stress_all.161043071
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.3646504415
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.1435905629
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.2960261772
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.3185755688
/workspace/coverage/default/44.sram_ctrl_alert_test.585993131
/workspace/coverage/default/44.sram_ctrl_bijection.485850886
/workspace/coverage/default/44.sram_ctrl_executable.969406386
/workspace/coverage/default/44.sram_ctrl_lc_escalation.1475835912
/workspace/coverage/default/44.sram_ctrl_max_throughput.3965045666
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.1527691584
/workspace/coverage/default/44.sram_ctrl_mem_walk.795129646
/workspace/coverage/default/44.sram_ctrl_multiple_keys.3746551193
/workspace/coverage/default/44.sram_ctrl_partial_access.2535821369
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.906551110
/workspace/coverage/default/44.sram_ctrl_ram_cfg.2643321916
/workspace/coverage/default/44.sram_ctrl_regwen.2886479051
/workspace/coverage/default/44.sram_ctrl_smoke.4163660969
/workspace/coverage/default/44.sram_ctrl_stress_all.1275103140
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.2403528677
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.2743168090
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.2313427192
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.1488393561
/workspace/coverage/default/45.sram_ctrl_alert_test.2411425634
/workspace/coverage/default/45.sram_ctrl_bijection.3218478852
/workspace/coverage/default/45.sram_ctrl_executable.496183120
/workspace/coverage/default/45.sram_ctrl_lc_escalation.1750651239
/workspace/coverage/default/45.sram_ctrl_max_throughput.3007969157
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.3222080057
/workspace/coverage/default/45.sram_ctrl_mem_walk.2986404951
/workspace/coverage/default/45.sram_ctrl_multiple_keys.3100449800
/workspace/coverage/default/45.sram_ctrl_partial_access.1806672332
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.305126935
/workspace/coverage/default/45.sram_ctrl_ram_cfg.1219455203
/workspace/coverage/default/45.sram_ctrl_regwen.3557551311
/workspace/coverage/default/45.sram_ctrl_smoke.398020588
/workspace/coverage/default/45.sram_ctrl_stress_all.39597453
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3747114353
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.2594000363
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.953998806
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.3184586283
/workspace/coverage/default/46.sram_ctrl_alert_test.1289715737
/workspace/coverage/default/46.sram_ctrl_bijection.1606351343
/workspace/coverage/default/46.sram_ctrl_executable.2369360434
/workspace/coverage/default/46.sram_ctrl_lc_escalation.3727448539
/workspace/coverage/default/46.sram_ctrl_max_throughput.55317321
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.128528489
/workspace/coverage/default/46.sram_ctrl_mem_walk.4074934045
/workspace/coverage/default/46.sram_ctrl_multiple_keys.3050774879
/workspace/coverage/default/46.sram_ctrl_partial_access.284464259
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.813172567
/workspace/coverage/default/46.sram_ctrl_ram_cfg.1514269763
/workspace/coverage/default/46.sram_ctrl_regwen.3726868405
/workspace/coverage/default/46.sram_ctrl_smoke.3823763826
/workspace/coverage/default/46.sram_ctrl_stress_all.1345724566
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2900657969
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.2715359401
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.2963577164
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.3016901806
/workspace/coverage/default/47.sram_ctrl_alert_test.177418726
/workspace/coverage/default/47.sram_ctrl_bijection.655109231
/workspace/coverage/default/47.sram_ctrl_executable.3354754724
/workspace/coverage/default/47.sram_ctrl_lc_escalation.1317268491
/workspace/coverage/default/47.sram_ctrl_max_throughput.3028394924
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.2044449732
/workspace/coverage/default/47.sram_ctrl_mem_walk.2229494652
/workspace/coverage/default/47.sram_ctrl_multiple_keys.499450938
/workspace/coverage/default/47.sram_ctrl_partial_access.3444998557
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2658893536
/workspace/coverage/default/47.sram_ctrl_ram_cfg.1542787073
/workspace/coverage/default/47.sram_ctrl_regwen.2559565364
/workspace/coverage/default/47.sram_ctrl_smoke.2482400639
/workspace/coverage/default/47.sram_ctrl_stress_all.2492898788
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.2390012490
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.826911449
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.3490224839
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.4232737387
/workspace/coverage/default/48.sram_ctrl_alert_test.3206728016
/workspace/coverage/default/48.sram_ctrl_bijection.1149891806
/workspace/coverage/default/48.sram_ctrl_executable.3941114630
/workspace/coverage/default/48.sram_ctrl_lc_escalation.1114881615
/workspace/coverage/default/48.sram_ctrl_max_throughput.2236658116
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.4058787023
/workspace/coverage/default/48.sram_ctrl_mem_walk.4129619737
/workspace/coverage/default/48.sram_ctrl_multiple_keys.3103491284
/workspace/coverage/default/48.sram_ctrl_partial_access.3117660925
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3382674181
/workspace/coverage/default/48.sram_ctrl_ram_cfg.2530593130
/workspace/coverage/default/48.sram_ctrl_regwen.1676878899
/workspace/coverage/default/48.sram_ctrl_smoke.1594472538
/workspace/coverage/default/48.sram_ctrl_stress_all.813207738
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.2285711357
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.747644520
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.787623071
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.2137367530
/workspace/coverage/default/49.sram_ctrl_alert_test.2430835199
/workspace/coverage/default/49.sram_ctrl_bijection.3632866026
/workspace/coverage/default/49.sram_ctrl_executable.196957871
/workspace/coverage/default/49.sram_ctrl_lc_escalation.1585015023
/workspace/coverage/default/49.sram_ctrl_max_throughput.663034560
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.4041777224
/workspace/coverage/default/49.sram_ctrl_mem_walk.3878239538
/workspace/coverage/default/49.sram_ctrl_multiple_keys.3678352507
/workspace/coverage/default/49.sram_ctrl_partial_access.1814050787
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.2506594439
/workspace/coverage/default/49.sram_ctrl_ram_cfg.220573048
/workspace/coverage/default/49.sram_ctrl_regwen.896432881
/workspace/coverage/default/49.sram_ctrl_smoke.2263279966
/workspace/coverage/default/49.sram_ctrl_stress_all.2826079433
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.2880597559
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.2821311796
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.3080438605
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.3638264737
/workspace/coverage/default/5.sram_ctrl_alert_test.1592722448
/workspace/coverage/default/5.sram_ctrl_bijection.678971648
/workspace/coverage/default/5.sram_ctrl_executable.2699605740
/workspace/coverage/default/5.sram_ctrl_lc_escalation.2104185045
/workspace/coverage/default/5.sram_ctrl_max_throughput.2657825513
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.2918887807
/workspace/coverage/default/5.sram_ctrl_mem_walk.912518634
/workspace/coverage/default/5.sram_ctrl_multiple_keys.3302660332
/workspace/coverage/default/5.sram_ctrl_partial_access.3579257039
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.168810944
/workspace/coverage/default/5.sram_ctrl_regwen.2807748004
/workspace/coverage/default/5.sram_ctrl_smoke.2736606834
/workspace/coverage/default/5.sram_ctrl_stress_all.108861043
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.4286323437
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.4129835484
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.2578882458
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.2801964308
/workspace/coverage/default/6.sram_ctrl_alert_test.2027225262
/workspace/coverage/default/6.sram_ctrl_bijection.1751417315
/workspace/coverage/default/6.sram_ctrl_executable.3777100488
/workspace/coverage/default/6.sram_ctrl_lc_escalation.3025575008
/workspace/coverage/default/6.sram_ctrl_max_throughput.1272142629
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.3746803706
/workspace/coverage/default/6.sram_ctrl_mem_walk.686004812
/workspace/coverage/default/6.sram_ctrl_multiple_keys.3352160934
/workspace/coverage/default/6.sram_ctrl_partial_access.2166784852
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.3543298453
/workspace/coverage/default/6.sram_ctrl_ram_cfg.3353893531
/workspace/coverage/default/6.sram_ctrl_regwen.191662412
/workspace/coverage/default/6.sram_ctrl_smoke.2567753810
/workspace/coverage/default/6.sram_ctrl_stress_all.1645530547
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.119931566
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.545376874
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.498818879
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.4043760721
/workspace/coverage/default/7.sram_ctrl_alert_test.1740414015
/workspace/coverage/default/7.sram_ctrl_bijection.3489000276
/workspace/coverage/default/7.sram_ctrl_executable.3648267166
/workspace/coverage/default/7.sram_ctrl_lc_escalation.2893694874
/workspace/coverage/default/7.sram_ctrl_max_throughput.2983209411
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.512026097
/workspace/coverage/default/7.sram_ctrl_mem_walk.794274951
/workspace/coverage/default/7.sram_ctrl_multiple_keys.884143298
/workspace/coverage/default/7.sram_ctrl_partial_access.1059405521
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.794470747
/workspace/coverage/default/7.sram_ctrl_ram_cfg.797331536
/workspace/coverage/default/7.sram_ctrl_regwen.2317082964
/workspace/coverage/default/7.sram_ctrl_smoke.47581401
/workspace/coverage/default/7.sram_ctrl_stress_all.2556699738
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.1079487131
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.1487398902
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2140581640
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.2463316242
/workspace/coverage/default/8.sram_ctrl_alert_test.3872633025
/workspace/coverage/default/8.sram_ctrl_bijection.3263998736
/workspace/coverage/default/8.sram_ctrl_executable.4118259058
/workspace/coverage/default/8.sram_ctrl_lc_escalation.1888563337
/workspace/coverage/default/8.sram_ctrl_max_throughput.540525354
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.3404772889
/workspace/coverage/default/8.sram_ctrl_mem_walk.294544038
/workspace/coverage/default/8.sram_ctrl_multiple_keys.1747710106
/workspace/coverage/default/8.sram_ctrl_partial_access.968863437
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.3613157074
/workspace/coverage/default/8.sram_ctrl_ram_cfg.2381001426
/workspace/coverage/default/8.sram_ctrl_regwen.1985788131
/workspace/coverage/default/8.sram_ctrl_smoke.1142985660
/workspace/coverage/default/8.sram_ctrl_stress_all.915475011
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2946987251
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.2284920285
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2172136922
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.2902960049
/workspace/coverage/default/9.sram_ctrl_alert_test.590774586
/workspace/coverage/default/9.sram_ctrl_bijection.2463655459
/workspace/coverage/default/9.sram_ctrl_executable.1887228992
/workspace/coverage/default/9.sram_ctrl_lc_escalation.2957349299
/workspace/coverage/default/9.sram_ctrl_max_throughput.2349118539
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.143724007
/workspace/coverage/default/9.sram_ctrl_mem_walk.4021735925
/workspace/coverage/default/9.sram_ctrl_multiple_keys.2051146392
/workspace/coverage/default/9.sram_ctrl_partial_access.1172128536
/workspace/coverage/default/9.sram_ctrl_ram_cfg.234373768
/workspace/coverage/default/9.sram_ctrl_regwen.2442672860
/workspace/coverage/default/9.sram_ctrl_smoke.3896618482
/workspace/coverage/default/9.sram_ctrl_stress_all.2521493274
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3314447987
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.1904857653
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3564939370

Total test records in report: 1038

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/2.sram_ctrl_regwen.2310670897	May 12 01:06:41 PM PDT 24	May 12 01:22:23 PM PDT 24	9121959568 ps
T2	/workspace/coverage/default/6.sram_ctrl_stress_pipeline.545376874	May 12 01:06:49 PM PDT 24	May 12 01:10:07 PM PDT 24	12150981902 ps
T3	/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.2213578451	May 12 01:07:14 PM PDT 24	May 12 01:09:12 PM PDT 24	802834642 ps
T4	/workspace/coverage/default/31.sram_ctrl_regwen.2725132667	May 12 01:09:47 PM PDT 24	May 12 01:47:25 PM PDT 24	23669777580 ps
T5	/workspace/coverage/default/47.sram_ctrl_stress_pipeline.826911449	May 12 01:12:31 PM PDT 24	May 12 01:15:29 PM PDT 24	3308075825 ps
T6	/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.721691593	May 12 01:07:21 PM PDT 24	May 12 01:07:41 PM PDT 24	1619150432 ps
T10	/workspace/coverage/default/49.sram_ctrl_regwen.896432881	May 12 01:13:02 PM PDT 24	May 12 01:23:00 PM PDT 24	42959735997 ps
T11	/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2140581640	May 12 01:06:53 PM PDT 24	May 12 01:07:12 PM PDT 24	1496170305 ps
T12	/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.1887474646	May 12 01:10:34 PM PDT 24	May 12 01:13:56 PM PDT 24	43617857469 ps
T13	/workspace/coverage/default/13.sram_ctrl_bijection.2032003852	May 12 01:07:17 PM PDT 24	May 12 01:44:47 PM PDT 24	230212063986 ps
T27	/workspace/coverage/default/5.sram_ctrl_ram_cfg.3900446086	May 12 01:06:48 PM PDT 24	May 12 01:06:52 PM PDT 24	736543028 ps
T7	/workspace/coverage/default/32.sram_ctrl_lc_escalation.547710998	May 12 01:09:57 PM PDT 24	May 12 01:10:12 PM PDT 24	2431637295 ps
T16	/workspace/coverage/default/18.sram_ctrl_smoke.4212060019	May 12 01:07:49 PM PDT 24	May 12 01:07:58 PM PDT 24	427086158 ps
T14	/workspace/coverage/default/33.sram_ctrl_executable.1308733817	May 12 01:10:09 PM PDT 24	May 12 01:33:04 PM PDT 24	23958728094 ps
T15	/workspace/coverage/default/18.sram_ctrl_regwen.1962600088	May 12 01:07:50 PM PDT 24	May 12 01:27:17 PM PDT 24	16608655716 ps
T25	/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.2139031500	May 12 01:10:08 PM PDT 24	May 12 01:10:23 PM PDT 24	1634148079 ps
T48	/workspace/coverage/default/8.sram_ctrl_regwen.1985788131	May 12 01:07:04 PM PDT 24	May 12 01:15:55 PM PDT 24	31260758334 ps
T28	/workspace/coverage/default/6.sram_ctrl_ram_cfg.3353893531	May 12 01:06:48 PM PDT 24	May 12 01:06:52 PM PDT 24	353164779 ps
T131	/workspace/coverage/default/20.sram_ctrl_smoke.2522768276	May 12 01:08:05 PM PDT 24	May 12 01:10:31 PM PDT 24	927180061 ps
T59	/workspace/coverage/default/28.sram_ctrl_smoke.762094013	May 12 01:09:12 PM PDT 24	May 12 01:09:50 PM PDT 24	3076207974 ps
T60	/workspace/coverage/default/12.sram_ctrl_partial_access.3040038594	May 12 01:07:16 PM PDT 24	May 12 01:07:34 PM PDT 24	1188757670 ps
T20	/workspace/coverage/default/41.sram_ctrl_alert_test.3976896793	May 12 01:11:31 PM PDT 24	May 12 01:11:32 PM PDT 24	39493523 ps
T89	/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.1911319933	May 12 01:07:46 PM PDT 24	May 12 01:12:21 PM PDT 24	4773555895 ps
T122	/workspace/coverage/default/9.sram_ctrl_executable.1887228992	May 12 01:07:08 PM PDT 24	May 12 01:08:47 PM PDT 24	6009449930 ps
T132	/workspace/coverage/default/45.sram_ctrl_mem_walk.2986404951	May 12 01:12:20 PM PDT 24	May 12 01:17:40 PM PDT 24	18437602070 ps
T133	/workspace/coverage/default/9.sram_ctrl_max_throughput.2349118539	May 12 01:07:05 PM PDT 24	May 12 01:07:11 PM PDT 24	727263268 ps
T40	/workspace/coverage/default/1.sram_ctrl_access_during_key_req.2008360848	May 12 01:06:35 PM PDT 24	May 12 01:28:40 PM PDT 24	18281414677 ps
T61	/workspace/coverage/default/26.sram_ctrl_multiple_keys.2496548301	May 12 01:08:53 PM PDT 24	May 12 01:26:33 PM PDT 24	80988582306 ps
T62	/workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.1407214133	May 12 01:09:23 PM PDT 24	May 12 01:10:26 PM PDT 24	15137377260 ps
T63	/workspace/coverage/default/49.sram_ctrl_mem_walk.3878239538	May 12 01:13:03 PM PDT 24	May 12 01:15:18 PM PDT 24	7178051347 ps
T41	/workspace/coverage/default/12.sram_ctrl_access_during_key_req.2643744600	May 12 01:07:14 PM PDT 24	May 12 01:13:31 PM PDT 24	30561606493 ps
T42	/workspace/coverage/default/13.sram_ctrl_access_during_key_req.4000441107	May 12 01:07:17 PM PDT 24	May 12 01:24:28 PM PDT 24	17085010437 ps
T64	/workspace/coverage/default/16.sram_ctrl_partial_access.4075755889	May 12 01:07:35 PM PDT 24	May 12 01:07:52 PM PDT 24	906097102 ps
T65	/workspace/coverage/default/41.sram_ctrl_partial_access.587996663	May 12 01:11:25 PM PDT 24	May 12 01:13:55 PM PDT 24	3876202504 ps
T66	/workspace/coverage/default/33.sram_ctrl_multiple_keys.325337338	May 12 01:10:02 PM PDT 24	May 12 01:21:30 PM PDT 24	10873168710 ps
T67	/workspace/coverage/default/38.sram_ctrl_executable.2071565105	May 12 01:10:57 PM PDT 24	May 12 01:17:06 PM PDT 24	7376921652 ps
T26	/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.3646504415	May 12 01:11:51 PM PDT 24	May 12 01:12:27 PM PDT 24	1137022608 ps
T79	/workspace/coverage/default/47.sram_ctrl_max_throughput.3028394924	May 12 01:12:38 PM PDT 24	May 12 01:13:11 PM PDT 24	2854806462 ps
T80	/workspace/coverage/default/31.sram_ctrl_smoke.1358397906	May 12 01:09:44 PM PDT 24	May 12 01:10:00 PM PDT 24	1120460752 ps
T81	/workspace/coverage/default/45.sram_ctrl_stress_pipeline.2594000363	May 12 01:12:13 PM PDT 24	May 12 01:18:51 PM PDT 24	5583454386 ps
T82	/workspace/coverage/default/8.sram_ctrl_mem_walk.294544038	May 12 01:07:03 PM PDT 24	May 12 01:09:05 PM PDT 24	1978308784 ps
T73	/workspace/coverage/default/36.sram_ctrl_access_during_key_req.821503402	May 12 01:10:38 PM PDT 24	May 12 01:29:51 PM PDT 24	19156498905 ps
T134	/workspace/coverage/default/6.sram_ctrl_partial_access.2166784852	May 12 01:06:56 PM PDT 24	May 12 01:07:06 PM PDT 24	552912015 ps
T135	/workspace/coverage/default/13.sram_ctrl_smoke.411840268	May 12 01:07:17 PM PDT 24	May 12 01:07:32 PM PDT 24	1709976643 ps
T43	/workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.4151116193	May 12 01:08:23 PM PDT 24	May 12 01:09:23 PM PDT 24	2172263539 ps
T90	/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.2741332753	May 12 01:11:35 PM PDT 24	May 12 01:17:34 PM PDT 24	25855513412 ps
T8	/workspace/coverage/default/38.sram_ctrl_stress_all.400541993	May 12 01:11:01 PM PDT 24	May 12 02:21:54 PM PDT 24	35685425416 ps
T9	/workspace/coverage/default/47.sram_ctrl_stress_all.2492898788	May 12 01:12:37 PM PDT 24	May 12 02:26:47 PM PDT 24	74064821946 ps
T136	/workspace/coverage/default/4.sram_ctrl_mem_walk.2552053424	May 12 01:06:46 PM PDT 24	May 12 01:09:37 PM PDT 24	114626389965 ps
T17	/workspace/coverage/default/2.sram_ctrl_sec_cm.2325538368	May 12 01:06:38 PM PDT 24	May 12 01:06:41 PM PDT 24	134130579 ps
T32	/workspace/coverage/default/42.sram_ctrl_max_throughput.2273623209	May 12 01:11:36 PM PDT 24	May 12 01:11:46 PM PDT 24	715953015 ps
T33	/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.446749917	May 12 01:07:16 PM PDT 24	May 12 01:07:30 PM PDT 24	1922365431 ps
T34	/workspace/coverage/default/29.sram_ctrl_mem_partial_access.3162916944	May 12 01:09:29 PM PDT 24	May 12 01:12:07 PM PDT 24	9957705225 ps
T23	/workspace/coverage/default/48.sram_ctrl_lc_escalation.1114881615	May 12 01:12:53 PM PDT 24	May 12 01:14:08 PM PDT 24	11994357498 ps
T35	/workspace/coverage/default/23.sram_ctrl_access_during_key_req.1724947506	May 12 01:08:33 PM PDT 24	May 12 01:30:29 PM PDT 24	19985263244 ps
T36	/workspace/coverage/default/34.sram_ctrl_lc_escalation.1145148868	May 12 01:10:15 PM PDT 24	May 12 01:10:53 PM PDT 24	11166216012 ps
T37	/workspace/coverage/default/25.sram_ctrl_smoke.1187731415	May 12 01:08:43 PM PDT 24	May 12 01:08:51 PM PDT 24	1571402851 ps
T38	/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3511014991	May 12 01:06:33 PM PDT 24	May 12 01:09:55 PM PDT 24	4131754235 ps
T39	/workspace/coverage/default/0.sram_ctrl_partial_access.2016318192	May 12 01:06:30 PM PDT 24	May 12 01:06:50 PM PDT 24	950330676 ps
T137	/workspace/coverage/default/27.sram_ctrl_mem_walk.232590059	May 12 01:09:13 PM PDT 24	May 12 01:13:15 PM PDT 24	4033663304 ps
T24	/workspace/coverage/default/36.sram_ctrl_stress_all.1115756019	May 12 01:10:41 PM PDT 24	May 12 02:09:22 PM PDT 24	57399556555 ps
T138	/workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.2860181587	May 12 01:07:46 PM PDT 24	May 12 01:08:16 PM PDT 24	2661297118 ps
T44	/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2385332879	May 12 01:06:30 PM PDT 24	May 12 01:07:19 PM PDT 24	1997093076 ps
T74	/workspace/coverage/default/38.sram_ctrl_access_during_key_req.1385724527	May 12 01:10:58 PM PDT 24	May 12 01:23:35 PM PDT 24	11142300461 ps
T21	/workspace/coverage/default/9.sram_ctrl_alert_test.590774586	May 12 01:07:10 PM PDT 24	May 12 01:07:11 PM PDT 24	20933384 ps
T91	/workspace/coverage/default/30.sram_ctrl_stress_pipeline.2913711856	May 12 01:09:41 PM PDT 24	May 12 01:15:42 PM PDT 24	5913099438 ps
T139	/workspace/coverage/default/22.sram_ctrl_max_throughput.2243882029	May 12 01:08:19 PM PDT 24	May 12 01:08:42 PM PDT 24	705779103 ps
T105	/workspace/coverage/default/6.sram_ctrl_stress_all.1645530547	May 12 01:06:52 PM PDT 24	May 12 01:27:31 PM PDT 24	23776034120 ps
T126	/workspace/coverage/default/43.sram_ctrl_multiple_keys.2967122816	May 12 01:11:54 PM PDT 24	May 12 01:33:37 PM PDT 24	36738351507 ps
T29	/workspace/coverage/default/24.sram_ctrl_ram_cfg.869840120	May 12 01:08:40 PM PDT 24	May 12 01:08:44 PM PDT 24	1354853186 ps
T140	/workspace/coverage/default/22.sram_ctrl_smoke.3604302686	May 12 01:08:19 PM PDT 24	May 12 01:08:30 PM PDT 24	1590993979 ps
T75	/workspace/coverage/default/15.sram_ctrl_access_during_key_req.2594265349	May 12 01:07:30 PM PDT 24	May 12 01:23:21 PM PDT 24	18527700656 ps
T141	/workspace/coverage/default/14.sram_ctrl_bijection.1944587292	May 12 01:07:21 PM PDT 24	May 12 01:38:46 PM PDT 24	27879149610 ps
T45	/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2946987251	May 12 01:07:04 PM PDT 24	May 12 01:08:46 PM PDT 24	5432222832 ps
T142	/workspace/coverage/default/3.sram_ctrl_max_throughput.2678236917	May 12 01:06:39 PM PDT 24	May 12 01:07:13 PM PDT 24	733920059 ps
T143	/workspace/coverage/default/40.sram_ctrl_mem_walk.3386081608	May 12 01:11:21 PM PDT 24	May 12 01:16:01 PM PDT 24	15845390170 ps
T144	/workspace/coverage/default/23.sram_ctrl_max_throughput.2969735478	May 12 01:08:33 PM PDT 24	May 12 01:10:21 PM PDT 24	3147378597 ps
T145	/workspace/coverage/default/13.sram_ctrl_stress_all.1184626813	May 12 01:07:23 PM PDT 24	May 12 01:23:14 PM PDT 24	47517899556 ps
T146	/workspace/coverage/default/46.sram_ctrl_partial_access.284464259	May 12 01:12:21 PM PDT 24	May 12 01:12:30 PM PDT 24	742614914 ps
T147	/workspace/coverage/default/46.sram_ctrl_multiple_keys.3050774879	May 12 01:12:21 PM PDT 24	May 12 01:28:48 PM PDT 24	33404483333 ps
T148	/workspace/coverage/default/7.sram_ctrl_smoke.47581401	May 12 01:06:56 PM PDT 24	May 12 01:08:29 PM PDT 24	2858816029 ps
T149	/workspace/coverage/default/40.sram_ctrl_multiple_keys.3962926357	May 12 01:11:12 PM PDT 24	May 12 01:26:37 PM PDT 24	39285765335 ps
T150	/workspace/coverage/default/35.sram_ctrl_ram_cfg.4258067910	May 12 01:10:29 PM PDT 24	May 12 01:10:33 PM PDT 24	1600062558 ps
T151	/workspace/coverage/default/43.sram_ctrl_mem_walk.1178839580	May 12 01:11:56 PM PDT 24	May 12 01:15:07 PM PDT 24	137666552542 ps
T152	/workspace/coverage/default/25.sram_ctrl_max_throughput.385828118	May 12 01:08:51 PM PDT 24	May 12 01:09:27 PM PDT 24	748739511 ps
T153	/workspace/coverage/default/26.sram_ctrl_ram_cfg.2362837620	May 12 01:09:02 PM PDT 24	May 12 01:09:06 PM PDT 24	1467107058 ps
T92	/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.3392911425	May 12 01:07:07 PM PDT 24	May 12 01:13:44 PM PDT 24	39716438881 ps
T154	/workspace/coverage/default/1.sram_ctrl_multiple_keys.2588489185	May 12 01:06:37 PM PDT 24	May 12 01:07:44 PM PDT 24	3845707512 ps
T76	/workspace/coverage/default/26.sram_ctrl_access_during_key_req.4136126731	May 12 01:09:01 PM PDT 24	May 12 01:23:19 PM PDT 24	43123550064 ps
T155	/workspace/coverage/default/5.sram_ctrl_executable.2699605740	May 12 01:06:52 PM PDT 24	May 12 01:21:58 PM PDT 24	8775850550 ps
T93	/workspace/coverage/default/22.sram_ctrl_stress_pipeline.1439573918	May 12 01:08:19 PM PDT 24	May 12 01:13:23 PM PDT 24	5327054309 ps
T106	/workspace/coverage/default/15.sram_ctrl_stress_all.791369493	May 12 01:07:35 PM PDT 24	May 12 02:02:05 PM PDT 24	203799203336 ps
T77	/workspace/coverage/default/17.sram_ctrl_mem_partial_access.833553928	May 12 01:07:49 PM PDT 24	May 12 01:09:51 PM PDT 24	3104468515 ps
T156	/workspace/coverage/default/40.sram_ctrl_lc_escalation.4093050329	May 12 01:11:19 PM PDT 24	May 12 01:12:51 PM PDT 24	73781177397 ps
T157	/workspace/coverage/default/9.sram_ctrl_multiple_keys.2051146392	May 12 01:07:04 PM PDT 24	May 12 01:07:20 PM PDT 24	2939602826 ps
T158	/workspace/coverage/default/20.sram_ctrl_max_throughput.798930682	May 12 01:08:05 PM PDT 24	May 12 01:10:16 PM PDT 24	759225844 ps
T159	/workspace/coverage/default/8.sram_ctrl_smoke.1142985660	May 12 01:07:01 PM PDT 24	May 12 01:07:20 PM PDT 24	1124563843 ps
T83	/workspace/coverage/default/31.sram_ctrl_mem_partial_access.83552831	May 12 01:09:49 PM PDT 24	May 12 01:10:50 PM PDT 24	1932394755 ps
T160	/workspace/coverage/default/34.sram_ctrl_partial_access.2461343292	May 12 01:10:12 PM PDT 24	May 12 01:10:31 PM PDT 24	2042871609 ps
T161	/workspace/coverage/default/36.sram_ctrl_lc_escalation.3701982823	May 12 01:10:36 PM PDT 24	May 12 01:11:37 PM PDT 24	40947083900 ps
T162	/workspace/coverage/default/42.sram_ctrl_regwen.3131437987	May 12 01:11:41 PM PDT 24	May 12 01:15:28 PM PDT 24	12650629353 ps
T163	/workspace/coverage/default/26.sram_ctrl_partial_access.1110385685	May 12 01:08:55 PM PDT 24	May 12 01:09:19 PM PDT 24	6834592387 ps
T46	/workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.3187689316	May 12 01:09:01 PM PDT 24	May 12 01:09:23 PM PDT 24	1351414447 ps
T164	/workspace/coverage/default/4.sram_ctrl_executable.1989657624	May 12 01:06:45 PM PDT 24	May 12 01:22:47 PM PDT 24	17928721590 ps
T165	/workspace/coverage/default/31.sram_ctrl_lc_escalation.3514642929	May 12 01:09:47 PM PDT 24	May 12 01:10:34 PM PDT 24	8282669383 ps
T166	/workspace/coverage/default/31.sram_ctrl_multiple_keys.2549448349	May 12 01:09:47 PM PDT 24	May 12 01:34:56 PM PDT 24	19346155371 ps
T167	/workspace/coverage/default/40.sram_ctrl_ram_cfg.4139221550	May 12 01:11:25 PM PDT 24	May 12 01:11:28 PM PDT 24	362227074 ps
T168	/workspace/coverage/default/20.sram_ctrl_executable.3402847629	May 12 01:08:05 PM PDT 24	May 12 01:18:14 PM PDT 24	7913204689 ps
T169	/workspace/coverage/default/15.sram_ctrl_stress_pipeline.4214888749	May 12 01:07:25 PM PDT 24	May 12 01:10:02 PM PDT 24	26158895157 ps
T47	/workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.3612365643	May 12 01:09:42 PM PDT 24	May 12 01:10:31 PM PDT 24	1960292707 ps
T170	/workspace/coverage/default/40.sram_ctrl_stress_pipeline.3772000949	May 12 01:11:18 PM PDT 24	May 12 01:16:35 PM PDT 24	46999952720 ps
T84	/workspace/coverage/default/6.sram_ctrl_mem_partial_access.3746803706	May 12 01:06:55 PM PDT 24	May 12 01:08:57 PM PDT 24	1585233470 ps
T171	/workspace/coverage/default/43.sram_ctrl_access_during_key_req.22501591	May 12 01:11:52 PM PDT 24	May 12 01:23:38 PM PDT 24	25182219303 ps
T172	/workspace/coverage/default/45.sram_ctrl_lc_escalation.1750651239	May 12 01:12:13 PM PDT 24	May 12 01:12:21 PM PDT 24	3736249233 ps
T173	/workspace/coverage/default/24.sram_ctrl_max_throughput.906805848	May 12 01:08:41 PM PDT 24	May 12 01:10:00 PM PDT 24	773280620 ps
T174	/workspace/coverage/default/49.sram_ctrl_bijection.3632866026	May 12 01:12:58 PM PDT 24	May 12 01:41:43 PM PDT 24	100969805294 ps
T175	/workspace/coverage/default/16.sram_ctrl_mem_walk.1395483464	May 12 01:07:38 PM PDT 24	May 12 01:11:54 PM PDT 24	8209315645 ps
T176	/workspace/coverage/default/17.sram_ctrl_lc_escalation.4127860091	May 12 01:07:44 PM PDT 24	May 12 01:08:21 PM PDT 24	6398288760 ps
T177	/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.2944518181	May 12 01:07:25 PM PDT 24	May 12 01:10:31 PM PDT 24	7195039856 ps
T85	/workspace/coverage/default/31.sram_ctrl_access_during_key_req.3534611518	May 12 01:09:49 PM PDT 24	May 12 01:27:12 PM PDT 24	23471551215 ps
T178	/workspace/coverage/default/16.sram_ctrl_lc_escalation.4253752660	May 12 01:07:40 PM PDT 24	May 12 01:09:26 PM PDT 24	51563963667 ps
T179	/workspace/coverage/default/47.sram_ctrl_smoke.2482400639	May 12 01:12:31 PM PDT 24	May 12 01:12:51 PM PDT 24	5246754841 ps
T180	/workspace/coverage/default/7.sram_ctrl_lc_escalation.2893694874	May 12 01:06:51 PM PDT 24	May 12 01:08:22 PM PDT 24	18211331361 ps
T181	/workspace/coverage/default/18.sram_ctrl_lc_escalation.2359252776	May 12 01:07:52 PM PDT 24	May 12 01:08:21 PM PDT 24	4224998325 ps
T182	/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3844523182	May 12 01:07:07 PM PDT 24	May 12 01:09:33 PM PDT 24	1276615266 ps
T183	/workspace/coverage/default/26.sram_ctrl_stress_pipeline.2001004780	May 12 01:08:57 PM PDT 24	May 12 01:12:43 PM PDT 24	15201521223 ps
T184	/workspace/coverage/default/49.sram_ctrl_lc_escalation.1585015023	May 12 01:12:58 PM PDT 24	May 12 01:13:52 PM PDT 24	9041808847 ps
T22	/workspace/coverage/default/5.sram_ctrl_alert_test.1592722448	May 12 01:06:51 PM PDT 24	May 12 01:06:53 PM PDT 24	81047343 ps
T185	/workspace/coverage/default/25.sram_ctrl_mem_partial_access.1107679987	May 12 01:08:53 PM PDT 24	May 12 01:11:27 PM PDT 24	9396282372 ps
T186	/workspace/coverage/default/45.sram_ctrl_alert_test.2411425634	May 12 01:12:20 PM PDT 24	May 12 01:12:21 PM PDT 24	12074765 ps
T187	/workspace/coverage/default/14.sram_ctrl_lc_escalation.103911546	May 12 01:07:22 PM PDT 24	May 12 01:07:37 PM PDT 24	1991841627 ps
T188	/workspace/coverage/default/16.sram_ctrl_mem_partial_access.518181175	May 12 01:07:38 PM PDT 24	May 12 01:08:53 PM PDT 24	13767189334 ps
T189	/workspace/coverage/default/13.sram_ctrl_partial_access.256838506	May 12 01:07:21 PM PDT 24	May 12 01:09:58 PM PDT 24	1330072560 ps
T190	/workspace/coverage/default/3.sram_ctrl_lc_escalation.283788213	May 12 01:06:39 PM PDT 24	May 12 01:07:45 PM PDT 24	40860804835 ps
T191	/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.2102560277	May 12 01:08:20 PM PDT 24	May 12 01:12:50 PM PDT 24	44848459451 ps
T192	/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.787623071	May 12 01:12:43 PM PDT 24	May 12 01:14:48 PM PDT 24	843377984 ps
T123	/workspace/coverage/default/15.sram_ctrl_regwen.1198050199	May 12 01:07:31 PM PDT 24	May 12 01:27:32 PM PDT 24	18570144149 ps
T193	/workspace/coverage/default/15.sram_ctrl_partial_access.4098343247	May 12 01:07:28 PM PDT 24	May 12 01:07:50 PM PDT 24	961366865 ps
T194	/workspace/coverage/default/19.sram_ctrl_bijection.2430532320	May 12 01:07:57 PM PDT 24	May 12 01:29:34 PM PDT 24	124582502623 ps
T195	/workspace/coverage/default/2.sram_ctrl_executable.2481877870	May 12 01:06:34 PM PDT 24	May 12 01:07:24 PM PDT 24	6350272426 ps
T196	/workspace/coverage/default/49.sram_ctrl_multiple_keys.3678352507	May 12 01:12:55 PM PDT 24	May 12 01:28:13 PM PDT 24	72958795754 ps
T197	/workspace/coverage/default/26.sram_ctrl_regwen.3002098401	May 12 01:09:00 PM PDT 24	May 12 01:30:03 PM PDT 24	102486754180 ps
T198	/workspace/coverage/default/13.sram_ctrl_alert_test.1902327791	May 12 01:07:21 PM PDT 24	May 12 01:07:22 PM PDT 24	41013424 ps
T199	/workspace/coverage/default/20.sram_ctrl_regwen.3524280210	May 12 01:08:12 PM PDT 24	May 12 01:19:44 PM PDT 24	26074302290 ps
T200	/workspace/coverage/default/30.sram_ctrl_ram_cfg.4240203208	May 12 01:09:39 PM PDT 24	May 12 01:09:45 PM PDT 24	5575528281 ps
T201	/workspace/coverage/default/10.sram_ctrl_executable.3533073238	May 12 01:07:09 PM PDT 24	May 12 01:22:31 PM PDT 24	8609099660 ps
T124	/workspace/coverage/default/27.sram_ctrl_mem_partial_access.1835891566	May 12 01:09:10 PM PDT 24	May 12 01:11:40 PM PDT 24	10365376046 ps
T202	/workspace/coverage/default/36.sram_ctrl_regwen.2943318602	May 12 01:10:42 PM PDT 24	May 12 01:32:38 PM PDT 24	109032747159 ps
T203	/workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.2010030337	May 12 01:10:19 PM PDT 24	May 12 01:13:01 PM PDT 24	13451553369 ps
T125	/workspace/coverage/default/46.sram_ctrl_mem_partial_access.128528489	May 12 01:12:29 PM PDT 24	May 12 01:13:49 PM PDT 24	6804094166 ps
T204	/workspace/coverage/default/28.sram_ctrl_partial_access_b2b.1380023890	May 12 01:09:15 PM PDT 24	May 12 01:13:27 PM PDT 24	15521657862 ps
T205	/workspace/coverage/default/33.sram_ctrl_regwen.3937777336	May 12 01:10:06 PM PDT 24	May 12 01:15:57 PM PDT 24	5001051760 ps
T100	/workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.789615707	May 12 01:06:46 PM PDT 24	May 12 01:07:37 PM PDT 24	8018694598 ps
T206	/workspace/coverage/default/37.sram_ctrl_ram_cfg.528536741	May 12 01:10:44 PM PDT 24	May 12 01:10:48 PM PDT 24	1407467934 ps
T207	/workspace/coverage/default/36.sram_ctrl_alert_test.4265871527	May 12 01:10:42 PM PDT 24	May 12 01:10:44 PM PDT 24	43093283 ps
T208	/workspace/coverage/default/18.sram_ctrl_alert_test.3384778915	May 12 01:07:57 PM PDT 24	May 12 01:07:58 PM PDT 24	65366583 ps
T209	/workspace/coverage/default/3.sram_ctrl_partial_access.3874584854	May 12 01:06:41 PM PDT 24	May 12 01:06:52 PM PDT 24	1662776123 ps
T210	/workspace/coverage/default/16.sram_ctrl_bijection.2194014936	May 12 01:07:37 PM PDT 24	May 12 01:23:00 PM PDT 24	53810538110 ps
T211	/workspace/coverage/default/26.sram_ctrl_mem_partial_access.1616201710	May 12 01:09:02 PM PDT 24	May 12 01:10:05 PM PDT 24	1943698957 ps
T212	/workspace/coverage/default/1.sram_ctrl_mem_partial_access.2199680685	May 12 01:06:42 PM PDT 24	May 12 01:07:43 PM PDT 24	1760262603 ps
T213	/workspace/coverage/default/40.sram_ctrl_alert_test.2157998526	May 12 01:11:20 PM PDT 24	May 12 01:11:21 PM PDT 24	68889832 ps
T214	/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.2337360997	May 12 01:06:31 PM PDT 24	May 12 01:08:51 PM PDT 24	833027268 ps
T215	/workspace/coverage/default/7.sram_ctrl_ram_cfg.797331536	May 12 01:06:59 PM PDT 24	May 12 01:07:03 PM PDT 24	381309556 ps
T216	/workspace/coverage/default/33.sram_ctrl_partial_access.1341148564	May 12 01:10:04 PM PDT 24	May 12 01:12:35 PM PDT 24	2567567821 ps
T217	/workspace/coverage/default/43.sram_ctrl_smoke.148650770	May 12 01:11:46 PM PDT 24	May 12 01:11:51 PM PDT 24	1527284713 ps
T218	/workspace/coverage/default/31.sram_ctrl_partial_access_b2b.2358139530	May 12 01:09:47 PM PDT 24	May 12 01:16:14 PM PDT 24	5888326030 ps
T219	/workspace/coverage/default/31.sram_ctrl_alert_test.866270874	May 12 01:09:54 PM PDT 24	May 12 01:09:55 PM PDT 24	61430670 ps
T220	/workspace/coverage/default/40.sram_ctrl_partial_access.4190838583	May 12 01:11:16 PM PDT 24	May 12 01:11:38 PM PDT 24	9100851889 ps
T221	/workspace/coverage/default/44.sram_ctrl_ram_cfg.2643321916	May 12 01:12:05 PM PDT 24	May 12 01:12:08 PM PDT 24	353787176 ps
T222	/workspace/coverage/default/36.sram_ctrl_stress_pipeline.128279725	May 12 01:10:32 PM PDT 24	May 12 01:14:28 PM PDT 24	32378222954 ps
T223	/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.3271427992	May 12 01:08:22 PM PDT 24	May 12 01:09:58 PM PDT 24	2649347554 ps
T224	/workspace/coverage/default/8.sram_ctrl_mem_partial_access.3404772889	May 12 01:07:03 PM PDT 24	May 12 01:09:04 PM PDT 24	1630420188 ps
T225	/workspace/coverage/default/18.sram_ctrl_stress_pipeline.1967291481	May 12 01:07:48 PM PDT 24	May 12 01:11:12 PM PDT 24	3636993388 ps
T226	/workspace/coverage/default/40.sram_ctrl_bijection.508243449	May 12 01:11:14 PM PDT 24	May 12 01:27:08 PM PDT 24	264553398197 ps
T227	/workspace/coverage/default/37.sram_ctrl_stress_pipeline.542856820	May 12 01:10:42 PM PDT 24	May 12 01:15:57 PM PDT 24	19263909795 ps
T228	/workspace/coverage/default/35.sram_ctrl_lc_escalation.1343086185	May 12 01:10:29 PM PDT 24	May 12 01:12:09 PM PDT 24	185559986376 ps
T229	/workspace/coverage/default/42.sram_ctrl_stress_all.975840016	May 12 01:11:54 PM PDT 24	May 12 02:09:04 PM PDT 24	115033551862 ps
T230	/workspace/coverage/default/25.sram_ctrl_lc_escalation.3319071995	May 12 01:08:51 PM PDT 24	May 12 01:09:07 PM PDT 24	21368715803 ps
T231	/workspace/coverage/default/5.sram_ctrl_stress_pipeline.4129835484	May 12 01:06:51 PM PDT 24	May 12 01:11:06 PM PDT 24	76285063868 ps
T232	/workspace/coverage/default/8.sram_ctrl_max_throughput.540525354	May 12 01:07:03 PM PDT 24	May 12 01:07:38 PM PDT 24	1485838619 ps
T233	/workspace/coverage/default/35.sram_ctrl_partial_access.3300831033	May 12 01:10:24 PM PDT 24	May 12 01:13:14 PM PDT 24	6526730390 ps
T234	/workspace/coverage/default/21.sram_ctrl_alert_test.638884756	May 12 01:08:19 PM PDT 24	May 12 01:08:20 PM PDT 24	34781113 ps
T235	/workspace/coverage/default/34.sram_ctrl_multiple_keys.2017421085	May 12 01:10:11 PM PDT 24	May 12 01:16:46 PM PDT 24	32223744170 ps
T236	/workspace/coverage/default/36.sram_ctrl_ram_cfg.166184912	May 12 01:10:37 PM PDT 24	May 12 01:10:41 PM PDT 24	1689642791 ps
T237	/workspace/coverage/default/32.sram_ctrl_bijection.1904772636	May 12 01:09:51 PM PDT 24	May 12 01:26:25 PM PDT 24	15083925502 ps
T238	/workspace/coverage/default/26.sram_ctrl_lc_escalation.3274297414	May 12 01:09:01 PM PDT 24	May 12 01:10:08 PM PDT 24	11356710637 ps
T239	/workspace/coverage/default/23.sram_ctrl_ram_cfg.919081820	May 12 01:08:33 PM PDT 24	May 12 01:08:36 PM PDT 24	342465234 ps
T240	/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.4288037496	May 12 01:06:40 PM PDT 24	May 12 01:07:13 PM PDT 24	3165110311 ps
T241	/workspace/coverage/default/3.sram_ctrl_regwen.3858759043	May 12 01:06:40 PM PDT 24	May 12 01:23:23 PM PDT 24	10594679331 ps
T242	/workspace/coverage/default/40.sram_ctrl_max_throughput.2113066066	May 12 01:11:18 PM PDT 24	May 12 01:12:08 PM PDT 24	3047780016 ps
T243	/workspace/coverage/default/19.sram_ctrl_partial_access.987982738	May 12 01:08:02 PM PDT 24	May 12 01:08:09 PM PDT 24	731715090 ps
T244	/workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.2758611950	May 12 01:09:05 PM PDT 24	May 12 01:09:16 PM PDT 24	1379080494 ps
T245	/workspace/coverage/default/4.sram_ctrl_smoke.3844182785	May 12 01:06:46 PM PDT 24	May 12 01:06:54 PM PDT 24	4059129722 ps
T246	/workspace/coverage/default/7.sram_ctrl_mem_walk.794274951	May 12 01:06:58 PM PDT 24	May 12 01:11:30 PM PDT 24	14336684390 ps
T247	/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.3719018487	May 12 01:07:39 PM PDT 24	May 12 01:09:10 PM PDT 24	787907059 ps
T248	/workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.2608525819	May 12 01:06:46 PM PDT 24	May 12 01:07:13 PM PDT 24	1889952709 ps
T249	/workspace/coverage/default/41.sram_ctrl_multiple_keys.2832742964	May 12 01:11:25 PM PDT 24	May 12 01:19:23 PM PDT 24	4307226756 ps
T250	/workspace/coverage/default/20.sram_ctrl_bijection.1592297127	May 12 01:08:12 PM PDT 24	May 12 01:35:57 PM PDT 24	76869004341 ps
T251	/workspace/coverage/default/15.sram_ctrl_max_throughput.3316913731	May 12 01:07:26 PM PDT 24	May 12 01:07:34 PM PDT 24	2957915336 ps
T252	/workspace/coverage/default/31.sram_ctrl_executable.1648069491	May 12 01:09:47 PM PDT 24	May 12 01:18:58 PM PDT 24	13940368686 ps
T253	/workspace/coverage/default/6.sram_ctrl_regwen.191662412	May 12 01:06:48 PM PDT 24	May 12 01:16:21 PM PDT 24	4780092925 ps
T254	/workspace/coverage/default/9.sram_ctrl_smoke.3896618482	May 12 01:07:08 PM PDT 24	May 12 01:07:22 PM PDT 24	4299217064 ps
T255	/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.2529939220	May 12 01:08:10 PM PDT 24	May 12 01:11:19 PM PDT 24	5249129596 ps
T256	/workspace/coverage/default/7.sram_ctrl_partial_access.1059405521	May 12 01:06:55 PM PDT 24	May 12 01:07:04 PM PDT 24	397463959 ps
T257	/workspace/coverage/default/2.sram_ctrl_bijection.576414778	May 12 01:06:35 PM PDT 24	May 12 01:36:27 PM PDT 24	85462191632 ps
T258	/workspace/coverage/default/6.sram_ctrl_multiple_keys.3352160934	May 12 01:06:50 PM PDT 24	May 12 01:15:33 PM PDT 24	6212277280 ps
T259	/workspace/coverage/default/11.sram_ctrl_stress_pipeline.278839428	May 12 01:07:08 PM PDT 24	May 12 01:12:52 PM PDT 24	16610439760 ps
T260	/workspace/coverage/default/12.sram_ctrl_smoke.3480256376	May 12 01:07:15 PM PDT 24	May 12 01:07:35 PM PDT 24	1539353886 ps
T261	/workspace/coverage/default/46.sram_ctrl_ram_cfg.1514269763	May 12 01:12:29 PM PDT 24	May 12 01:12:33 PM PDT 24	697441788 ps
T262	/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.3986929606	May 12 01:07:22 PM PDT 24	May 12 01:09:52 PM PDT 24	1561142506 ps
T263	/workspace/coverage/default/33.sram_ctrl_stress_pipeline.403822484	May 12 01:10:04 PM PDT 24	May 12 01:14:27 PM PDT 24	4461717731 ps
T264	/workspace/coverage/default/42.sram_ctrl_alert_test.3547965014	May 12 01:11:54 PM PDT 24	May 12 01:11:55 PM PDT 24	31418481 ps
T265	/workspace/coverage/default/49.sram_ctrl_stress_pipeline.2821311796	May 12 01:12:58 PM PDT 24	May 12 01:16:21 PM PDT 24	7830389676 ps
T129	/workspace/coverage/default/12.sram_ctrl_mem_partial_access.138934204	May 12 01:07:20 PM PDT 24	May 12 01:09:51 PM PDT 24	9791885402 ps
T266	/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.1233709158	May 12 01:09:02 PM PDT 24	May 12 01:09:13 PM PDT 24	4544871026 ps
T267	/workspace/coverage/default/16.sram_ctrl_partial_access_b2b.1342832952	May 12 01:07:37 PM PDT 24	May 12 01:13:32 PM PDT 24	45711276005 ps
T268	/workspace/coverage/default/24.sram_ctrl_stress_all.826748092	May 12 01:08:45 PM PDT 24	May 12 02:25:49 PM PDT 24	316703448851 ps
T269	/workspace/coverage/default/46.sram_ctrl_stress_all.1345724566	May 12 01:12:31 PM PDT 24	May 12 02:38:27 PM PDT 24	1222961570782 ps
T270	/workspace/coverage/default/37.sram_ctrl_access_during_key_req.1475396161	May 12 01:10:41 PM PDT 24	May 12 01:21:17 PM PDT 24	20633073938 ps
T18	/workspace/coverage/default/4.sram_ctrl_sec_cm.2293064278	May 12 01:06:46 PM PDT 24	May 12 01:06:48 PM PDT 24	824935054 ps
T271	/workspace/coverage/default/14.sram_ctrl_access_during_key_req.2448815930	May 12 01:07:27 PM PDT 24	May 12 01:26:30 PM PDT 24	68778048216 ps
T272	/workspace/coverage/default/19.sram_ctrl_executable.3428449935	May 12 01:08:02 PM PDT 24	May 12 01:15:26 PM PDT 24	11551447106 ps
T273	/workspace/coverage/default/7.sram_ctrl_access_during_key_req.4043760721	May 12 01:06:55 PM PDT 24	May 12 01:26:30 PM PDT 24	53017333768 ps
T274	/workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.370541964	May 12 01:07:56 PM PDT 24	May 12 01:08:28 PM PDT 24	1041097799 ps
T275	/workspace/coverage/default/39.sram_ctrl_ram_cfg.975464764	May 12 01:11:09 PM PDT 24	May 12 01:11:12 PM PDT 24	361851964 ps
T276	/workspace/coverage/default/45.sram_ctrl_regwen.3557551311	May 12 01:12:20 PM PDT 24	May 12 01:19:27 PM PDT 24	4179441028 ps
T277	/workspace/coverage/default/40.sram_ctrl_mem_partial_access.2127875924	May 12 01:11:26 PM PDT 24	May 12 01:12:30 PM PDT 24	1605680855 ps
T278	/workspace/coverage/default/30.sram_ctrl_access_during_key_req.1682904991	May 12 01:09:39 PM PDT 24	May 12 01:32:15 PM PDT 24	65429328245 ps
T279	/workspace/coverage/default/16.sram_ctrl_regwen.1581582362	May 12 01:07:39 PM PDT 24	May 12 01:27:19 PM PDT 24	13876688705 ps
T280	/workspace/coverage/default/29.sram_ctrl_alert_test.3680634913	May 12 01:09:34 PM PDT 24	May 12 01:09:35 PM PDT 24	37873404 ps
T130	/workspace/coverage/default/8.sram_ctrl_stress_all.915475011	May 12 01:07:10 PM PDT 24	May 12 02:10:31 PM PDT 24	527606887610 ps
T281	/workspace/coverage/default/29.sram_ctrl_stress_all.3575975241	May 12 01:09:41 PM PDT 24	May 12 02:26:21 PM PDT 24	195385070125 ps
T282	/workspace/coverage/default/11.sram_ctrl_executable.682638496	May 12 01:07:12 PM PDT 24	May 12 01:13:39 PM PDT 24	15701163684 ps
T283	/workspace/coverage/default/47.sram_ctrl_executable.3354754724	May 12 01:12:30 PM PDT 24	May 12 01:27:29 PM PDT 24	17646847178 ps
T284	/workspace/coverage/default/20.sram_ctrl_multiple_keys.32755599	May 12 01:08:05 PM PDT 24	May 12 01:27:07 PM PDT 24	22358725473 ps
T285	/workspace/coverage/default/34.sram_ctrl_max_throughput.3325590119	May 12 01:10:14 PM PDT 24	May 12 01:11:56 PM PDT 24	3146237302 ps
T286	/workspace/coverage/default/10.sram_ctrl_bijection.81096438	May 12 01:07:08 PM PDT 24	May 12 01:16:15 PM PDT 24	97044640858 ps
T287	/workspace/coverage/default/36.sram_ctrl_multiple_keys.956200207	May 12 01:10:32 PM PDT 24	May 12 01:52:32 PM PDT 24	27297365426 ps
T288	/workspace/coverage/default/38.sram_ctrl_lc_escalation.2134503080	May 12 01:10:57 PM PDT 24	May 12 01:11:43 PM PDT 24	26182966857 ps
T289	/workspace/coverage/default/16.sram_ctrl_alert_test.1610560300	May 12 01:07:38 PM PDT 24	May 12 01:07:39 PM PDT 24	12876170 ps
T290	/workspace/coverage/default/0.sram_ctrl_stress_pipeline.731110302	May 12 01:06:30 PM PDT 24	May 12 01:11:10 PM PDT 24	4485023532 ps
T291	/workspace/coverage/default/38.sram_ctrl_max_throughput.3078363546	May 12 01:10:56 PM PDT 24	May 12 01:12:03 PM PDT 24	3054471858 ps
T292	/workspace/coverage/default/18.sram_ctrl_partial_access_b2b.1427205353	May 12 01:07:51 PM PDT 24	May 12 01:11:56 PM PDT 24	20119251995 ps
T293	/workspace/coverage/default/28.sram_ctrl_alert_test.1490883107	May 12 01:09:25 PM PDT 24	May 12 01:09:26 PM PDT 24	25492581 ps
T294	/workspace/coverage/default/5.sram_ctrl_lc_escalation.2104185045	May 12 01:06:51 PM PDT 24	May 12 01:07:49 PM PDT 24	16596930851 ps
T295	/workspace/coverage/default/35.sram_ctrl_executable.2107080333	May 12 01:10:28 PM PDT 24	May 12 01:17:00 PM PDT 24	9729076531 ps
T127	/workspace/coverage/default/21.sram_ctrl_partial_access_b2b.357980081	May 12 01:08:16 PM PDT 24	May 12 01:13:32 PM PDT 24	57457646916 ps
T296	/workspace/coverage/default/17.sram_ctrl_access_during_key_req.1809141957	May 12 01:07:44 PM PDT 24	May 12 01:27:18 PM PDT 24	52072623801 ps
T297	/workspace/coverage/default/14.sram_ctrl_mem_walk.3830392358	May 12 01:07:27 PM PDT 24	May 12 01:11:58 PM PDT 24	38333443242 ps
T298	/workspace/coverage/default/35.sram_ctrl_multiple_keys.4086706512	May 12 01:10:25 PM PDT 24	May 12 01:13:33 PM PDT 24	39304999749 ps