Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

---

Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	138820687	1			T1	89683		T2	149083		T3	8168
triple_byte_access	2868225	1			T1	1780		T2	3046		T3	369
halfword_access	4399094	1			T1	2697		T2	4433		T3	545
byte_access	6135297	1			T1	3561		T2	5988		T3	719
zero_access	1853118	1			T1	880		T2	1513		T3	199

---

Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

76853652

1

T1

55483

T2

82171

T3

5050

auto[1]

77222769

1

T1

43118

T2

81892

T3

4950

---

Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	69075419	1			T1	50479		T2	74578		T3	4134
auto[0]	triple_byte_access	1372562	1			T1	1028		T2	1508		T3	184
auto[0]	halfword_access	2154108	1			T1	1530		T2	2292		T3	281
auto[0]	byte_access	3147780	1			T1	1956		T2	3038		T3	354
auto[0]	zero_access	1103783	1			T1	490		T2	755		T3	97
auto[1]	word_access	69745268	1			T1	39204		T2	74505		T3	4034
auto[1]	triple_byte_access	1495663	1			T1	752		T2	1538		T3	185
auto[1]	halfword_access	2244986	1			T1	1167		T2	2141		T3	264
auto[1]	byte_access	2987517	1			T1	1605		T2	2950		T3	365
auto[1]	zero_access	749335	1			T1	390		T2	758		T3	102