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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.09 99.81 96.99 100.00 100.00 98.60 99.70 98.52


Total test records in report: 1038
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T791 /workspace/coverage/default/39.sram_ctrl_bijection.534305668 May 12 01:11:05 PM PDT 24 May 12 01:31:59 PM PDT 24 72440433106 ps
T792 /workspace/coverage/default/23.sram_ctrl_bijection.1699170620 May 12 01:08:28 PM PDT 24 May 12 01:34:21 PM PDT 24 197267243211 ps
T793 /workspace/coverage/default/35.sram_ctrl_max_throughput.1582809212 May 12 01:10:27 PM PDT 24 May 12 01:11:39 PM PDT 24 2969134872 ps
T794 /workspace/coverage/default/45.sram_ctrl_stress_all.39597453 May 12 01:12:22 PM PDT 24 May 12 01:42:56 PM PDT 24 76086805959 ps
T795 /workspace/coverage/default/42.sram_ctrl_ram_cfg.620130023 May 12 01:11:39 PM PDT 24 May 12 01:11:43 PM PDT 24 391627754 ps
T796 /workspace/coverage/default/2.sram_ctrl_stress_pipeline.4014071580 May 12 01:06:37 PM PDT 24 May 12 01:08:48 PM PDT 24 5447118442 ps
T797 /workspace/coverage/default/20.sram_ctrl_alert_test.28003672 May 12 01:08:10 PM PDT 24 May 12 01:08:11 PM PDT 24 31921686 ps
T798 /workspace/coverage/default/2.sram_ctrl_stress_all.2888210998 May 12 01:06:39 PM PDT 24 May 12 02:06:47 PM PDT 24 79620555512 ps
T799 /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.794470747 May 12 01:06:54 PM PDT 24 May 12 01:15:04 PM PDT 24 20401715044 ps
T800 /workspace/coverage/default/17.sram_ctrl_stress_pipeline.824057018 May 12 01:07:42 PM PDT 24 May 12 01:11:57 PM PDT 24 6485088717 ps
T801 /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.2963577164 May 12 01:12:23 PM PDT 24 May 12 01:13:02 PM PDT 24 760648806 ps
T802 /workspace/coverage/default/13.sram_ctrl_mem_partial_access.2052743912 May 12 01:07:24 PM PDT 24 May 12 01:08:39 PM PDT 24 2730496347 ps
T803 /workspace/coverage/default/32.sram_ctrl_mem_walk.2908756649 May 12 01:10:03 PM PDT 24 May 12 01:12:25 PM PDT 24 6904469103 ps
T31 /workspace/coverage/default/3.sram_ctrl_sec_cm.1083668674 May 12 01:06:44 PM PDT 24 May 12 01:06:47 PM PDT 24 229436782 ps
T804 /workspace/coverage/default/27.sram_ctrl_ram_cfg.2164068695 May 12 01:09:09 PM PDT 24 May 12 01:09:13 PM PDT 24 352300515 ps
T805 /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.2880597559 May 12 01:13:02 PM PDT 24 May 12 01:15:49 PM PDT 24 4948720109 ps
T806 /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2900657969 May 12 01:12:38 PM PDT 24 May 12 01:13:12 PM PDT 24 4461673492 ps
T807 /workspace/coverage/default/34.sram_ctrl_bijection.4154873375 May 12 01:10:13 PM PDT 24 May 12 01:42:46 PM PDT 24 121147496113 ps
T808 /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.1552103503 May 12 01:11:18 PM PDT 24 May 12 01:11:25 PM PDT 24 2925537860 ps
T809 /workspace/coverage/default/38.sram_ctrl_stress_pipeline.3799155283 May 12 01:10:53 PM PDT 24 May 12 01:16:05 PM PDT 24 4120340335 ps
T810 /workspace/coverage/default/27.sram_ctrl_lc_escalation.4250422422 May 12 01:09:06 PM PDT 24 May 12 01:09:52 PM PDT 24 8220584416 ps
T811 /workspace/coverage/default/27.sram_ctrl_alert_test.1165605114 May 12 01:09:13 PM PDT 24 May 12 01:09:14 PM PDT 24 20686111 ps
T812 /workspace/coverage/default/8.sram_ctrl_bijection.3263998736 May 12 01:06:58 PM PDT 24 May 12 01:23:11 PM PDT 24 173517305516 ps
T813 /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.1768071662 May 12 01:10:41 PM PDT 24 May 12 01:19:13 PM PDT 24 85178636305 ps
T814 /workspace/coverage/default/45.sram_ctrl_bijection.3218478852 May 12 01:12:13 PM PDT 24 May 12 01:28:58 PM PDT 24 215947207030 ps
T815 /workspace/coverage/default/30.sram_ctrl_mem_walk.2154646587 May 12 01:09:42 PM PDT 24 May 12 01:14:24 PM PDT 24 55028867165 ps
T816 /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.305126935 May 12 01:12:14 PM PDT 24 May 12 01:18:50 PM PDT 24 16676833348 ps
T817 /workspace/coverage/default/27.sram_ctrl_access_during_key_req.1144122877 May 12 01:09:12 PM PDT 24 May 12 01:09:44 PM PDT 24 3822454274 ps
T818 /workspace/coverage/default/2.sram_ctrl_lc_escalation.1756389805 May 12 01:06:41 PM PDT 24 May 12 01:07:01 PM PDT 24 4997660086 ps
T819 /workspace/coverage/default/1.sram_ctrl_partial_access.405970522 May 12 01:06:34 PM PDT 24 May 12 01:06:40 PM PDT 24 420354146 ps
T820 /workspace/coverage/default/48.sram_ctrl_stress_all.813207738 May 12 01:12:48 PM PDT 24 May 12 01:56:14 PM PDT 24 27733650044 ps
T821 /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2520839036 May 12 01:07:09 PM PDT 24 May 12 01:07:25 PM PDT 24 3192075793 ps
T822 /workspace/coverage/default/20.sram_ctrl_partial_access.4109316510 May 12 01:08:06 PM PDT 24 May 12 01:08:16 PM PDT 24 1396781582 ps
T823 /workspace/coverage/default/45.sram_ctrl_multiple_keys.3100449800 May 12 01:12:09 PM PDT 24 May 12 01:30:07 PM PDT 24 87196095003 ps
T824 /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.4071589080 May 12 01:11:47 PM PDT 24 May 12 01:15:16 PM PDT 24 15576618145 ps
T825 /workspace/coverage/default/14.sram_ctrl_multiple_keys.2253443632 May 12 01:07:22 PM PDT 24 May 12 01:22:17 PM PDT 24 31735411217 ps
T826 /workspace/coverage/default/4.sram_ctrl_max_throughput.1754347047 May 12 01:06:47 PM PDT 24 May 12 01:08:14 PM PDT 24 784546644 ps
T827 /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.2578882458 May 12 01:06:49 PM PDT 24 May 12 01:07:26 PM PDT 24 755015307 ps
T828 /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.3958802838 May 12 01:08:12 PM PDT 24 May 12 01:09:31 PM PDT 24 3124245079 ps
T829 /workspace/coverage/default/38.sram_ctrl_regwen.4135056789 May 12 01:10:56 PM PDT 24 May 12 01:25:52 PM PDT 24 13113104106 ps
T830 /workspace/coverage/default/49.sram_ctrl_mem_partial_access.4041777224 May 12 01:13:02 PM PDT 24 May 12 01:14:22 PM PDT 24 2721148792 ps
T831 /workspace/coverage/default/44.sram_ctrl_lc_escalation.1475835912 May 12 01:12:03 PM PDT 24 May 12 01:12:52 PM PDT 24 27807840029 ps
T832 /workspace/coverage/default/15.sram_ctrl_mem_walk.174139992 May 12 01:07:30 PM PDT 24 May 12 01:09:55 PM PDT 24 9431926845 ps
T833 /workspace/coverage/default/22.sram_ctrl_mem_walk.288493831 May 12 01:08:22 PM PDT 24 May 12 01:12:30 PM PDT 24 15764979866 ps
T834 /workspace/coverage/default/16.sram_ctrl_stress_pipeline.3390661255 May 12 01:07:34 PM PDT 24 May 12 01:12:55 PM PDT 24 4598925485 ps
T835 /workspace/coverage/default/23.sram_ctrl_multiple_keys.1889997847 May 12 01:08:22 PM PDT 24 May 12 01:35:40 PM PDT 24 31373280645 ps
T836 /workspace/coverage/default/17.sram_ctrl_regwen.3771043083 May 12 01:07:44 PM PDT 24 May 12 01:20:50 PM PDT 24 9142711600 ps
T837 /workspace/coverage/default/28.sram_ctrl_stress_pipeline.4220428896 May 12 01:09:15 PM PDT 24 May 12 01:13:44 PM PDT 24 20158974663 ps
T838 /workspace/coverage/default/26.sram_ctrl_mem_walk.696659661 May 12 01:09:02 PM PDT 24 May 12 01:14:11 PM PDT 24 20689965211 ps
T839 /workspace/coverage/default/32.sram_ctrl_max_throughput.958687142 May 12 01:09:56 PM PDT 24 May 12 01:10:29 PM PDT 24 1573417718 ps
T840 /workspace/coverage/default/10.sram_ctrl_access_during_key_req.683122063 May 12 01:07:09 PM PDT 24 May 12 01:12:09 PM PDT 24 9142248949 ps
T841 /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.1203586912 May 12 01:10:43 PM PDT 24 May 12 01:12:48 PM PDT 24 3129383042 ps
T842 /workspace/coverage/default/1.sram_ctrl_lc_escalation.596258490 May 12 01:06:37 PM PDT 24 May 12 01:08:44 PM PDT 24 72209790944 ps
T843 /workspace/coverage/default/16.sram_ctrl_smoke.585671420 May 12 01:07:33 PM PDT 24 May 12 01:07:52 PM PDT 24 7060721061 ps
T844 /workspace/coverage/default/38.sram_ctrl_alert_test.796243768 May 12 01:11:05 PM PDT 24 May 12 01:11:06 PM PDT 24 87027403 ps
T845 /workspace/coverage/default/4.sram_ctrl_stress_all.488801350 May 12 01:06:46 PM PDT 24 May 12 03:29:06 PM PDT 24 232256011467 ps
T846 /workspace/coverage/default/22.sram_ctrl_stress_all.1483335281 May 12 01:08:22 PM PDT 24 May 12 02:20:12 PM PDT 24 667755852298 ps
T847 /workspace/coverage/default/43.sram_ctrl_lc_escalation.2681295960 May 12 01:11:48 PM PDT 24 May 12 01:12:41 PM PDT 24 21875627123 ps
T848 /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.3970117497 May 12 01:07:39 PM PDT 24 May 12 01:07:48 PM PDT 24 941880587 ps
T849 /workspace/coverage/default/28.sram_ctrl_multiple_keys.3225191052 May 12 01:09:09 PM PDT 24 May 12 01:23:01 PM PDT 24 8000704908 ps
T850 /workspace/coverage/default/20.sram_ctrl_stress_pipeline.1603248431 May 12 01:08:07 PM PDT 24 May 12 01:11:05 PM PDT 24 3784513012 ps
T851 /workspace/coverage/default/17.sram_ctrl_smoke.3006942517 May 12 01:07:38 PM PDT 24 May 12 01:07:59 PM PDT 24 1405664898 ps
T852 /workspace/coverage/default/46.sram_ctrl_mem_walk.4074934045 May 12 01:12:30 PM PDT 24 May 12 01:16:37 PM PDT 24 4065937195 ps
T853 /workspace/coverage/default/28.sram_ctrl_stress_all.1656991467 May 12 01:09:17 PM PDT 24 May 12 01:51:58 PM PDT 24 100695316762 ps
T854 /workspace/coverage/default/41.sram_ctrl_bijection.120002040 May 12 01:11:24 PM PDT 24 May 12 01:37:13 PM PDT 24 299787782094 ps
T855 /workspace/coverage/default/0.sram_ctrl_mem_partial_access.1365050895 May 12 01:06:37 PM PDT 24 May 12 01:07:42 PM PDT 24 1890485515 ps
T856 /workspace/coverage/default/36.sram_ctrl_executable.317460133 May 12 01:10:37 PM PDT 24 May 12 01:14:47 PM PDT 24 8734894232 ps
T857 /workspace/coverage/default/48.sram_ctrl_regwen.1676878899 May 12 01:12:45 PM PDT 24 May 12 01:29:50 PM PDT 24 30277475263 ps
T858 /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.2680779794 May 12 01:08:44 PM PDT 24 May 12 01:09:04 PM PDT 24 6039651177 ps
T859 /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.1930146652 May 12 01:08:34 PM PDT 24 May 12 01:10:06 PM PDT 24 789760063 ps
T860 /workspace/coverage/default/16.sram_ctrl_executable.1529067116 May 12 01:07:38 PM PDT 24 May 12 01:21:39 PM PDT 24 94465532464 ps
T861 /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.2842374830 May 12 01:08:49 PM PDT 24 May 12 01:08:55 PM PDT 24 672897810 ps
T862 /workspace/coverage/default/45.sram_ctrl_mem_partial_access.3222080057 May 12 01:12:20 PM PDT 24 May 12 01:13:33 PM PDT 24 2722193101 ps
T863 /workspace/coverage/default/19.sram_ctrl_mem_partial_access.2184028074 May 12 01:08:02 PM PDT 24 May 12 01:10:42 PM PDT 24 9927020178 ps
T864 /workspace/coverage/default/22.sram_ctrl_alert_test.899268565 May 12 01:08:27 PM PDT 24 May 12 01:08:28 PM PDT 24 21042703 ps
T865 /workspace/coverage/default/0.sram_ctrl_regwen.2834643796 May 12 01:06:36 PM PDT 24 May 12 01:22:50 PM PDT 24 12089127683 ps
T866 /workspace/coverage/default/43.sram_ctrl_ram_cfg.144381129 May 12 01:11:51 PM PDT 24 May 12 01:11:55 PM PDT 24 1402808640 ps
T867 /workspace/coverage/default/31.sram_ctrl_bijection.486121447 May 12 01:09:44 PM PDT 24 May 12 01:45:26 PM PDT 24 193398150011 ps
T868 /workspace/coverage/default/8.sram_ctrl_alert_test.3872633025 May 12 01:07:04 PM PDT 24 May 12 01:07:05 PM PDT 24 10239656 ps
T869 /workspace/coverage/default/12.sram_ctrl_alert_test.1448966024 May 12 01:07:16 PM PDT 24 May 12 01:07:18 PM PDT 24 16472662 ps
T870 /workspace/coverage/default/1.sram_ctrl_stress_pipeline.2579723620 May 12 01:06:33 PM PDT 24 May 12 01:11:03 PM PDT 24 5069608088 ps
T871 /workspace/coverage/default/2.sram_ctrl_mem_walk.3501416942 May 12 01:06:36 PM PDT 24 May 12 01:08:36 PM PDT 24 3797440451 ps
T872 /workspace/coverage/default/5.sram_ctrl_stress_all.108861043 May 12 01:06:48 PM PDT 24 May 12 01:43:40 PM PDT 24 148689161163 ps
T873 /workspace/coverage/default/41.sram_ctrl_mem_walk.4226558947 May 12 01:11:31 PM PDT 24 May 12 01:16:57 PM PDT 24 37299124770 ps
T874 /workspace/coverage/default/37.sram_ctrl_max_throughput.2374563594 May 12 01:10:41 PM PDT 24 May 12 01:11:42 PM PDT 24 734593741 ps
T875 /workspace/coverage/default/26.sram_ctrl_executable.3008721657 May 12 01:09:02 PM PDT 24 May 12 01:19:54 PM PDT 24 14298383977 ps
T876 /workspace/coverage/default/44.sram_ctrl_regwen.2886479051 May 12 01:12:07 PM PDT 24 May 12 01:25:28 PM PDT 24 22605034235 ps
T877 /workspace/coverage/default/14.sram_ctrl_ram_cfg.129842714 May 12 01:07:28 PM PDT 24 May 12 01:07:31 PM PDT 24 349904182 ps
T878 /workspace/coverage/default/2.sram_ctrl_multiple_keys.3786289633 May 12 01:06:35 PM PDT 24 May 12 01:25:51 PM PDT 24 53812750535 ps
T879 /workspace/coverage/default/1.sram_ctrl_alert_test.1565797673 May 12 01:06:35 PM PDT 24 May 12 01:06:36 PM PDT 24 16531137 ps
T880 /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.205975975 May 12 01:07:14 PM PDT 24 May 12 01:13:18 PM PDT 24 14500079396 ps
T881 /workspace/coverage/default/45.sram_ctrl_smoke.398020588 May 12 01:12:10 PM PDT 24 May 12 01:13:09 PM PDT 24 4787147104 ps
T882 /workspace/coverage/default/19.sram_ctrl_ram_cfg.2008586076 May 12 01:08:00 PM PDT 24 May 12 01:08:04 PM PDT 24 1408527765 ps
T883 /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.3490224839 May 12 01:12:30 PM PDT 24 May 12 01:12:36 PM PDT 24 700967576 ps
T884 /workspace/coverage/default/0.sram_ctrl_multiple_keys.3008496898 May 12 01:06:30 PM PDT 24 May 12 01:20:34 PM PDT 24 23807483899 ps
T885 /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.2425815559 May 12 01:09:22 PM PDT 24 May 12 01:15:08 PM PDT 24 25849090482 ps
T886 /workspace/coverage/default/3.sram_ctrl_mem_partial_access.3403371973 May 12 01:06:40 PM PDT 24 May 12 01:07:47 PM PDT 24 10449226891 ps
T887 /workspace/coverage/default/38.sram_ctrl_mem_partial_access.1310488267 May 12 01:11:01 PM PDT 24 May 12 01:13:26 PM PDT 24 8735819585 ps
T888 /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.629110425 May 12 01:08:32 PM PDT 24 May 12 01:14:03 PM PDT 24 24908272487 ps
T889 /workspace/coverage/default/8.sram_ctrl_partial_access.968863437 May 12 01:06:59 PM PDT 24 May 12 01:07:18 PM PDT 24 1237118495 ps
T890 /workspace/coverage/default/26.sram_ctrl_bijection.3964258647 May 12 01:09:00 PM PDT 24 May 12 01:34:12 PM PDT 24 461579304672 ps
T891 /workspace/coverage/default/6.sram_ctrl_mem_walk.686004812 May 12 01:06:54 PM PDT 24 May 12 01:11:53 PM PDT 24 20655125373 ps
T892 /workspace/coverage/default/43.sram_ctrl_partial_access.1483637963 May 12 01:11:47 PM PDT 24 May 12 01:11:54 PM PDT 24 978270873 ps
T893 /workspace/coverage/default/39.sram_ctrl_mem_partial_access.3263766650 May 12 01:11:13 PM PDT 24 May 12 01:12:35 PM PDT 24 4761954915 ps
T894 /workspace/coverage/default/13.sram_ctrl_lc_escalation.7367794 May 12 01:07:17 PM PDT 24 May 12 01:07:57 PM PDT 24 62009974923 ps
T895 /workspace/coverage/default/29.sram_ctrl_smoke.3417969133 May 12 01:09:22 PM PDT 24 May 12 01:09:41 PM PDT 24 3917730189 ps
T896 /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3564939370 May 12 01:07:08 PM PDT 24 May 12 01:08:07 PM PDT 24 781560812 ps
T897 /workspace/coverage/default/37.sram_ctrl_lc_escalation.1692161856 May 12 01:10:42 PM PDT 24 May 12 01:11:31 PM PDT 24 25581908678 ps
T898 /workspace/coverage/default/33.sram_ctrl_alert_test.1911094684 May 12 01:10:14 PM PDT 24 May 12 01:10:16 PM PDT 24 15448926 ps
T899 /workspace/coverage/default/6.sram_ctrl_smoke.2567753810 May 12 01:06:47 PM PDT 24 May 12 01:07:00 PM PDT 24 1486255167 ps
T900 /workspace/coverage/default/48.sram_ctrl_bijection.1149891806 May 12 01:12:42 PM PDT 24 May 12 01:48:21 PM PDT 24 30492353705 ps
T901 /workspace/coverage/default/15.sram_ctrl_alert_test.90326594 May 12 01:07:34 PM PDT 24 May 12 01:07:35 PM PDT 24 17844859 ps
T902 /workspace/coverage/default/12.sram_ctrl_multiple_keys.3576041657 May 12 01:07:12 PM PDT 24 May 12 01:16:54 PM PDT 24 11642159396 ps
T903 /workspace/coverage/default/1.sram_ctrl_stress_all.515854398 May 12 01:06:37 PM PDT 24 May 12 02:14:10 PM PDT 24 37008309073 ps
T904 /workspace/coverage/default/3.sram_ctrl_stress_all.2090544828 May 12 01:06:51 PM PDT 24 May 12 02:02:53 PM PDT 24 41779951887 ps
T905 /workspace/coverage/default/12.sram_ctrl_stress_all.410210470 May 12 01:07:17 PM PDT 24 May 12 02:55:47 PM PDT 24 203522066266 ps
T906 /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3314447987 May 12 01:07:06 PM PDT 24 May 12 01:09:21 PM PDT 24 4469357216 ps
T907 /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.132656295 May 12 01:07:09 PM PDT 24 May 12 01:16:00 PM PDT 24 23200300711 ps
T908 /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.1497343862 May 12 01:11:36 PM PDT 24 May 12 01:11:42 PM PDT 24 1361922327 ps
T909 /workspace/coverage/default/39.sram_ctrl_regwen.714332327 May 12 01:11:11 PM PDT 24 May 12 01:31:17 PM PDT 24 89587560260 ps
T910 /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.2313427192 May 12 01:12:01 PM PDT 24 May 12 01:12:58 PM PDT 24 1412225654 ps
T911 /workspace/coverage/default/10.sram_ctrl_stress_pipeline.2859683108 May 12 01:07:07 PM PDT 24 May 12 01:12:03 PM PDT 24 3912876219 ps
T912 /workspace/coverage/default/0.sram_ctrl_alert_test.2904553800 May 12 01:06:31 PM PDT 24 May 12 01:06:33 PM PDT 24 11743639 ps
T913 /workspace/coverage/default/7.sram_ctrl_multiple_keys.884143298 May 12 01:06:54 PM PDT 24 May 12 01:26:30 PM PDT 24 14048191862 ps
T914 /workspace/coverage/default/29.sram_ctrl_partial_access.2119937030 May 12 01:09:22 PM PDT 24 May 12 01:10:57 PM PDT 24 2141158555 ps
T915 /workspace/coverage/default/34.sram_ctrl_executable.2655594907 May 12 01:10:16 PM PDT 24 May 12 01:24:32 PM PDT 24 6812284002 ps
T916 /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.948024701 May 12 01:09:56 PM PDT 24 May 12 01:10:02 PM PDT 24 3052396935 ps
T917 /workspace/coverage/default/19.sram_ctrl_alert_test.1565093312 May 12 01:08:05 PM PDT 24 May 12 01:08:06 PM PDT 24 15823890 ps
T918 /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.2012372083 May 12 01:06:39 PM PDT 24 May 12 01:07:00 PM PDT 24 3382356063 ps
T919 /workspace/coverage/default/37.sram_ctrl_mem_walk.1741133804 May 12 01:10:46 PM PDT 24 May 12 01:13:10 PM PDT 24 6968036476 ps
T920 /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.3270938743 May 12 01:10:04 PM PDT 24 May 12 01:16:17 PM PDT 24 126111346995 ps
T921 /workspace/coverage/default/11.sram_ctrl_regwen.1284201102 May 12 01:07:14 PM PDT 24 May 12 01:31:45 PM PDT 24 69799335124 ps
T922 /workspace/coverage/default/21.sram_ctrl_multiple_keys.2730853724 May 12 01:08:11 PM PDT 24 May 12 01:18:05 PM PDT 24 14121335963 ps
T923 /workspace/coverage/default/48.sram_ctrl_multiple_keys.3103491284 May 12 01:12:42 PM PDT 24 May 12 01:21:42 PM PDT 24 67082986603 ps
T924 /workspace/coverage/default/20.sram_ctrl_lc_escalation.2031411098 May 12 01:08:07 PM PDT 24 May 12 01:08:44 PM PDT 24 6802700318 ps
T925 /workspace/coverage/default/22.sram_ctrl_access_during_key_req.2045954699 May 12 01:08:19 PM PDT 24 May 12 01:14:21 PM PDT 24 4415212589 ps
T926 /workspace/coverage/default/0.sram_ctrl_max_throughput.808763618 May 12 01:06:37 PM PDT 24 May 12 01:07:02 PM PDT 24 729447375 ps
T927 /workspace/coverage/default/11.sram_ctrl_alert_test.3085423763 May 12 01:07:15 PM PDT 24 May 12 01:07:16 PM PDT 24 17607793 ps
T928 /workspace/coverage/default/37.sram_ctrl_mem_partial_access.2651359943 May 12 01:10:44 PM PDT 24 May 12 01:12:48 PM PDT 24 1564133848 ps
T929 /workspace/coverage/default/38.sram_ctrl_smoke.2647252929 May 12 01:10:48 PM PDT 24 May 12 01:11:14 PM PDT 24 6601871156 ps
T930 /workspace/coverage/default/18.sram_ctrl_access_during_key_req.3745238593 May 12 01:07:52 PM PDT 24 May 12 01:17:15 PM PDT 24 47163452960 ps
T931 /workspace/coverage/default/9.sram_ctrl_stress_all.2521493274 May 12 01:07:04 PM PDT 24 May 12 01:46:46 PM PDT 24 41391545636 ps
T932 /workspace/coverage/default/14.sram_ctrl_alert_test.804147271 May 12 01:07:30 PM PDT 24 May 12 01:07:32 PM PDT 24 11950298 ps
T933 /workspace/coverage/default/25.sram_ctrl_access_during_key_req.3288759308 May 12 01:08:48 PM PDT 24 May 12 01:17:20 PM PDT 24 30262605750 ps
T934 /workspace/coverage/default/37.sram_ctrl_executable.466725597 May 12 01:10:44 PM PDT 24 May 12 01:24:10 PM PDT 24 143690587344 ps
T935 /workspace/coverage/default/21.sram_ctrl_mem_walk.4016454231 May 12 01:08:19 PM PDT 24 May 12 01:13:10 PM PDT 24 14226718431 ps
T936 /workspace/coverage/default/46.sram_ctrl_access_during_key_req.3184586283 May 12 01:12:25 PM PDT 24 May 12 01:32:05 PM PDT 24 27649666502 ps
T937 /workspace/coverage/default/31.sram_ctrl_stress_all.4060837308 May 12 01:09:53 PM PDT 24 May 12 02:53:04 PM PDT 24 100037752212 ps
T938 /workspace/coverage/default/27.sram_ctrl_bijection.2747911401 May 12 01:09:05 PM PDT 24 May 12 01:40:56 PM PDT 24 423908793812 ps
T939 /workspace/coverage/default/37.sram_ctrl_partial_access.2670421123 May 12 01:10:41 PM PDT 24 May 12 01:11:14 PM PDT 24 1242063738 ps
T940 /workspace/coverage/default/34.sram_ctrl_ram_cfg.3499454830 May 12 01:10:19 PM PDT 24 May 12 01:10:23 PM PDT 24 347644181 ps
T941 /workspace/coverage/default/30.sram_ctrl_regwen.779708368 May 12 01:09:39 PM PDT 24 May 12 01:29:16 PM PDT 24 55317340614 ps
T942 /workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.2709303618 May 12 01:10:38 PM PDT 24 May 12 01:11:48 PM PDT 24 1442039863 ps
T49 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3011717613 May 12 01:00:39 PM PDT 24 May 12 01:00:41 PM PDT 24 227979992 ps
T97 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3908752303 May 12 01:00:58 PM PDT 24 May 12 01:01:00 PM PDT 24 102464736 ps
T50 /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.691460162 May 12 01:01:20 PM PDT 24 May 12 01:01:21 PM PDT 24 28379397 ps
T943 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.4064891162 May 12 01:01:12 PM PDT 24 May 12 01:01:16 PM PDT 24 164523288 ps
T94 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2822267554 May 12 01:00:53 PM PDT 24 May 12 01:00:55 PM PDT 24 14392031 ps
T944 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3331878737 May 12 01:01:08 PM PDT 24 May 12 01:01:12 PM PDT 24 726980998 ps
T945 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1637993174 May 12 01:01:16 PM PDT 24 May 12 01:01:20 PM PDT 24 69761654 ps
T946 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1908873436 May 12 01:00:45 PM PDT 24 May 12 01:00:50 PM PDT 24 557592529 ps
T947 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2242093639 May 12 01:00:41 PM PDT 24 May 12 01:00:45 PM PDT 24 3221504891 ps
T948 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.4168307448 May 12 01:00:49 PM PDT 24 May 12 01:00:51 PM PDT 24 81097331 ps
T949 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.600042421 May 12 01:01:19 PM PDT 24 May 12 01:01:22 PM PDT 24 29455482 ps
T95 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.453406553 May 12 01:00:49 PM PDT 24 May 12 01:00:51 PM PDT 24 595860372 ps
T51 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1032328403 May 12 01:00:40 PM PDT 24 May 12 01:00:41 PM PDT 24 66835149 ps
T950 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2185096556 May 12 01:01:05 PM PDT 24 May 12 01:01:08 PM PDT 24 132327335 ps
T951 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.431581292 May 12 01:01:08 PM PDT 24 May 12 01:01:13 PM PDT 24 211214761 ps
T52 /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1659411149 May 12 01:00:52 PM PDT 24 May 12 01:01:17 PM PDT 24 7331063065 ps
T53 /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1764611221 May 12 01:00:59 PM PDT 24 May 12 01:01:00 PM PDT 24 27651710 ps
T54 /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.508949871 May 12 01:01:18 PM PDT 24 May 12 01:01:48 PM PDT 24 6709078731 ps
T55 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.651182099 May 12 01:00:56 PM PDT 24 May 12 01:00:58 PM PDT 24 52880851 ps
T96 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.221328660 May 12 01:01:06 PM PDT 24 May 12 01:01:07 PM PDT 24 24093058 ps
T86 /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.952737992 May 12 01:01:05 PM PDT 24 May 12 01:01:07 PM PDT 24 30301448 ps
T952 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.4151396085 May 12 01:00:53 PM PDT 24 May 12 01:00:57 PM PDT 24 3120111833 ps
T56 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1029802104 May 12 01:00:52 PM PDT 24 May 12 01:00:54 PM PDT 24 30754852 ps
T57 /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2889578506 May 12 01:01:18 PM PDT 24 May 12 01:01:19 PM PDT 24 16488386 ps
T98 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1966620460 May 12 01:00:41 PM PDT 24 May 12 01:00:43 PM PDT 24 104887212 ps
T87 /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3621317408 May 12 01:01:13 PM PDT 24 May 12 01:01:14 PM PDT 24 21770548 ps
T58 /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3353845404 May 12 01:01:19 PM PDT 24 May 12 01:02:13 PM PDT 24 29391340446 ps
T88 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2828173371 May 12 01:01:18 PM PDT 24 May 12 01:01:19 PM PDT 24 20904694 ps
T953 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2532377884 May 12 01:00:43 PM PDT 24 May 12 01:00:44 PM PDT 24 16632425 ps
T99 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.889573040 May 12 01:01:09 PM PDT 24 May 12 01:01:12 PM PDT 24 262657520 ps
T68 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1007750781 May 12 01:01:06 PM PDT 24 May 12 01:01:07 PM PDT 24 28270042 ps
T954 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.772030935 May 12 01:00:58 PM PDT 24 May 12 01:01:01 PM PDT 24 270062713 ps
T69 /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1712108748 May 12 01:01:14 PM PDT 24 May 12 01:01:47 PM PDT 24 30783199262 ps
T955 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3593032246 May 12 01:00:55 PM PDT 24 May 12 01:00:56 PM PDT 24 43834581 ps
T956 /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2771245841 May 12 01:01:01 PM PDT 24 May 12 01:01:02 PM PDT 24 39457747 ps
T957 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1920334605 May 12 01:00:40 PM PDT 24 May 12 01:00:42 PM PDT 24 24496185 ps
T958 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3773811470 May 12 01:00:56 PM PDT 24 May 12 01:00:57 PM PDT 24 15027702 ps
T959 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2764716339 May 12 01:00:55 PM PDT 24 May 12 01:00:58 PM PDT 24 27384834 ps
T960 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.159205292 May 12 01:00:56 PM PDT 24 May 12 01:01:01 PM PDT 24 367196503 ps
T961 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1504406087 May 12 01:00:49 PM PDT 24 May 12 01:00:54 PM PDT 24 1248918650 ps
T962 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2859111118 May 12 01:01:17 PM PDT 24 May 12 01:01:18 PM PDT 24 80110052 ps
T963 /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2904461197 May 12 01:00:39 PM PDT 24 May 12 01:01:09 PM PDT 24 8052367169 ps
T964 /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.4292063646 May 12 01:01:09 PM PDT 24 May 12 01:01:11 PM PDT 24 24421245 ps
T965 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1247405669 May 12 01:01:20 PM PDT 24 May 12 01:01:23 PM PDT 24 148935960 ps
T107 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2189921132 May 12 01:01:21 PM PDT 24 May 12 01:01:24 PM PDT 24 284151305 ps
T70 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.53390730 May 12 01:01:11 PM PDT 24 May 12 01:01:13 PM PDT 24 150612264 ps
T108 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.4256513440 May 12 01:00:49 PM PDT 24 May 12 01:00:52 PM PDT 24 766382054 ps
T110 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1381011423 May 12 01:01:11 PM PDT 24 May 12 01:01:13 PM PDT 24 289920139 ps
T966 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2969153837 May 12 01:00:53 PM PDT 24 May 12 01:00:55 PM PDT 24 140074086 ps
T967 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2476923875 May 12 01:01:09 PM PDT 24 May 12 01:01:14 PM PDT 24 591675632 ps
T968 /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3566837696 May 12 01:00:48 PM PDT 24 May 12 01:01:40 PM PDT 24 43975389776 ps
T969 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2472825716 May 12 01:01:20 PM PDT 24 May 12 01:01:24 PM PDT 24 2668393807 ps
T970 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1064135714 May 12 01:01:10 PM PDT 24 May 12 01:01:14 PM PDT 24 357386031 ps
T971 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1461766852 May 12 01:01:09 PM PDT 24 May 12 01:01:12 PM PDT 24 225127728 ps
T71 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.736913082 May 12 01:01:01 PM PDT 24 May 12 01:01:02 PM PDT 24 18590393 ps
T72 /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2218812733 May 12 01:01:09 PM PDT 24 May 12 01:02:17 PM PDT 24 117180266988 ps
T972 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1850511487 May 12 01:01:12 PM PDT 24 May 12 01:01:14 PM PDT 24 10940464 ps
T973 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1698454559 May 12 01:00:56 PM PDT 24 May 12 01:01:00 PM PDT 24 1905327733 ps
T974 /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.573928920 May 12 01:01:05 PM PDT 24 May 12 01:01:33 PM PDT 24 3890550621 ps
T975 /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.4032000215 May 12 01:01:09 PM PDT 24 May 12 01:02:03 PM PDT 24 28293593317 ps
T976 /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1648902881 May 12 01:01:10 PM PDT 24 May 12 01:01:11 PM PDT 24 86912347 ps
T977 /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1053355036 May 12 01:00:53 PM PDT 24 May 12 01:00:54 PM PDT 24 25235579 ps
T978 /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1530281325 May 12 01:01:13 PM PDT 24 May 12 01:01:44 PM PDT 24 24619543125 ps
T979 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2601503211 May 12 01:01:00 PM PDT 24 May 12 01:01:04 PM PDT 24 316684189 ps
T980 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3833158655 May 12 01:00:51 PM PDT 24 May 12 01:00:54 PM PDT 24 174594646 ps
T981 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1636917658 May 12 01:01:19 PM PDT 24 May 12 01:01:23 PM PDT 24 367028030 ps
T982 /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3775072561 May 12 01:01:08 PM PDT 24 May 12 01:01:09 PM PDT 24 18357529 ps
T983 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2589697538 May 12 01:00:45 PM PDT 24 May 12 01:00:46 PM PDT 24 32081117 ps
T984 /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2269834780 May 12 01:00:53 PM PDT 24 May 12 01:00:55 PM PDT 24 32500380 ps
T985 /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2216173717 May 12 01:01:18 PM PDT 24 May 12 01:01:19 PM PDT 24 53489959 ps
T986 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1642411552 May 12 01:00:57 PM PDT 24 May 12 01:01:01 PM PDT 24 1369183922 ps
T987 /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.557493932 May 12 01:00:39 PM PDT 24 May 12 01:01:43 PM PDT 24 41483450571 ps
T112 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3921879846 May 12 01:01:12 PM PDT 24 May 12 01:01:14 PM PDT 24 760917878 ps
T988 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3868755753 May 12 01:00:43 PM PDT 24 May 12 01:00:46 PM PDT 24 1383673913 ps
T989 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2626666766 May 12 01:01:07 PM PDT 24 May 12 01:01:11 PM PDT 24 661916948 ps
T990 /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.939312730 May 12 01:00:44 PM PDT 24 May 12 01:01:10 PM PDT 24 3868476926 ps
T991 /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.754435622 May 12 01:01:01 PM PDT 24 May 12 01:01:56 PM PDT 24 29339438528 ps
T992 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2547791119 May 12 01:01:20 PM PDT 24 May 12 01:01:25 PM PDT 24 1393030817 ps
T993 /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2916159837 May 12 01:01:11 PM PDT 24 May 12 01:01:12 PM PDT 24 31039734 ps
T994 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1399744141 May 12 01:01:13 PM PDT 24 May 12 01:01:17 PM PDT 24 1439524303 ps
T995 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1303431529 May 12 01:01:09 PM PDT 24 May 12 01:01:14 PM PDT 24 360135905 ps
T996 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2032486489 May 12 01:01:01 PM PDT 24 May 12 01:01:02 PM PDT 24 38649598 ps
T997 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3777533198 May 12 01:01:08 PM PDT 24 May 12 01:01:09 PM PDT 24 12993113 ps
T998 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.479852786 May 12 01:00:43 PM PDT 24 May 12 01:00:48 PM PDT 24 889251999 ps
T113 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2326735842 May 12 01:01:15 PM PDT 24 May 12 01:01:17 PM PDT 24 442565475 ps
T999 /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2943868295 May 12 01:00:57 PM PDT 24 May 12 01:01:55 PM PDT 24 88292036233 ps
T1000 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.356621588 May 12 01:00:58 PM PDT 24 May 12 01:00:59 PM PDT 24 16137920 ps
T111 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.4031097840 May 12 01:01:08 PM PDT 24 May 12 01:01:11 PM PDT 24 405550536 ps
T1001 /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.996416182 May 12 01:01:08 PM PDT 24 May 12 01:01:39 PM PDT 24 16015229506 ps
T1002 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1117087079 May 12 01:00:58 PM PDT 24 May 12 01:01:02 PM PDT 24 1286502104 ps
T1003 /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2135045538 May 12 01:00:46 PM PDT 24 May 12 01:00:47 PM PDT 24 18420374 ps
T1004 /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3616903960 May 12 01:00:59 PM PDT 24 May 12 01:02:02 PM PDT 24 29353637684 ps
T118 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3573630162 May 12 01:01:19 PM PDT 24 May 12 01:01:21 PM PDT 24 321775871 ps
T1005 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2838304971 May 12 01:00:44 PM PDT 24 May 12 01:00:45 PM PDT 24 13705215 ps
T1006 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2959613092 May 12 01:00:46 PM PDT 24 May 12 01:00:47 PM PDT 24 46408960 ps
T115 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1818422833 May 12 01:00:53 PM PDT 24 May 12 01:00:55 PM PDT 24 269877043 ps
T1007 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2352204013 May 12 01:00:39 PM PDT 24 May 12 01:00:43 PM PDT 24 139650989 ps
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