Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	346308284	1			T1	470836		T2	108189		T3	499540
instr_valid_dis	302177564	1			T1	470836		T2	918386		T3	499540
instr_en	29792420	1			T2	163508		T4	153162		T18	26426

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	13346030	1			T2	78764		T4	63882		T18	50414
sram_ifetch_valid_disable	307198486	1			T1	470836		T2	975642		T3	499540
sram_ifetch_enable	25763768	1			T2	27488		T4	116946		T18	8134

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	346308284	1			T1	470836		T2	108189		T3	499540
hw_debug_en_valid_off	309918095	1			T1	470836		T2	976162		T3	499540
hw_debug_en_on	25657785	1			T2	53828		T4	215928		T18	97160

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	307198486	1			T1	470836		T2	975642		T3	499540
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	289122708	1			T1	470836		T2	918386		T3	499540
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	11162218	1			T2	57256		T4	76976		T18	24254
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	6407464	1			T2	55142		T132	34668		T49	6846
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1524478	1			T134	34446		T5	33816		T47	81688
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	3339612	1			T2	55142		T132	34668		T49	6846
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4028950	1			T2	2988		T4	52398		T18	50414
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1568212	1			T5	55900		T47	38478		T28	30200
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1478704	1			T2	2988		T4	52398		T132	20000
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	13682997	1			T2	50840		T4	120032		T18	46746
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3345447	1			T49	20000		T133	20000		T72	65016
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	5841500	1			T2	50840		T4	25554		T18	11294

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	12814956	1			T2	27488		T4	23788		T18	2172
lc_exec_en	7945838	1			T4	43498		T132	10356		T49	43846
valid_exec_dis	298475831	1			T1	470836		T2	921020		T3	499540
invalid_exec_dis	39109798	1			T2	106252		T4	180828		T18	58548