Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	142738716	1			T1	214019		T2	454533		T3	226865
triple_byte_access	2989999	1			T1	4375		T2	9031		T3	4595
halfword_access	4578430	1			T1	6485		T2	13727		T3	6870
byte_access	6379228	1			T1	8455		T2	18228		T3	9186
zero_access	1902067	1			T1	2084		T2	4493		T3	2254

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

79098952

1

T1

117477

T2

253444

T3

125098

auto[1]

79489488

1

T1

117941

T2

246568

T3

124672

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	71038113	1			T1	106759		T2	230442		T3	113639
auto[0]	triple_byte_access	1431534	1			T1	2143		T2	4601		T3	2351
auto[0]	halfword_access	2240726	1			T1	3271		T2	6955		T3	3438
auto[0]	byte_access	3264645	1			T1	4275		T2	9186		T3	4573
auto[0]	zero_access	1123934	1			T1	1029		T2	2260		T3	1097
auto[1]	word_access	71700603	1			T1	107260		T2	224091		T3	113226
auto[1]	triple_byte_access	1558465	1			T1	2232		T2	4430		T3	2244
auto[1]	halfword_access	2337704	1			T1	3214		T2	6772		T3	3432
auto[1]	byte_access	3114583	1			T1	4180		T2	9042		T3	4613
auto[1]	zero_access	778133	1			T1	1055		T2	2233		T3	1157