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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.09 99.81 96.99 100.00 100.00 98.60 99.70 98.52


Total test records in report: 1038
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T796 /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.1312667305 May 14 02:12:07 PM PDT 24 May 14 02:15:00 PM PDT 24 16237861252 ps
T797 /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.1143664614 May 14 02:11:53 PM PDT 24 May 14 02:12:02 PM PDT 24 3064124909 ps
T798 /workspace/coverage/default/47.sram_ctrl_stress_pipeline.4106076885 May 14 02:18:28 PM PDT 24 May 14 02:22:14 PM PDT 24 13845689298 ps
T799 /workspace/coverage/default/27.sram_ctrl_smoke.4154671521 May 14 02:14:23 PM PDT 24 May 14 02:14:39 PM PDT 24 3283826880 ps
T800 /workspace/coverage/default/5.sram_ctrl_executable.1950647321 May 14 02:12:01 PM PDT 24 May 14 02:25:27 PM PDT 24 41994939080 ps
T114 /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3604430283 May 14 02:11:56 PM PDT 24 May 14 02:12:04 PM PDT 24 290254673 ps
T801 /workspace/coverage/default/44.sram_ctrl_mem_walk.3849626587 May 14 02:18:05 PM PDT 24 May 14 02:20:42 PM PDT 24 42945848504 ps
T802 /workspace/coverage/default/7.sram_ctrl_smoke.11491818 May 14 02:12:04 PM PDT 24 May 14 02:12:21 PM PDT 24 1215630757 ps
T803 /workspace/coverage/default/8.sram_ctrl_bijection.2717272706 May 14 02:12:06 PM PDT 24 May 14 02:50:39 PM PDT 24 421831475301 ps
T804 /workspace/coverage/default/20.sram_ctrl_smoke.3994264577 May 14 02:13:21 PM PDT 24 May 14 02:13:36 PM PDT 24 1913417792 ps
T805 /workspace/coverage/default/18.sram_ctrl_bijection.130553569 May 14 02:13:02 PM PDT 24 May 14 02:52:09 PM PDT 24 137948458973 ps
T806 /workspace/coverage/default/15.sram_ctrl_max_throughput.209133371 May 14 02:12:41 PM PDT 24 May 14 02:14:58 PM PDT 24 761808394 ps
T807 /workspace/coverage/default/17.sram_ctrl_stress_all.3008725326 May 14 02:12:55 PM PDT 24 May 14 02:33:48 PM PDT 24 22167886148 ps
T808 /workspace/coverage/default/2.sram_ctrl_access_during_key_req.1333705254 May 14 02:11:50 PM PDT 24 May 14 02:34:34 PM PDT 24 16541353289 ps
T809 /workspace/coverage/default/42.sram_ctrl_mem_walk.3719389471 May 14 02:17:37 PM PDT 24 May 14 02:19:42 PM PDT 24 2000163642 ps
T810 /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.472167792 May 14 02:17:29 PM PDT 24 May 14 02:17:47 PM PDT 24 742594606 ps
T811 /workspace/coverage/default/0.sram_ctrl_access_during_key_req.852460265 May 14 02:11:42 PM PDT 24 May 14 02:14:50 PM PDT 24 2343796571 ps
T812 /workspace/coverage/default/8.sram_ctrl_access_during_key_req.2027963362 May 14 02:12:07 PM PDT 24 May 14 02:26:47 PM PDT 24 14568089611 ps
T813 /workspace/coverage/default/33.sram_ctrl_smoke.38245784 May 14 02:15:34 PM PDT 24 May 14 02:17:49 PM PDT 24 4291083635 ps
T814 /workspace/coverage/default/18.sram_ctrl_smoke.3113245784 May 14 02:12:56 PM PDT 24 May 14 02:13:54 PM PDT 24 14623367914 ps
T815 /workspace/coverage/default/1.sram_ctrl_stress_all.1170882072 May 14 02:11:50 PM PDT 24 May 14 03:41:35 PM PDT 24 435954244654 ps
T816 /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.3296850645 May 14 02:15:46 PM PDT 24 May 14 02:15:59 PM PDT 24 281923822 ps
T817 /workspace/coverage/default/31.sram_ctrl_stress_pipeline.489486843 May 14 02:15:06 PM PDT 24 May 14 02:19:25 PM PDT 24 22270682079 ps
T818 /workspace/coverage/default/22.sram_ctrl_mem_partial_access.4060912578 May 14 02:13:46 PM PDT 24 May 14 02:15:03 PM PDT 24 2760321996 ps
T819 /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.795617302 May 14 02:19:00 PM PDT 24 May 14 02:22:04 PM PDT 24 2511400575 ps
T820 /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.655665099 May 14 02:12:02 PM PDT 24 May 14 02:14:29 PM PDT 24 877814651 ps
T821 /workspace/coverage/default/46.sram_ctrl_access_during_key_req.3060664615 May 14 02:18:22 PM PDT 24 May 14 02:39:45 PM PDT 24 13838329918 ps
T822 /workspace/coverage/default/47.sram_ctrl_smoke.3728405058 May 14 02:18:28 PM PDT 24 May 14 02:18:46 PM PDT 24 563339243 ps
T823 /workspace/coverage/default/0.sram_ctrl_multiple_keys.253715150 May 14 02:11:46 PM PDT 24 May 14 02:21:17 PM PDT 24 9924636484 ps
T824 /workspace/coverage/default/49.sram_ctrl_bijection.3007191995 May 14 02:19:07 PM PDT 24 May 14 02:39:47 PM PDT 24 115852632064 ps
T825 /workspace/coverage/default/39.sram_ctrl_stress_pipeline.3652002268 May 14 02:16:55 PM PDT 24 May 14 02:21:14 PM PDT 24 18185537800 ps
T826 /workspace/coverage/default/10.sram_ctrl_lc_escalation.2496193091 May 14 02:12:14 PM PDT 24 May 14 02:13:42 PM PDT 24 14248573390 ps
T827 /workspace/coverage/default/42.sram_ctrl_smoke.1800414130 May 14 02:17:30 PM PDT 24 May 14 02:17:38 PM PDT 24 2854556188 ps
T828 /workspace/coverage/default/31.sram_ctrl_partial_access.1893159064 May 14 02:15:08 PM PDT 24 May 14 02:15:24 PM PDT 24 4482155066 ps
T829 /workspace/coverage/default/38.sram_ctrl_multiple_keys.2425587769 May 14 02:16:43 PM PDT 24 May 14 02:35:15 PM PDT 24 53279803569 ps
T830 /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.1708641132 May 14 02:11:43 PM PDT 24 May 14 02:13:36 PM PDT 24 768676882 ps
T831 /workspace/coverage/default/15.sram_ctrl_regwen.2010608863 May 14 02:12:40 PM PDT 24 May 14 02:22:06 PM PDT 24 2814268607 ps
T832 /workspace/coverage/default/19.sram_ctrl_smoke.1722819850 May 14 02:13:08 PM PDT 24 May 14 02:13:33 PM PDT 24 1421542856 ps
T833 /workspace/coverage/default/21.sram_ctrl_access_during_key_req.1862371233 May 14 02:13:32 PM PDT 24 May 14 02:39:23 PM PDT 24 13001095271 ps
T834 /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.1655455033 May 14 02:12:31 PM PDT 24 May 14 02:12:49 PM PDT 24 535870043 ps
T835 /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.890649040 May 14 02:12:26 PM PDT 24 May 14 02:12:38 PM PDT 24 6199743742 ps
T836 /workspace/coverage/default/7.sram_ctrl_executable.220868760 May 14 02:12:07 PM PDT 24 May 14 02:22:15 PM PDT 24 11446902329 ps
T837 /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1156477010 May 14 02:18:39 PM PDT 24 May 14 02:19:06 PM PDT 24 781304127 ps
T838 /workspace/coverage/default/48.sram_ctrl_access_during_key_req.1461149673 May 14 02:18:57 PM PDT 24 May 14 02:27:05 PM PDT 24 27507922374 ps
T839 /workspace/coverage/default/17.sram_ctrl_executable.929589625 May 14 02:12:56 PM PDT 24 May 14 02:21:00 PM PDT 24 64217182844 ps
T840 /workspace/coverage/default/15.sram_ctrl_executable.2666837162 May 14 02:12:41 PM PDT 24 May 14 02:33:52 PM PDT 24 159770201510 ps
T841 /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2970519840 May 14 02:11:46 PM PDT 24 May 14 02:21:43 PM PDT 24 28116292044 ps
T842 /workspace/coverage/default/6.sram_ctrl_lc_escalation.1953686349 May 14 02:12:00 PM PDT 24 May 14 02:12:26 PM PDT 24 4164173204 ps
T843 /workspace/coverage/default/13.sram_ctrl_regwen.4271589921 May 14 02:12:23 PM PDT 24 May 14 02:15:03 PM PDT 24 4910929281 ps
T844 /workspace/coverage/default/44.sram_ctrl_bijection.1615849196 May 14 02:17:55 PM PDT 24 May 14 02:29:04 PM PDT 24 33967011485 ps
T845 /workspace/coverage/default/28.sram_ctrl_regwen.1670560327 May 14 02:14:41 PM PDT 24 May 14 02:27:53 PM PDT 24 11894750365 ps
T846 /workspace/coverage/default/6.sram_ctrl_regwen.1161029071 May 14 02:11:58 PM PDT 24 May 14 02:16:18 PM PDT 24 15675541264 ps
T847 /workspace/coverage/default/39.sram_ctrl_ram_cfg.1286959564 May 14 02:16:55 PM PDT 24 May 14 02:16:59 PM PDT 24 1291367398 ps
T848 /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.2639660908 May 14 02:13:16 PM PDT 24 May 14 02:13:29 PM PDT 24 892851826 ps
T849 /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.3338389569 May 14 02:14:36 PM PDT 24 May 14 02:14:43 PM PDT 24 2477232338 ps
T850 /workspace/coverage/default/42.sram_ctrl_stress_pipeline.3884898355 May 14 02:17:30 PM PDT 24 May 14 02:20:47 PM PDT 24 7852072025 ps
T851 /workspace/coverage/default/40.sram_ctrl_stress_all.3769686498 May 14 02:17:12 PM PDT 24 May 14 03:13:21 PM PDT 24 52677152636 ps
T852 /workspace/coverage/default/33.sram_ctrl_executable.402909549 May 14 02:15:41 PM PDT 24 May 14 02:40:51 PM PDT 24 75084745634 ps
T853 /workspace/coverage/default/23.sram_ctrl_mem_walk.2348295328 May 14 02:13:55 PM PDT 24 May 14 02:16:21 PM PDT 24 7262689212 ps
T854 /workspace/coverage/default/44.sram_ctrl_stress_pipeline.4010990224 May 14 02:17:54 PM PDT 24 May 14 02:22:45 PM PDT 24 4338388011 ps
T855 /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.3619659109 May 14 02:14:15 PM PDT 24 May 14 02:21:42 PM PDT 24 16741327083 ps
T856 /workspace/coverage/default/11.sram_ctrl_partial_access.3427145192 May 14 02:12:13 PM PDT 24 May 14 02:12:18 PM PDT 24 372331663 ps
T857 /workspace/coverage/default/19.sram_ctrl_multiple_keys.1783651169 May 14 02:13:08 PM PDT 24 May 14 02:46:20 PM PDT 24 104510894039 ps
T858 /workspace/coverage/default/34.sram_ctrl_mem_walk.1109304653 May 14 02:16:00 PM PDT 24 May 14 02:18:42 PM PDT 24 10882298677 ps
T859 /workspace/coverage/default/45.sram_ctrl_lc_escalation.1555932851 May 14 02:18:14 PM PDT 24 May 14 02:19:34 PM PDT 24 96973501786 ps
T860 /workspace/coverage/default/4.sram_ctrl_ram_cfg.783423691 May 14 02:12:00 PM PDT 24 May 14 02:12:04 PM PDT 24 726222315 ps
T861 /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.3990319541 May 14 02:17:38 PM PDT 24 May 14 02:18:12 PM PDT 24 1037380100 ps
T862 /workspace/coverage/default/12.sram_ctrl_lc_escalation.1075605956 May 14 02:12:27 PM PDT 24 May 14 02:13:32 PM PDT 24 39152018167 ps
T863 /workspace/coverage/default/20.sram_ctrl_access_during_key_req.2313090505 May 14 02:13:22 PM PDT 24 May 14 02:29:30 PM PDT 24 21966412820 ps
T864 /workspace/coverage/default/37.sram_ctrl_alert_test.3486972276 May 14 02:16:44 PM PDT 24 May 14 02:16:45 PM PDT 24 32307154 ps
T865 /workspace/coverage/default/20.sram_ctrl_mem_walk.579052132 May 14 02:13:22 PM PDT 24 May 14 02:15:19 PM PDT 24 8968587483 ps
T866 /workspace/coverage/default/35.sram_ctrl_regwen.105542421 May 14 02:16:05 PM PDT 24 May 14 02:32:23 PM PDT 24 50684768264 ps
T867 /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.2910807881 May 14 02:13:08 PM PDT 24 May 14 02:13:44 PM PDT 24 2888229917 ps
T868 /workspace/coverage/default/10.sram_ctrl_max_throughput.4020946129 May 14 02:12:16 PM PDT 24 May 14 02:13:17 PM PDT 24 1557013504 ps
T869 /workspace/coverage/default/44.sram_ctrl_stress_all.113294277 May 14 02:18:05 PM PDT 24 May 14 03:07:24 PM PDT 24 70166790390 ps
T870 /workspace/coverage/default/42.sram_ctrl_executable.4156009667 May 14 02:17:38 PM PDT 24 May 14 02:36:37 PM PDT 24 44681534453 ps
T871 /workspace/coverage/default/5.sram_ctrl_multiple_keys.197024259 May 14 02:11:57 PM PDT 24 May 14 02:16:59 PM PDT 24 17294971057 ps
T872 /workspace/coverage/default/22.sram_ctrl_bijection.1874715518 May 14 02:13:38 PM PDT 24 May 14 02:24:15 PM PDT 24 29317741740 ps
T873 /workspace/coverage/default/29.sram_ctrl_access_during_key_req.4007907412 May 14 02:14:52 PM PDT 24 May 14 02:22:20 PM PDT 24 15208197075 ps
T874 /workspace/coverage/default/25.sram_ctrl_regwen.143837069 May 14 02:14:14 PM PDT 24 May 14 02:43:18 PM PDT 24 117797348397 ps
T115 /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.2228308055 May 14 02:12:56 PM PDT 24 May 14 02:13:53 PM PDT 24 11661123697 ps
T875 /workspace/coverage/default/43.sram_ctrl_lc_escalation.3726731223 May 14 02:17:46 PM PDT 24 May 14 02:18:45 PM PDT 24 16150698113 ps
T876 /workspace/coverage/default/13.sram_ctrl_access_during_key_req.2459195614 May 14 02:12:23 PM PDT 24 May 14 02:13:34 PM PDT 24 2871565797 ps
T877 /workspace/coverage/default/36.sram_ctrl_alert_test.95472212 May 14 02:16:24 PM PDT 24 May 14 02:16:26 PM PDT 24 90864329 ps
T878 /workspace/coverage/default/13.sram_ctrl_mem_partial_access.3518003227 May 14 02:12:25 PM PDT 24 May 14 02:14:34 PM PDT 24 1650937286 ps
T879 /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.3179992265 May 14 02:12:38 PM PDT 24 May 14 02:19:53 PM PDT 24 54324897837 ps
T880 /workspace/coverage/default/46.sram_ctrl_smoke.3154183202 May 14 02:18:21 PM PDT 24 May 14 02:18:39 PM PDT 24 4965071806 ps
T881 /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.1612700261 May 14 02:14:14 PM PDT 24 May 14 02:17:09 PM PDT 24 3147849439 ps
T882 /workspace/coverage/default/1.sram_ctrl_partial_access.3990925438 May 14 02:11:43 PM PDT 24 May 14 02:13:30 PM PDT 24 1009974944 ps
T883 /workspace/coverage/default/47.sram_ctrl_mem_walk.609724878 May 14 02:18:39 PM PDT 24 May 14 02:22:40 PM PDT 24 4067113317 ps
T884 /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3154309525 May 14 02:18:15 PM PDT 24 May 14 02:25:20 PM PDT 24 3252706480 ps
T885 /workspace/coverage/default/16.sram_ctrl_lc_escalation.472003048 May 14 02:12:46 PM PDT 24 May 14 02:14:14 PM PDT 24 47015878242 ps
T886 /workspace/coverage/default/2.sram_ctrl_alert_test.2762213939 May 14 02:11:49 PM PDT 24 May 14 02:11:51 PM PDT 24 57477088 ps
T887 /workspace/coverage/default/45.sram_ctrl_multiple_keys.1787524158 May 14 02:18:04 PM PDT 24 May 14 02:33:45 PM PDT 24 15567546496 ps
T888 /workspace/coverage/default/16.sram_ctrl_smoke.2380574321 May 14 02:12:44 PM PDT 24 May 14 02:13:44 PM PDT 24 4474060317 ps
T889 /workspace/coverage/default/1.sram_ctrl_stress_pipeline.3999709140 May 14 02:11:43 PM PDT 24 May 14 02:16:54 PM PDT 24 27261157820 ps
T890 /workspace/coverage/default/0.sram_ctrl_bijection.3101259543 May 14 02:11:41 PM PDT 24 May 14 02:43:10 PM PDT 24 460182072803 ps
T891 /workspace/coverage/default/29.sram_ctrl_regwen.226204491 May 14 02:14:51 PM PDT 24 May 14 02:28:31 PM PDT 24 42232496197 ps
T892 /workspace/coverage/default/18.sram_ctrl_alert_test.4073758344 May 14 02:13:08 PM PDT 24 May 14 02:13:10 PM PDT 24 54749736 ps
T893 /workspace/coverage/default/17.sram_ctrl_multiple_keys.3709636510 May 14 02:12:49 PM PDT 24 May 14 02:13:20 PM PDT 24 17099280952 ps
T894 /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.4098242410 May 14 02:12:15 PM PDT 24 May 14 02:12:43 PM PDT 24 718874235 ps
T895 /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3647504136 May 14 02:11:53 PM PDT 24 May 14 02:12:36 PM PDT 24 2772260835 ps
T896 /workspace/coverage/default/43.sram_ctrl_stress_pipeline.4263091121 May 14 02:17:37 PM PDT 24 May 14 02:21:51 PM PDT 24 6453623128 ps
T897 /workspace/coverage/default/0.sram_ctrl_smoke.2101057768 May 14 02:11:40 PM PDT 24 May 14 02:13:17 PM PDT 24 440986146 ps
T898 /workspace/coverage/default/5.sram_ctrl_alert_test.712727310 May 14 02:12:01 PM PDT 24 May 14 02:12:03 PM PDT 24 74835000 ps
T899 /workspace/coverage/default/24.sram_ctrl_mem_walk.603252448 May 14 02:14:04 PM PDT 24 May 14 02:16:33 PM PDT 24 42934539981 ps
T900 /workspace/coverage/default/23.sram_ctrl_regwen.3422599071 May 14 02:13:57 PM PDT 24 May 14 02:19:22 PM PDT 24 9409354499 ps
T901 /workspace/coverage/default/34.sram_ctrl_mem_partial_access.465415406 May 14 02:15:57 PM PDT 24 May 14 02:18:03 PM PDT 24 1691733671 ps
T902 /workspace/coverage/default/4.sram_ctrl_smoke.1458873452 May 14 02:11:53 PM PDT 24 May 14 02:12:16 PM PDT 24 3502254551 ps
T903 /workspace/coverage/default/4.sram_ctrl_executable.3228910810 May 14 02:12:00 PM PDT 24 May 14 02:25:30 PM PDT 24 8844051301 ps
T904 /workspace/coverage/default/38.sram_ctrl_stress_pipeline.3935776863 May 14 02:16:42 PM PDT 24 May 14 02:20:45 PM PDT 24 12234123753 ps
T905 /workspace/coverage/default/9.sram_ctrl_stress_pipeline.4153148950 May 14 02:12:15 PM PDT 24 May 14 02:15:46 PM PDT 24 7682033389 ps
T906 /workspace/coverage/default/9.sram_ctrl_access_during_key_req.2597620489 May 14 02:12:14 PM PDT 24 May 14 02:39:25 PM PDT 24 102595582464 ps
T907 /workspace/coverage/default/37.sram_ctrl_partial_access.2023343727 May 14 02:16:33 PM PDT 24 May 14 02:18:41 PM PDT 24 987703598 ps
T908 /workspace/coverage/default/7.sram_ctrl_lc_escalation.3846539687 May 14 02:12:08 PM PDT 24 May 14 02:13:10 PM PDT 24 16922439311 ps
T909 /workspace/coverage/default/41.sram_ctrl_executable.3203956596 May 14 02:17:23 PM PDT 24 May 14 02:37:11 PM PDT 24 21645325725 ps
T910 /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.2072313599 May 14 02:14:04 PM PDT 24 May 14 02:14:41 PM PDT 24 3822456266 ps
T911 /workspace/coverage/default/12.sram_ctrl_stress_pipeline.537764538 May 14 02:12:25 PM PDT 24 May 14 02:15:58 PM PDT 24 11354251084 ps
T912 /workspace/coverage/default/19.sram_ctrl_partial_access.2914922797 May 14 02:13:08 PM PDT 24 May 14 02:13:33 PM PDT 24 936606024 ps
T913 /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.2892303294 May 14 02:18:20 PM PDT 24 May 14 02:20:09 PM PDT 24 769620802 ps
T914 /workspace/coverage/default/22.sram_ctrl_stress_all.2582102213 May 14 02:13:47 PM PDT 24 May 14 03:42:17 PM PDT 24 935099005720 ps
T915 /workspace/coverage/default/7.sram_ctrl_alert_test.600725730 May 14 02:12:05 PM PDT 24 May 14 02:12:07 PM PDT 24 48049697 ps
T916 /workspace/coverage/default/3.sram_ctrl_lc_escalation.421855540 May 14 02:11:53 PM PDT 24 May 14 02:12:08 PM PDT 24 1987592652 ps
T917 /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.2058257968 May 14 02:13:58 PM PDT 24 May 14 02:16:06 PM PDT 24 1638975916 ps
T918 /workspace/coverage/default/35.sram_ctrl_partial_access.1949125145 May 14 02:15:58 PM PDT 24 May 14 02:16:05 PM PDT 24 2652680455 ps
T919 /workspace/coverage/default/32.sram_ctrl_mem_walk.1021905037 May 14 02:15:37 PM PDT 24 May 14 02:17:39 PM PDT 24 7900450428 ps
T920 /workspace/coverage/default/49.sram_ctrl_stress_pipeline.2189844079 May 14 02:19:08 PM PDT 24 May 14 02:22:58 PM PDT 24 15897410109 ps
T921 /workspace/coverage/default/0.sram_ctrl_mem_walk.3102429844 May 14 02:11:45 PM PDT 24 May 14 02:13:57 PM PDT 24 21929795970 ps
T922 /workspace/coverage/default/26.sram_ctrl_partial_access.2760026918 May 14 02:14:15 PM PDT 24 May 14 02:14:26 PM PDT 24 696781204 ps
T923 /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.1818483428 May 14 02:18:04 PM PDT 24 May 14 02:28:15 PM PDT 24 270162949771 ps
T924 /workspace/coverage/default/7.sram_ctrl_regwen.3473348677 May 14 02:12:05 PM PDT 24 May 14 02:12:39 PM PDT 24 1335314711 ps
T925 /workspace/coverage/default/5.sram_ctrl_partial_access.41813558 May 14 02:11:58 PM PDT 24 May 14 02:12:10 PM PDT 24 4105188740 ps
T926 /workspace/coverage/default/20.sram_ctrl_lc_escalation.1998570311 May 14 02:13:23 PM PDT 24 May 14 02:14:09 PM PDT 24 13258771614 ps
T927 /workspace/coverage/default/19.sram_ctrl_mem_walk.3010089473 May 14 02:13:18 PM PDT 24 May 14 02:15:45 PM PDT 24 17884337840 ps
T928 /workspace/coverage/default/25.sram_ctrl_stress_pipeline.3523670269 May 14 02:14:15 PM PDT 24 May 14 02:19:19 PM PDT 24 10026803339 ps
T929 /workspace/coverage/default/37.sram_ctrl_stress_all.477120647 May 14 02:16:42 PM PDT 24 May 14 02:44:40 PM PDT 24 33070683636 ps
T930 /workspace/coverage/default/40.sram_ctrl_mem_walk.3022459700 May 14 02:17:18 PM PDT 24 May 14 02:21:16 PM PDT 24 15757618851 ps
T931 /workspace/coverage/default/21.sram_ctrl_mem_partial_access.1836349577 May 14 02:13:29 PM PDT 24 May 14 02:14:39 PM PDT 24 3928447316 ps
T932 /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.2750611912 May 14 02:16:02 PM PDT 24 May 14 02:18:21 PM PDT 24 1384666026 ps
T933 /workspace/coverage/default/7.sram_ctrl_mem_walk.3928026723 May 14 02:12:07 PM PDT 24 May 14 02:16:53 PM PDT 24 55102183925 ps
T934 /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.1499151519 May 14 02:13:02 PM PDT 24 May 14 02:20:47 PM PDT 24 8598282866 ps
T935 /workspace/coverage/default/8.sram_ctrl_regwen.811118364 May 14 02:12:07 PM PDT 24 May 14 02:37:13 PM PDT 24 3946249159 ps
T936 /workspace/coverage/default/42.sram_ctrl_mem_partial_access.2179592231 May 14 02:17:38 PM PDT 24 May 14 02:18:49 PM PDT 24 955732787 ps
T937 /workspace/coverage/default/11.sram_ctrl_multiple_keys.1390031255 May 14 02:12:13 PM PDT 24 May 14 02:38:44 PM PDT 24 44110326829 ps
T938 /workspace/coverage/default/24.sram_ctrl_mem_partial_access.535114989 May 14 02:14:05 PM PDT 24 May 14 02:16:07 PM PDT 24 3177306438 ps
T939 /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.3498865830 May 14 02:17:12 PM PDT 24 May 14 02:18:38 PM PDT 24 3420790462 ps
T940 /workspace/coverage/default/8.sram_ctrl_mem_partial_access.3943965476 May 14 02:12:05 PM PDT 24 May 14 02:13:10 PM PDT 24 2108395870 ps
T941 /workspace/coverage/default/23.sram_ctrl_ram_cfg.2126443746 May 14 02:13:56 PM PDT 24 May 14 02:14:00 PM PDT 24 560767370 ps
T942 /workspace/coverage/default/37.sram_ctrl_bijection.2880095804 May 14 02:16:33 PM PDT 24 May 14 02:27:29 PM PDT 24 9955250928 ps
T943 /workspace/coverage/default/35.sram_ctrl_access_during_key_req.3064102028 May 14 02:15:58 PM PDT 24 May 14 02:29:00 PM PDT 24 38564603073 ps
T944 /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.3383469964 May 14 02:16:55 PM PDT 24 May 14 02:17:44 PM PDT 24 761865474 ps
T945 /workspace/coverage/default/8.sram_ctrl_alert_test.2081445652 May 14 02:12:03 PM PDT 24 May 14 02:12:06 PM PDT 24 20572016 ps
T946 /workspace/coverage/default/25.sram_ctrl_partial_access.159209508 May 14 02:14:15 PM PDT 24 May 14 02:14:31 PM PDT 24 1867989539 ps
T947 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1875010060 May 14 01:35:41 PM PDT 24 May 14 01:35:45 PM PDT 24 83565115 ps
T60 /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.519580067 May 14 01:35:48 PM PDT 24 May 14 01:36:43 PM PDT 24 7180207336 ps
T107 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.462936113 May 14 01:35:48 PM PDT 24 May 14 01:35:53 PM PDT 24 140880136 ps
T61 /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.632569243 May 14 01:35:52 PM PDT 24 May 14 01:35:56 PM PDT 24 68105071 ps
T62 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1689588250 May 14 01:35:55 PM PDT 24 May 14 01:35:59 PM PDT 24 14307202 ps
T948 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3018873048 May 14 01:35:55 PM PDT 24 May 14 01:36:03 PM PDT 24 1363892287 ps
T104 /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3299874020 May 14 01:35:44 PM PDT 24 May 14 01:36:18 PM PDT 24 14832979337 ps
T949 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3309093971 May 14 01:35:47 PM PDT 24 May 14 01:35:55 PM PDT 24 78087528 ps
T950 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3082512463 May 14 01:35:50 PM PDT 24 May 14 01:35:58 PM PDT 24 718264571 ps
T108 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3129469842 May 14 01:35:41 PM PDT 24 May 14 01:35:45 PM PDT 24 114558226 ps
T63 /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.4250591171 May 14 01:35:41 PM PDT 24 May 14 01:35:44 PM PDT 24 16447750 ps
T105 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1533434376 May 14 01:35:45 PM PDT 24 May 14 01:35:50 PM PDT 24 13275217 ps
T109 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3701821069 May 14 01:35:48 PM PDT 24 May 14 01:35:54 PM PDT 24 708436668 ps
T120 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2665031796 May 14 01:35:46 PM PDT 24 May 14 01:35:53 PM PDT 24 271054418 ps
T106 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1690610772 May 14 01:35:41 PM PDT 24 May 14 01:35:43 PM PDT 24 44707572 ps
T64 /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1224422007 May 14 01:35:53 PM PDT 24 May 14 01:36:25 PM PDT 24 15483923917 ps
T65 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3374742086 May 14 01:35:45 PM PDT 24 May 14 01:35:49 PM PDT 24 47427006 ps
T66 /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3148052966 May 14 01:35:57 PM PDT 24 May 14 01:36:00 PM PDT 24 11729753 ps
T951 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.260807447 May 14 01:35:49 PM PDT 24 May 14 01:35:59 PM PDT 24 6926478279 ps
T121 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.892940392 May 14 01:35:41 PM PDT 24 May 14 01:35:44 PM PDT 24 222586643 ps
T952 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3746438745 May 14 01:35:46 PM PDT 24 May 14 01:35:56 PM PDT 24 192502615 ps
T124 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2258674772 May 14 01:35:49 PM PDT 24 May 14 01:35:56 PM PDT 24 279634608 ps
T100 /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.424053800 May 14 01:35:48 PM PDT 24 May 14 01:35:53 PM PDT 24 166212054 ps
T953 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.468457415 May 14 01:35:51 PM PDT 24 May 14 01:35:58 PM PDT 24 752655895 ps
T67 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3962848444 May 14 01:35:48 PM PDT 24 May 14 01:35:52 PM PDT 24 42876797 ps
T68 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3135798405 May 14 01:35:41 PM PDT 24 May 14 01:35:42 PM PDT 24 14564241 ps
T101 /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3451817922 May 14 01:35:49 PM PDT 24 May 14 01:35:54 PM PDT 24 18391816 ps
T954 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1099291200 May 14 01:35:56 PM PDT 24 May 14 01:36:02 PM PDT 24 89228548 ps
T955 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1444926314 May 14 01:35:45 PM PDT 24 May 14 01:35:53 PM PDT 24 361175437 ps
T69 /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.991990240 May 14 01:35:47 PM PDT 24 May 14 01:35:52 PM PDT 24 68756825 ps
T956 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3170904695 May 14 01:35:58 PM PDT 24 May 14 01:36:04 PM PDT 24 139754123 ps
T102 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2440141970 May 14 01:35:09 PM PDT 24 May 14 01:35:10 PM PDT 24 40103456 ps
T957 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3674447530 May 14 01:35:57 PM PDT 24 May 14 01:36:00 PM PDT 24 11170339 ps
T958 /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1665353638 May 14 01:36:00 PM PDT 24 May 14 01:36:02 PM PDT 24 127311279 ps
T959 /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2195185776 May 14 01:35:46 PM PDT 24 May 14 01:35:51 PM PDT 24 86825386 ps
T78 /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.4276144609 May 14 01:35:52 PM PDT 24 May 14 01:36:23 PM PDT 24 3776356940 ps
T126 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3058178571 May 14 01:35:08 PM PDT 24 May 14 01:35:11 PM PDT 24 902191745 ps
T960 /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2202743716 May 14 01:35:43 PM PDT 24 May 14 01:35:46 PM PDT 24 29802378 ps
T961 /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.945840603 May 14 01:35:50 PM PDT 24 May 14 01:35:55 PM PDT 24 26304751 ps
T79 /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2534547814 May 14 01:35:41 PM PDT 24 May 14 01:36:34 PM PDT 24 73672603868 ps
T122 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2787770131 May 14 01:35:46 PM PDT 24 May 14 01:35:52 PM PDT 24 271603818 ps
T962 /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.96858039 May 14 01:35:49 PM PDT 24 May 14 01:35:54 PM PDT 24 36544951 ps
T80 /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3491437568 May 14 01:35:52 PM PDT 24 May 14 01:36:43 PM PDT 24 7113667788 ps
T963 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3723804371 May 14 01:35:43 PM PDT 24 May 14 01:35:49 PM PDT 24 698570118 ps
T964 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1586486557 May 14 01:35:44 PM PDT 24 May 14 01:35:51 PM PDT 24 1388222482 ps
T965 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3200854128 May 14 01:35:41 PM PDT 24 May 14 01:35:44 PM PDT 24 44623167 ps
T131 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1417953656 May 14 01:35:42 PM PDT 24 May 14 01:35:47 PM PDT 24 262905527 ps
T966 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.926655199 May 14 01:35:42 PM PDT 24 May 14 01:35:47 PM PDT 24 694382378 ps
T967 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1215299404 May 14 01:35:46 PM PDT 24 May 14 01:35:54 PM PDT 24 2051231695 ps
T81 /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.917211638 May 14 01:35:45 PM PDT 24 May 14 01:36:15 PM PDT 24 4192940400 ps
T968 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1713259529 May 14 01:35:57 PM PDT 24 May 14 01:36:03 PM PDT 24 1416313812 ps
T969 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2916914288 May 14 01:35:41 PM PDT 24 May 14 01:35:44 PM PDT 24 47360851 ps
T970 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.272799696 May 14 01:35:34 PM PDT 24 May 14 01:35:40 PM PDT 24 1347452624 ps
T971 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.533102670 May 14 01:35:45 PM PDT 24 May 14 01:35:51 PM PDT 24 31139624 ps
T972 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.464438679 May 14 01:35:45 PM PDT 24 May 14 01:35:52 PM PDT 24 707613697 ps
T82 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.748657955 May 14 01:35:41 PM PDT 24 May 14 01:35:43 PM PDT 24 17430934 ps
T83 /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.214047393 May 14 01:35:49 PM PDT 24 May 14 01:36:40 PM PDT 24 7329783745 ps
T973 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1765979106 May 14 01:35:43 PM PDT 24 May 14 01:35:49 PM PDT 24 31249788 ps
T974 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3021066432 May 14 01:35:56 PM PDT 24 May 14 01:36:03 PM PDT 24 569801627 ps
T975 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3253364759 May 14 01:35:41 PM PDT 24 May 14 01:35:46 PM PDT 24 708685894 ps
T976 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3865372458 May 14 01:35:47 PM PDT 24 May 14 01:35:56 PM PDT 24 1405679299 ps
T977 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1235590099 May 14 01:35:47 PM PDT 24 May 14 01:35:53 PM PDT 24 71107597 ps
T978 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1895113065 May 14 01:35:50 PM PDT 24 May 14 01:35:55 PM PDT 24 25294160 ps
T979 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3763868510 May 14 01:35:57 PM PDT 24 May 14 01:36:04 PM PDT 24 2047053261 ps
T980 /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3766355757 May 14 01:35:52 PM PDT 24 May 14 01:35:57 PM PDT 24 99203044 ps
T93 /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.181767213 May 14 01:35:44 PM PDT 24 May 14 01:36:38 PM PDT 24 14808612172 ps
T129 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2022792248 May 14 01:35:47 PM PDT 24 May 14 01:35:53 PM PDT 24 187825962 ps
T981 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2961110889 May 14 01:35:41 PM PDT 24 May 14 01:35:44 PM PDT 24 38716839 ps
T98 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2068737998 May 14 01:35:43 PM PDT 24 May 14 01:35:47 PM PDT 24 37863307 ps
T982 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1499663254 May 14 01:35:49 PM PDT 24 May 14 01:35:57 PM PDT 24 359524572 ps
T983 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.888684329 May 14 01:35:10 PM PDT 24 May 14 01:35:15 PM PDT 24 363091350 ps
T127 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3070196302 May 14 01:35:57 PM PDT 24 May 14 01:36:01 PM PDT 24 348424244 ps
T984 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1140170746 May 14 01:35:45 PM PDT 24 May 14 01:35:52 PM PDT 24 281239478 ps
T985 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1413200162 May 14 01:35:55 PM PDT 24 May 14 01:36:01 PM PDT 24 121911919 ps
T94 /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.33085060 May 14 01:35:47 PM PDT 24 May 14 01:36:48 PM PDT 24 29436457961 ps
T95 /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2403119045 May 14 01:35:44 PM PDT 24 May 14 01:36:15 PM PDT 24 7718759270 ps
T986 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2011343591 May 14 01:35:41 PM PDT 24 May 14 01:35:45 PM PDT 24 86674089 ps
T987 /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.123097665 May 14 01:35:44 PM PDT 24 May 14 01:36:13 PM PDT 24 18030115509 ps
T130 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.4044241185 May 14 01:35:49 PM PDT 24 May 14 01:35:54 PM PDT 24 86261937 ps
T96 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1218158944 May 14 01:35:44 PM PDT 24 May 14 01:35:48 PM PDT 24 474407126 ps
T988 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2947485015 May 14 01:35:52 PM PDT 24 May 14 01:35:56 PM PDT 24 157955595 ps
T128 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3917795644 May 14 01:35:46 PM PDT 24 May 14 01:35:52 PM PDT 24 196890503 ps
T989 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2138781170 May 14 01:35:56 PM PDT 24 May 14 01:35:59 PM PDT 24 26196634 ps
T990 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3492234703 May 14 01:35:09 PM PDT 24 May 14 01:35:12 PM PDT 24 318846864 ps
T991 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1469886360 May 14 01:35:49 PM PDT 24 May 14 01:35:54 PM PDT 24 19373667 ps
T992 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2790235499 May 14 01:35:41 PM PDT 24 May 14 01:35:44 PM PDT 24 1507696527 ps
T993 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1802769777 May 14 01:35:08 PM PDT 24 May 14 01:35:09 PM PDT 24 15138368 ps
T994 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1528548083 May 14 01:35:45 PM PDT 24 May 14 01:35:49 PM PDT 24 25593668 ps
T123 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2287899439 May 14 01:35:44 PM PDT 24 May 14 01:35:50 PM PDT 24 445421943 ps
T995 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.4113632753 May 14 01:35:44 PM PDT 24 May 14 01:35:48 PM PDT 24 28672608 ps
T996 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3293423665 May 14 01:35:40 PM PDT 24 May 14 01:35:42 PM PDT 24 22804253 ps
T997 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.987159531 May 14 01:35:55 PM PDT 24 May 14 01:36:00 PM PDT 24 110523749 ps
T998 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2637663425 May 14 01:35:44 PM PDT 24 May 14 01:35:50 PM PDT 24 56793861 ps
T999 /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1056543582 May 14 01:35:08 PM PDT 24 May 14 01:36:03 PM PDT 24 7206537280 ps
T1000 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1025927316 May 14 01:35:50 PM PDT 24 May 14 01:35:55 PM PDT 24 18138345 ps
T1001 /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.789756451 May 14 01:35:45 PM PDT 24 May 14 01:35:49 PM PDT 24 83608480 ps
T1002 /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.4009938622 May 14 01:35:08 PM PDT 24 May 14 01:35:10 PM PDT 24 56678739 ps
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