Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16110053	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

155816183

1

T1

153284

T2

1162

T3

57271

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	84608624	1			T1	84000		T2	314		T3	31491
values[0x0]	42062782	1			T1	40708		T2	451		T3	15293
values[0x1]	45254830	1			T1	43848		T2	397		T3	16066

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8192723	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

163733513

1

T1

160996

T2

1162

T3

60022

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	569351	1			T1	744		T2	4		T3	245
valid_sources[0x01]	570227	1			T1	660		T3	257		T7	951
valid_sources[0x02]	567721	1			T1	603		T2	2		T3	276
valid_sources[0x03]	635621	1			T1	686		T2	8		T3	220
valid_sources[0x04]	581950	1			T1	684		T2	1		T3	224
valid_sources[0x05]	850154	1			T1	638		T2	6		T3	218
valid_sources[0x06]	603585	1			T1	713		T2	1		T3	233
valid_sources[0x07]	577668	1			T1	622		T2	6		T3	250
valid_sources[0x08]	579613	1			T1	641		T2	8		T3	235
valid_sources[0x09]	569830	1			T1	657		T2	3		T3	281
valid_sources[0x0a]	618801	1			T1	656		T2	4		T3	269
valid_sources[0x0b]	616075	1			T1	757		T2	4		T3	230
valid_sources[0x0c]	592907	1			T1	666		T2	1		T3	258
valid_sources[0x0d]	569787	1			T1	647		T2	3		T3	271
valid_sources[0x0e]	603744	1			T1	665		T2	4		T3	229
valid_sources[0x0f]	587015	1			T1	690		T2	4		T3	228
valid_sources[0x10]	590589	1			T1	727		T2	10		T3	229
valid_sources[0x11]	580529	1			T1	685		T2	3		T3	255
valid_sources[0x12]	590383	1			T1	685		T2	3		T3	266
valid_sources[0x13]	615743	1			T1	706		T2	5		T3	278
valid_sources[0x14]	687605	1			T1	594		T2	4		T3	227
valid_sources[0x15]	576762	1			T1	611		T2	5		T3	225
valid_sources[0x16]	2215760	1			T1	646		T2	2		T3	238
valid_sources[0x17]	613216	1			T1	584		T2	2		T3	237
valid_sources[0x18]	613507	1			T1	685		T2	4		T3	250
valid_sources[0x19]	595701	1			T1	674		T2	4		T3	207
valid_sources[0x1a]	594801	1			T1	653		T2	4		T3	294
valid_sources[0x1b]	581983	1			T1	617		T2	6		T3	235
valid_sources[0x1c]	612013	1			T1	750		T2	7		T3	206
valid_sources[0x1d]	598332	1			T1	653		T2	2		T3	257
valid_sources[0x1e]	610014	1			T1	640		T2	3		T3	247
valid_sources[0x1f]	603127	1			T1	633		T2	1		T3	269
valid_sources[0x20]	580388	1			T1	599		T2	9		T3	223
valid_sources[0x21]	589855	1			T1	630		T2	6		T3	228
valid_sources[0x22]	606496	1			T1	667		T2	2		T3	262
valid_sources[0x23]	607599	1			T1	662		T2	3		T3	250
valid_sources[0x24]	631003	1			T1	620		T2	3		T3	278
valid_sources[0x25]	584960	1			T1	631		T3	247		T7	900
valid_sources[0x26]	640081	1			T1	696		T2	9		T3	267
valid_sources[0x27]	578157	1			T1	719		T2	2		T3	234
valid_sources[0x28]	1800776	1			T1	595		T2	3		T3	284
valid_sources[0x29]	605588	1			T1	613		T2	5		T3	241
valid_sources[0x2a]	634455	1			T1	622		T2	1		T3	229
valid_sources[0x2b]	579144	1			T1	623		T3	257		T7	900
valid_sources[0x2c]	579248	1			T1	630		T2	1		T3	240
valid_sources[0x2d]	608989	1			T1	679		T2	3		T3	258
valid_sources[0x2e]	570658	1			T1	617		T2	4		T3	233
valid_sources[0x2f]	579480	1			T1	668		T2	3		T3	243
valid_sources[0x30]	700406	1			T1	680		T2	9		T3	239
valid_sources[0x31]	607969	1			T1	644		T2	9		T3	283
valid_sources[0x32]	586666	1			T1	677		T2	3		T3	264
valid_sources[0x33]	630608	1			T1	649		T2	6		T3	297
valid_sources[0x34]	573526	1			T1	717		T2	8		T3	244
valid_sources[0x35]	623180	1			T1	667		T2	6		T3	248
valid_sources[0x36]	594667	1			T1	663		T3	223		T7	922
valid_sources[0x37]	637008	1			T1	711		T2	9		T3	254
valid_sources[0x38]	567447	1			T1	666		T2	9		T3	271
valid_sources[0x39]	572214	1			T1	631		T2	5		T3	282
valid_sources[0x3a]	631164	1			T1	634		T2	8		T3	219
valid_sources[0x3b]	641084	1			T1	594		T2	3		T3	268
valid_sources[0x3c]	622493	1			T1	548		T2	2		T3	262
valid_sources[0x3d]	654920	1			T1	603		T2	5		T3	273
valid_sources[0x3e]	610673	1			T1	658		T2	5		T3	233
valid_sources[0x3f]	603213	1			T1	654		T2	9		T3	265
valid_sources[0x40]	583491	1			T1	639		T2	3		T3	228
valid_sources[0x41]	609496	1			T1	662		T2	5		T3	250
valid_sources[0x42]	1411283	1			T1	648		T2	4		T3	269
valid_sources[0x43]	626471	1			T1	613		T2	10		T3	237
valid_sources[0x44]	610447	1			T1	703		T2	3		T3	253
valid_sources[0x45]	635468	1			T1	593		T2	3		T3	233
valid_sources[0x46]	629127	1			T1	679		T2	5		T3	210
valid_sources[0x47]	598259	1			T1	659		T2	8		T3	279
valid_sources[0x48]	588876	1			T1	697		T2	7		T3	200
valid_sources[0x49]	619514	1			T1	746		T2	10		T3	258
valid_sources[0x4a]	578993	1			T1	661		T2	5		T3	241
valid_sources[0x4b]	605596	1			T1	637		T2	8		T3	221
valid_sources[0x4c]	1230228	1			T1	611		T2	4		T3	259
valid_sources[0x4d]	782317	1			T1	597		T2	6		T3	229
valid_sources[0x4e]	583442	1			T1	685		T2	5		T3	276
valid_sources[0x4f]	578790	1			T1	687		T2	1		T3	232
valid_sources[0x50]	644259	1			T1	684		T2	4		T3	236
valid_sources[0x51]	572416	1			T1	694		T2	11		T3	224
valid_sources[0x52]	564021	1			T1	638		T2	3		T3	210
valid_sources[0x53]	578704	1			T1	652		T2	4		T3	249
valid_sources[0x54]	591975	1			T1	605		T2	5		T3	222
valid_sources[0x55]	601538	1			T1	643		T2	6		T3	256
valid_sources[0x56]	632732	1			T1	700		T2	1		T3	234
valid_sources[0x57]	607656	1			T1	703		T2	5		T3	263
valid_sources[0x58]	578366	1			T1	612		T2	7		T3	219
valid_sources[0x59]	580062	1			T1	649		T2	8		T3	236
valid_sources[0x5a]	582074	1			T1	703		T2	7		T3	249
valid_sources[0x5b]	576665	1			T1	655		T2	4		T3	219
valid_sources[0x5c]	1368061	1			T1	614		T2	8		T3	241
valid_sources[0x5d]	627451	1			T1	701		T2	5		T3	249
valid_sources[0x5e]	588201	1			T1	613		T2	5		T3	203
valid_sources[0x5f]	760441	1			T1	615		T2	3		T3	279
valid_sources[0x60]	2138189	1			T1	642		T3	250		T7	892
valid_sources[0x61]	574194	1			T1	603		T2	1		T3	266
valid_sources[0x62]	570637	1			T1	698		T2	8		T3	225
valid_sources[0x63]	813985	1			T1	685		T2	2		T3	217
valid_sources[0x64]	689647	1			T1	695		T2	4		T3	241
valid_sources[0x65]	614194	1			T1	693		T2	6		T3	232
valid_sources[0x66]	1307209	1			T1	683		T2	5		T3	214
valid_sources[0x67]	581657	1			T1	638		T2	11		T3	277
valid_sources[0x68]	588401	1			T1	699		T2	5		T3	251
valid_sources[0x69]	589367	1			T1	627		T2	3		T3	207
valid_sources[0x6a]	586204	1			T1	589		T2	6		T3	223
valid_sources[0x6b]	729204	1			T1	625		T2	6		T3	221
valid_sources[0x6c]	615056	1			T1	689		T2	4		T3	206
valid_sources[0x6d]	616828	1			T1	723		T2	10		T3	246
valid_sources[0x6e]	589502	1			T1	679		T2	2		T3	260
valid_sources[0x6f]	584471	1			T1	630		T2	4		T3	265
valid_sources[0x70]	607307	1			T1	681		T2	2		T3	251
valid_sources[0x71]	601974	1			T1	577		T2	15		T3	242
valid_sources[0x72]	614408	1			T1	634		T2	7		T3	233
valid_sources[0x73]	584437	1			T1	702		T2	11		T3	227
valid_sources[0x74]	628821	1			T1	688		T2	3		T3	246
valid_sources[0x75]	627663	1			T1	705		T2	7		T3	273
valid_sources[0x76]	580951	1			T1	647		T2	4		T3	270
valid_sources[0x77]	588280	1			T1	641		T2	3		T3	216
valid_sources[0x78]	598173	1			T1	667		T2	7		T3	276
valid_sources[0x79]	656517	1			T1	649		T2	3		T3	252
valid_sources[0x7a]	663958	1			T1	606		T2	6		T3	282
valid_sources[0x7b]	585952	1			T1	692		T2	1		T3	268
valid_sources[0x7c]	606700	1			T1	676		T2	2		T3	257
valid_sources[0x7d]	572613	1			T1	572		T2	7		T3	226
valid_sources[0x7e]	656994	1			T1	663		T2	3		T3	264
valid_sources[0x7f]	571228	1			T1	643		T2	4		T3	270
valid_sources[0x80]	1639647	1			T1	703		T2	2		T3	240

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

76510738

1

T1

76371

T2

314

T3

28736

values[0x0]

all_enables

biggest_size

39659903

1

T1

38411

T2

451

T3

14426

values[0x1]

all_enables

biggest_size

39645542

1

T1

38502

T2

397

T3

14109

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	31774	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

136025

1

T1

2

T2

1248

T3

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	48745	1			T2	358		T4	26		T16	798
values[0x0]	57408	1			T1	4		T2	453		T3	5
values[0x1]	61646	1			T2	491		T3	2		T7	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	23947	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

143852

1

T1

2

T2

1269

T3

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	586	1			T2	11		T16	13		T19	16
valid_sources[0x01]	625	1			T2	7		T16	4		T19	17
valid_sources[0x02]	518	1			T2	9		T16	8		T19	18
valid_sources[0x03]	533	1			T2	12		T16	5		T19	13
valid_sources[0x04]	604	1			T2	6		T57	5		T16	15
valid_sources[0x05]	775	1			T2	3		T9	2		T16	23
valid_sources[0x06]	650	1			T2	4		T19	13		T129	1
valid_sources[0x07]	642	1			T2	7		T16	9		T19	10
valid_sources[0x08]	644	1			T2	8		T16	1		T19	8
valid_sources[0x09]	748	1			T2	11		T16	1		T19	16
valid_sources[0x0a]	689	1			T2	3		T19	8		T55	3
valid_sources[0x0b]	692	1			T2	2		T16	3		T19	19
valid_sources[0x0c]	630	1			T2	4		T16	5		T19	10
valid_sources[0x0d]	869	1			T2	4		T16	49		T19	14
valid_sources[0x0e]	477	1			T2	3		T16	6		T19	16
valid_sources[0x0f]	499	1			T2	8		T13	1		T19	18
valid_sources[0x10]	675	1			T2	5		T16	14		T19	12
valid_sources[0x11]	981	1			T2	10		T18	5		T16	12
valid_sources[0x12]	993	1			T2	9		T16	30		T19	9
valid_sources[0x13]	715	1			T2	6		T16	26		T19	23
valid_sources[0x14]	509	1			T2	3		T19	5		T130	1
valid_sources[0x15]	708	1			T2	5		T19	12		T40	1
valid_sources[0x16]	982	1			T2	3		T16	29		T19	12
valid_sources[0x17]	729	1			T2	5		T16	20		T19	16
valid_sources[0x18]	652	1			T2	6		T16	1		T19	25
valid_sources[0x19]	858	1			T2	4		T16	22		T19	23
valid_sources[0x1a]	601	1			T2	4		T16	20		T19	11
valid_sources[0x1b]	734	1			T2	6		T7	3		T19	16
valid_sources[0x1c]	492	1			T2	3		T16	6		T19	19
valid_sources[0x1d]	654	1			T2	7		T16	13		T19	11
valid_sources[0x1e]	519	1			T2	1		T16	4		T19	7
valid_sources[0x1f]	620	1			T2	5		T16	7		T19	18
valid_sources[0x20]	640	1			T2	2		T16	11		T19	21
valid_sources[0x21]	795	1			T2	3		T16	4		T19	18
valid_sources[0x22]	551	1			T2	7		T16	28		T19	9
valid_sources[0x23]	621	1			T2	6		T16	29		T19	9
valid_sources[0x24]	836	1			T2	4		T16	8		T19	7
valid_sources[0x25]	827	1			T2	2		T16	67		T19	9
valid_sources[0x26]	552	1			T2	10		T16	15		T19	20
valid_sources[0x27]	459	1			T2	7		T16	2		T19	25
valid_sources[0x28]	686	1			T2	9		T16	21		T19	15
valid_sources[0x29]	737	1			T2	7		T16	25		T19	8
valid_sources[0x2a]	477	1			T2	6		T16	2		T19	18
valid_sources[0x2b]	618	1			T2	1		T16	11		T19	11
valid_sources[0x2c]	455	1			T2	4		T16	29		T19	5
valid_sources[0x2d]	554	1			T2	7		T16	4		T19	16
valid_sources[0x2e]	508	1			T2	6		T16	6		T19	14
valid_sources[0x2f]	561	1			T2	5		T16	7		T19	20
valid_sources[0x30]	901	1			T2	4		T16	9		T19	16
valid_sources[0x31]	508	1			T1	1		T2	6		T16	1
valid_sources[0x32]	467	1			T2	5		T16	14		T19	11
valid_sources[0x33]	831	1			T2	3		T16	16		T19	6
valid_sources[0x34]	806	1			T2	3		T16	5		T19	14
valid_sources[0x35]	566	1			T2	2		T16	21		T19	12
valid_sources[0x36]	632	1			T2	2		T15	1		T16	8
valid_sources[0x37]	581	1			T2	6		T16	6		T19	15
valid_sources[0x38]	525	1			T2	7		T19	18		T130	1
valid_sources[0x39]	559	1			T2	4		T16	1		T19	17
valid_sources[0x3a]	578	1			T2	5		T16	19		T19	20
valid_sources[0x3b]	786	1			T2	6		T16	20		T19	19
valid_sources[0x3c]	819	1			T2	5		T16	12		T19	10
valid_sources[0x3d]	652	1			T2	16		T16	29		T19	15
valid_sources[0x3e]	664	1			T2	7		T16	17		T19	18
valid_sources[0x3f]	667	1			T2	7		T17	1		T16	9
valid_sources[0x40]	605	1			T2	4		T16	50		T19	11
valid_sources[0x41]	635	1			T2	5		T17	1		T16	24
valid_sources[0x42]	598	1			T2	2		T19	12		T40	106
valid_sources[0x43]	609	1			T2	3		T19	13		T29	1
valid_sources[0x44]	686	1			T2	7		T16	1		T19	9
valid_sources[0x45]	770	1			T2	5		T16	5		T19	21
valid_sources[0x46]	703	1			T2	6		T16	17		T19	15
valid_sources[0x47]	536	1			T2	4		T16	1		T19	18
valid_sources[0x48]	548	1			T2	1		T16	4		T19	9
valid_sources[0x49]	563	1			T2	16		T16	17		T19	14
valid_sources[0x4a]	806	1			T2	6		T16	19		T19	13
valid_sources[0x4b]	526	1			T2	5		T16	2		T19	14
valid_sources[0x4c]	864	1			T2	5		T16	12		T19	13
valid_sources[0x4d]	588	1			T2	2		T16	41		T19	19
valid_sources[0x4e]	522	1			T2	3		T16	40		T19	20
valid_sources[0x4f]	817	1			T2	4		T16	13		T19	15
valid_sources[0x50]	706	1			T1	2		T2	2		T19	11
valid_sources[0x51]	650	1			T2	3		T16	15		T19	21
valid_sources[0x52]	590	1			T2	6		T16	5		T19	14
valid_sources[0x53]	755	1			T2	5		T17	2		T16	4
valid_sources[0x54]	597	1			T2	6		T16	14		T19	15
valid_sources[0x55]	432	1			T2	6		T19	8		T48	7
valid_sources[0x56]	664	1			T2	8		T16	42		T19	10
valid_sources[0x57]	882	1			T2	4		T16	5		T19	24
valid_sources[0x58]	862	1			T2	4		T16	8		T19	18
valid_sources[0x59]	672	1			T2	5		T16	5		T19	16
valid_sources[0x5a]	499	1			T2	4		T16	4		T19	5
valid_sources[0x5b]	568	1			T2	3		T16	26		T19	10
valid_sources[0x5c]	702	1			T2	3		T16	13		T19	15
valid_sources[0x5d]	727	1			T2	3		T16	33		T19	18
valid_sources[0x5e]	664	1			T2	6		T16	17		T19	12
valid_sources[0x5f]	822	1			T2	5		T16	25		T19	15
valid_sources[0x60]	555	1			T2	7		T12	2		T16	32
valid_sources[0x61]	867	1			T2	3		T16	7		T19	5
valid_sources[0x62]	459	1			T2	7		T16	15		T19	25
valid_sources[0x63]	588	1			T2	9		T16	18		T19	15
valid_sources[0x64]	995	1			T2	2		T16	16		T19	20
valid_sources[0x65]	696	1			T2	1		T16	15		T19	5
valid_sources[0x66]	521	1			T2	6		T16	24		T69	1
valid_sources[0x67]	576	1			T2	6		T3	1		T16	18
valid_sources[0x68]	607	1			T2	3		T18	6		T16	23
valid_sources[0x69]	653	1			T2	4		T16	20		T19	11
valid_sources[0x6a]	493	1			T2	5		T16	3		T19	8
valid_sources[0x6b]	531	1			T2	4		T4	52		T16	38
valid_sources[0x6c]	574	1			T2	2		T16	1		T19	17
valid_sources[0x6d]	587	1			T2	5		T16	3		T19	10
valid_sources[0x6e]	496	1			T2	4		T16	4		T19	6
valid_sources[0x6f]	532	1			T2	3		T16	21		T19	12
valid_sources[0x70]	571	1			T2	2		T16	4		T19	19
valid_sources[0x71]	528	1			T2	6		T16	11		T19	22
valid_sources[0x72]	588	1			T2	4		T16	30		T19	15
valid_sources[0x73]	564	1			T2	5		T19	12		T131	1
valid_sources[0x74]	667	1			T2	10		T16	1		T19	13
valid_sources[0x75]	772	1			T2	8		T16	22		T19	5
valid_sources[0x76]	706	1			T2	4		T16	23		T19	12
valid_sources[0x77]	460	1			T2	2		T16	2		T19	5
valid_sources[0x78]	577	1			T2	3		T16	4		T19	13
valid_sources[0x79]	905	1			T2	5		T19	10		T125	1
valid_sources[0x7a]	708	1			T2	9		T16	18		T19	17
valid_sources[0x7b]	832	1			T2	4		T16	1		T19	21
valid_sources[0x7c]	503	1			T2	1		T17	3		T16	38
valid_sources[0x7d]	532	1			T2	2		T19	16		T107	3
valid_sources[0x7e]	656	1			T2	7		T16	1		T19	10
valid_sources[0x7f]	549	1			T2	4		T19	12		T21	40
valid_sources[0x80]	589	1			T2	5		T19	15		T29	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

37414

1

T2

333

T4

16

T16

721

values[0x0]

all_enables

biggest_size

50167

1

T1

2

T2

450

T3

1

values[0x1]

all_enables

biggest_size

48444

1

T2

465

T3

1

T4

4