Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16003801

1

T1

15272

T2

1457

T3

5579

full_word

152921607

1

T1

153284

T2

1327

T3

57271

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	168925118	1			T1	168556		T2	2784		T3	62850
auto[TlIntgErrCmd]	99	1			T96	7		T97	3		T98	1
auto[TlIntgErrData]	86	1			T96	3		T97	4		T98	4
auto[TlIntgErrBoth]	105	1			T96	10		T97	3		T98	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

81553306

1

T1

84000

T2

658

T3

31491

auto[1]

87372102

1

T1

84556

T2

2126

T3

31359

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7853460	1			T1	7629		T2	308		T3	2755
auto[TlIntgErrNone]	partial	auto[1]	8150078	1			T1	7643		T2	1149		T3	2824
auto[TlIntgErrNone]	full_word	auto[0]	73699725	1			T1	76371		T2	350		T3	28736
auto[TlIntgErrNone]	full_word	auto[1]	79221855	1			T1	76913		T2	977		T3	28535
auto[TlIntgErrCmd]	partial	auto[0]	32	1			T96	4		T97	2		T109	2
auto[TlIntgErrCmd]	partial	auto[1]	58	1			T96	2		T98	1		T109	7
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T96	1		T97	1		T116	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T112	1		T113	1		T114	1
auto[TlIntgErrData]	partial	auto[0]	38	1			T96	2		T97	1		T98	3
auto[TlIntgErrData]	partial	auto[1]	40	1			T96	1		T97	2		T98	1
auto[TlIntgErrData]	full_word	auto[0]	1	1			T117	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	7	1			T97	1		T110	2		T117	1
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T96	3		T97	1		T98	4
auto[TlIntgErrBoth]	partial	auto[1]	51	1			T96	4		T97	2		T98	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T96	1		T110	1		T118	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T96	2		T109	1		T110	1