Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	794218	1			T13	52175		T14	334		T6	1
auto[1]	10907760	1			T1	70858		T3	17618		T7	11953
auto[2]	624128	1			T13	44348		T14	117		T6	6
auto[3]	10683775	1			T1	71088		T3	17558		T7	12107

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14368308	1			T1	117442		T3	29037		T7	322
auto[1]	2127732	1			T1	11667		T3	2942		T7	2807
auto[2]	2170462	1			T1	11705		T3	2916		T7	2691
auto[3]	4343379	1			T1	1132		T3	281		T7	18240

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9583865

1

T3

35172

T4

954

T8

6

auto[1]

13426016

1

T1

141946

T3

4

T7

24060

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	375570	1			T14	269		T20	2981		T127	584
auto[0]	auto[0]	auto[1]	38606	1			T13	2		T14	27		T6	1
auto[0]	auto[0]	auto[2]	38822	1			T13	3		T14	33		T20	289
auto[0]	auto[0]	auto[3]	49684	1			T13	5		T14	5		T20	34
auto[0]	auto[1]	auto[0]	3116709	1			T3	14578		T4	404		T9	1814
auto[0]	auto[1]	auto[1]	347439	1			T3	1470		T4	33		T9	371
auto[0]	auto[1]	auto[2]	367144	1			T3	1443		T4	28		T9	408
auto[0]	auto[1]	auto[3]	610238	1			T3	124		T4	3		T8	3
auto[0]	auto[2]	auto[0]	282587	1			T14	90		T6	5		T20	1818
auto[0]	auto[2]	auto[1]	32034	1			T14	11		T6	1		T20	185
auto[0]	auto[2]	auto[2]	26638	1			T14	15		T20	280		T127	48
auto[0]	auto[2]	auto[3]	36500	1			T13	7		T14	1		T20	28
auto[0]	auto[3]	auto[0]	2978692	1			T3	14457		T4	407		T9	1815
auto[0]	auto[3]	auto[1]	347711	1			T3	1472		T4	39		T9	380
auto[0]	auto[3]	auto[2]	374063	1			T3	1471		T4	38		T8	1
auto[0]	auto[3]	auto[3]	561428	1			T3	157		T4	2		T8	2
auto[1]	auto[0]	auto[0]	9547	1			T13	1781		T125	938		T126	658
auto[1]	auto[0]	auto[1]	43126	1			T13	7726		T125	4171		T126	2785
auto[1]	auto[0]	auto[2]	43365	1			T13	7825		T125	4270		T126	2813
auto[1]	auto[0]	auto[3]	195498	1			T13	34833		T125	19518		T126	12791
auto[1]	auto[1]	auto[0]	3800210	1			T1	58597		T3	2		T7	155
auto[1]	auto[1]	auto[1]	654217	1			T1	5811		T7	2040		T8	2190
auto[1]	auto[1]	auto[2]	635301	1			T1	5852		T3	1		T7	738
auto[1]	auto[1]	auto[3]	1376502	1			T1	598		T7	9020		T8	9680
auto[1]	auto[2]	auto[0]	8109	1			T13	1598		T125	827		T47	1
auto[1]	auto[2]	auto[1]	36556	1			T13	7151		T125	3862		T126	1698
auto[1]	auto[2]	auto[2]	36723	1			T13	6442		T125	3577		T126	3043
auto[1]	auto[2]	auto[3]	164981	1			T13	29150		T125	16381		T126	13804
auto[1]	auto[3]	auto[0]	3796884	1			T1	58845		T7	167		T8	183
auto[1]	auto[3]	auto[1]	628043	1			T1	5856		T7	767		T8	826
auto[1]	auto[3]	auto[2]	648406	1			T1	5853		T3	1		T7	1953
auto[1]	auto[3]	auto[3]	1348548	1			T1	534		T7	9220		T8	9635