Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.39	100.00	94.62	100.00		100.00	92.31	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1216386023	132432	0	0
ctrl_regwen_rd_A	1216386023	12349	0	0
exec_rd_A	1216386023	10787	0	0
exec_regwen_rd_A	1216386023	12014	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1216386023	132432	0	0
T2	28682	825	0	0
T3	326446	0	0	0
T4	808987	0	0	0
T7	158612	0	0	0
T8	171648	0	0	0
T9	72922	0	0	0
T10	1048	0	0	0
T11	95524	0	0	0
T12	514503	0	0	0
T15	154119	0	0	0
T16	0	3470	0	0
T19	0	3466	0	0
T40	0	3294	0	0
T48	0	4576	0	0
T49	0	2372	0	0
T50	0	839	0	0
T51	0	924	0	0
T52	0	3534	0	0
T53	0	4158	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1216386023	12349	0	0
T5	297996	0	0	0
T14	272749	0	0	0
T16	130927	732	0	0
T19	92396	0	0	0
T31	34152	0	0	0
T40	0	800	0	0
T50	0	239	0	0
T52	0	395	0	0
T68	60593	0	0	0
T69	54892	0	0	0
T99	0	688	0	0
T100	0	84	0	0
T101	0	367	0	0
T102	0	305	0	0
T103	0	482	0	0
T104	0	726	0	0
T105	82738	0	0	0
T106	76608	0	0	0
T107	142309	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1216386023	10787	0	0
T5	297996	0	0	0
T14	272749	0	0	0
T16	130927	452	0	0
T19	92396	0	0	0
T31	34152	0	0	0
T40	0	636	0	0
T50	0	270	0	0
T52	0	398	0	0
T68	60593	0	0	0
T69	54892	0	0	0
T99	0	610	0	0
T100	0	96	0	0
T101	0	346	0	0
T102	0	255	0	0
T103	0	375	0	0
T104	0	684	0	0
T105	82738	0	0	0
T106	76608	0	0	0
T107	142309	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1216386023	12014	0	0
T5	297996	0	0	0
T14	272749	0	0	0
T16	130927	693	0	0
T19	92396	0	0	0
T31	34152	0	0	0
T40	0	678	0	0
T50	0	255	0	0
T52	0	393	0	0
T68	60593	0	0	0
T69	54892	0	0	0
T99	0	740	0	0
T100	0	64	0	0
T101	0	442	0	0
T102	0	363	0	0
T103	0	474	0	0
T104	0	843	0	0
T105	82738	0	0	0
T106	76608	0	0	0
T107	142309	0	0	0