Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16765429	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

168879689

1

T1

48388

T3

138567

T4

19176

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	91540428	1			T1	132624		T3	76488		T4	10509
values[0x0]	45383995	1			T1	44939		T3	36852		T4	5125
values[0x1]	48720695	1			T1	87848		T3	39076		T4	5482

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8531892	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

177113226

1

T1

157354

T3

145429

T4

20151

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	567953	1			T1	858		T3	643		T4	74
valid_sources[0x01]	696954	1			T1	906		T3	538		T4	78
valid_sources[0x02]	591778	1			T1	1058		T3	498		T4	65
valid_sources[0x03]	571476	1			T1	887		T3	685		T4	99
valid_sources[0x04]	610056	1			T1	993		T3	587		T4	82
valid_sources[0x05]	566812	1			T1	900		T3	624		T4	65
valid_sources[0x06]	587409	1			T1	745		T3	610		T4	87
valid_sources[0x07]	692979	1			T1	1094		T3	669		T4	86
valid_sources[0x08]	634690	1			T1	981		T3	629		T4	77
valid_sources[0x09]	587593	1			T1	1180		T3	585		T4	77
valid_sources[0x0a]	594091	1			T1	1077		T3	642		T4	85
valid_sources[0x0b]	619848	1			T1	1088		T3	580		T4	85
valid_sources[0x0c]	647200	1			T1	1003		T3	593		T4	88
valid_sources[0x0d]	568493	1			T1	1273		T3	654		T4	85
valid_sources[0x0e]	564178	1			T1	1161		T3	611		T4	73
valid_sources[0x0f]	2030851	1			T1	803		T3	641		T4	83
valid_sources[0x10]	611159	1			T1	1088		T3	608		T4	98
valid_sources[0x11]	666303	1			T1	1013		T3	557		T4	93
valid_sources[0x12]	571942	1			T1	1027		T3	590		T4	83
valid_sources[0x13]	620286	1			T1	1223		T3	681		T4	74
valid_sources[0x14]	584673	1			T1	763		T3	594		T4	66
valid_sources[0x15]	565582	1			T1	1007		T3	607		T4	87
valid_sources[0x16]	605156	1			T1	995		T3	547		T4	78
valid_sources[0x17]	610412	1			T1	851		T3	666		T4	72
valid_sources[0x18]	629841	1			T1	765		T3	565		T4	87
valid_sources[0x19]	637728	1			T1	1091		T3	537		T4	74
valid_sources[0x1a]	695575	1			T1	978		T3	507		T4	93
valid_sources[0x1b]	584184	1			T1	1008		T3	615		T4	89
valid_sources[0x1c]	630331	1			T1	1088		T3	661		T4	73
valid_sources[0x1d]	585786	1			T1	890		T3	624		T4	66
valid_sources[0x1e]	624784	1			T1	1192		T3	648		T4	82
valid_sources[0x1f]	584296	1			T1	879		T3	603		T4	85
valid_sources[0x20]	653458	1			T1	698		T3	600		T4	74
valid_sources[0x21]	590850	1			T1	1191		T3	599		T4	88
valid_sources[0x22]	651230	1			T1	930		T3	551		T4	96
valid_sources[0x23]	598033	1			T1	716		T3	589		T4	84
valid_sources[0x24]	637838	1			T1	807		T3	643		T4	96
valid_sources[0x25]	2091307	1			T1	1002		T3	637		T4	76
valid_sources[0x26]	624256	1			T1	1315		T3	687		T4	87
valid_sources[0x27]	594691	1			T1	1039		T3	559		T4	88
valid_sources[0x28]	590685	1			T1	883		T3	553		T4	88
valid_sources[0x29]	594493	1			T1	922		T3	499		T4	97
valid_sources[0x2a]	584295	1			T1	1222		T3	641		T4	98
valid_sources[0x2b]	582120	1			T1	940		T3	607		T4	91
valid_sources[0x2c]	586343	1			T1	841		T3	600		T4	88
valid_sources[0x2d]	626637	1			T1	982		T3	578		T4	84
valid_sources[0x2e]	677203	1			T1	914		T3	613		T4	71
valid_sources[0x2f]	586027	1			T1	1389		T3	520		T4	69
valid_sources[0x30]	571417	1			T1	927		T3	635		T4	93
valid_sources[0x31]	584331	1			T1	1004		T3	532		T4	65
valid_sources[0x32]	600817	1			T1	1011		T3	581		T4	78
valid_sources[0x33]	573578	1			T1	928		T3	597		T4	92
valid_sources[0x34]	569964	1			T1	1046		T3	526		T4	84
valid_sources[0x35]	1870858	1			T1	1233		T3	584		T4	81
valid_sources[0x36]	587872	1			T1	1054		T3	588		T4	82
valid_sources[0x37]	670615	1			T1	1073		T3	596		T4	79
valid_sources[0x38]	567630	1			T1	945		T3	635		T4	73
valid_sources[0x39]	598631	1			T1	969		T3	576		T4	72
valid_sources[0x3a]	581088	1			T1	1063		T3	535		T4	81
valid_sources[0x3b]	616455	1			T1	897		T3	623		T4	82
valid_sources[0x3c]	1747624	1			T1	1083		T3	651		T4	92
valid_sources[0x3d]	581059	1			T1	1138		T3	610		T4	78
valid_sources[0x3e]	664390	1			T1	1062		T3	583		T4	89
valid_sources[0x3f]	579940	1			T1	1060		T3	685		T4	96
valid_sources[0x40]	595009	1			T1	1051		T3	632		T4	75
valid_sources[0x41]	600619	1			T1	968		T3	568		T4	64
valid_sources[0x42]	620475	1			T1	927		T3	549		T4	85
valid_sources[0x43]	578486	1			T1	1162		T3	549		T4	79
valid_sources[0x44]	600865	1			T1	854		T3	537		T4	77
valid_sources[0x45]	643789	1			T1	856		T3	659		T4	70
valid_sources[0x46]	609523	1			T1	821		T3	524		T4	84
valid_sources[0x47]	632775	1			T1	1287		T3	554		T4	82
valid_sources[0x48]	602864	1			T1	1051		T3	646		T4	63
valid_sources[0x49]	594899	1			T1	1028		T3	587		T4	76
valid_sources[0x4a]	583883	1			T1	1229		T3	584		T4	70
valid_sources[0x4b]	601284	1			T1	1199		T3	562		T4	100
valid_sources[0x4c]	586802	1			T1	964		T3	699		T4	71
valid_sources[0x4d]	595968	1			T1	1012		T3	557		T4	85
valid_sources[0x4e]	596327	1			T1	893		T3	576		T4	64
valid_sources[0x4f]	660056	1			T1	1065		T3	627		T4	93
valid_sources[0x50]	613768	1			T1	1058		T3	645		T4	110
valid_sources[0x51]	558563	1			T1	899		T3	571		T4	89
valid_sources[0x52]	587700	1			T1	958		T3	625		T4	67
valid_sources[0x53]	643025	1			T1	1286		T3	649		T4	78
valid_sources[0x54]	606303	1			T1	1112		T3	520		T4	86
valid_sources[0x55]	601646	1			T1	928		T3	573		T4	76
valid_sources[0x56]	1671349	1			T1	1096		T3	645		T4	75
valid_sources[0x57]	564204	1			T1	1338		T3	570		T4	75
valid_sources[0x58]	597208	1			T1	954		T3	623		T4	85
valid_sources[0x59]	577268	1			T1	1099		T3	591		T4	92
valid_sources[0x5a]	575043	1			T1	1279		T3	522		T4	82
valid_sources[0x5b]	646984	1			T1	1055		T3	559		T4	93
valid_sources[0x5c]	609920	1			T1	1113		T3	590		T4	80
valid_sources[0x5d]	720100	1			T1	1054		T3	571		T4	96
valid_sources[0x5e]	628482	1			T1	1119		T3	599		T4	76
valid_sources[0x5f]	572938	1			T1	1028		T3	546		T4	69
valid_sources[0x60]	619169	1			T1	897		T3	574		T4	92
valid_sources[0x61]	580054	1			T1	1188		T3	707		T4	85
valid_sources[0x62]	607572	1			T1	906		T3	722		T4	72
valid_sources[0x63]	625107	1			T1	786		T3	558		T4	75
valid_sources[0x64]	588214	1			T1	1312		T3	570		T4	72
valid_sources[0x65]	568476	1			T1	1085		T3	544		T4	68
valid_sources[0x66]	616498	1			T1	871		T3	532		T4	83
valid_sources[0x67]	818395	1			T1	1140		T3	529		T4	76
valid_sources[0x68]	589116	1			T1	1238		T3	585		T4	77
valid_sources[0x69]	619896	1			T1	1118		T3	506		T4	63
valid_sources[0x6a]	593426	1			T1	953		T3	628		T4	93
valid_sources[0x6b]	579788	1			T1	1328		T3	536		T4	64
valid_sources[0x6c]	632810	1			T1	1014		T3	637		T4	77
valid_sources[0x6d]	601183	1			T1	1050		T3	609		T4	76
valid_sources[0x6e]	567251	1			T1	1034		T3	616		T4	93
valid_sources[0x6f]	570152	1			T1	1458		T3	547		T4	90
valid_sources[0x70]	575609	1			T1	1298		T3	471		T4	88
valid_sources[0x71]	566443	1			T1	1037		T3	629		T4	89
valid_sources[0x72]	1181969	1			T1	1356		T3	520		T4	80
valid_sources[0x73]	3197120	1			T1	900		T3	535		T4	78
valid_sources[0x74]	630349	1			T1	922		T3	605		T4	91
valid_sources[0x75]	2012685	1			T1	1051		T3	578		T4	86
valid_sources[0x76]	615395	1			T1	908		T3	675		T4	77
valid_sources[0x77]	568442	1			T1	1051		T3	587		T4	87
valid_sources[0x78]	627342	1			T1	975		T3	517		T4	88
valid_sources[0x79]	586658	1			T1	913		T3	534		T4	70
valid_sources[0x7a]	591872	1			T1	1038		T3	585		T4	70
valid_sources[0x7b]	619326	1			T1	927		T3	568		T4	89
valid_sources[0x7c]	589965	1			T1	988		T3	625		T4	71
valid_sources[0x7d]	579266	1			T1	789		T3	620		T4	100
valid_sources[0x7e]	2762403	1			T1	867		T3	533		T4	82
valid_sources[0x7f]	812605	1			T1	865		T3	603		T4	96
valid_sources[0x80]	565306	1			T1	1154		T3	540		T4	95

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

83110488

1

T1

24227

T3

69528

T4

9535

values[0x0]

all_enables

biggest_size

42882543

1

T1

12097

T3

34720

T4

4830

values[0x1]

all_enables

biggest_size

42886658

1

T1

12064

T3

34319

T4

4811

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	33967	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

144769

1

T3

5

T5

10

T11

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	52282	1			T5	10		T18	12		T20	1126
values[0x0]	61230	1			T1	3		T2	1		T3	11
values[0x1]	65224	1			T1	1		T3	17		T4	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	25817	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

152919

1

T1

1

T3

9

T4

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	699	1			T31	9		T32	61		T60	3
valid_sources[0x01]	931	1			T73	1		T31	4		T32	242
valid_sources[0x02]	892	1			T42	27		T74	1		T31	31
valid_sources[0x03]	518	1			T3	1		T31	9		T49	3
valid_sources[0x04]	1246	1			T20	206		T31	1		T32	125
valid_sources[0x05]	658	1			T9	2		T6	2		T31	3
valid_sources[0x06]	578	1			T6	1		T31	13		T60	7
valid_sources[0x07]	691	1			T6	1		T31	1		T109	1
valid_sources[0x08]	746	1			T123	1		T32	78		T49	2
valid_sources[0x09]	669	1			T12	1		T7	2		T31	17
valid_sources[0x0a]	559	1			T6	1		T31	10		T32	2
valid_sources[0x0b]	644	1			T31	40		T123	4		T51	14
valid_sources[0x0c]	515	1			T6	1		T31	11		T44	1
valid_sources[0x0d]	811	1			T20	68		T6	1		T31	2
valid_sources[0x0e]	511	1			T31	15		T29	1		T110	1
valid_sources[0x0f]	889	1			T3	1		T31	23		T29	1
valid_sources[0x10]	549	1			T20	88		T6	3		T31	1
valid_sources[0x11]	659	1			T3	2		T31	12		T29	1
valid_sources[0x12]	691	1			T31	5		T60	1		T49	4
valid_sources[0x13]	507	1			T5	10		T29	1		T123	2
valid_sources[0x14]	877	1			T20	3		T7	1		T31	7
valid_sources[0x15]	657	1			T44	1		T49	7		T50	13
valid_sources[0x16]	553	1			T31	15		T32	1		T49	1
valid_sources[0x17]	623	1			T8	1		T31	6		T123	1
valid_sources[0x18]	680	1			T6	3		T39	2		T31	29
valid_sources[0x19]	758	1			T3	2		T20	165		T31	10
valid_sources[0x1a]	1287	1			T20	136		T56	1		T31	2
valid_sources[0x1b]	435	1			T5	1		T31	7		T49	4
valid_sources[0x1c]	709	1			T3	1		T12	1		T7	1
valid_sources[0x1d]	723	1			T31	3		T32	4		T49	2
valid_sources[0x1e]	1271	1			T5	3		T6	1		T31	2
valid_sources[0x1f]	536	1			T31	33		T32	1		T49	4
valid_sources[0x20]	557	1			T31	6		T29	1		T32	3
valid_sources[0x21]	1172	1			T20	88		T6	1		T31	16
valid_sources[0x22]	477	1			T4	1		T6	1		T31	28
valid_sources[0x23]	848	1			T6	3		T31	8		T109	1
valid_sources[0x24]	601	1			T6	1		T134	1		T31	5
valid_sources[0x25]	507	1			T6	1		T134	1		T31	10
valid_sources[0x26]	619	1			T14	1		T8	1		T31	34
valid_sources[0x27]	507	1			T12	1		T31	21		T60	3
valid_sources[0x28]	742	1			T8	4		T31	10		T32	20
valid_sources[0x29]	469	1			T6	1		T31	52		T109	1
valid_sources[0x2a]	589	1			T31	12		T49	3		T135	1
valid_sources[0x2b]	509	1			T14	1		T31	18		T49	2
valid_sources[0x2c]	837	1			T12	1		T6	4		T39	1
valid_sources[0x2d]	1050	1			T31	32		T32	1		T49	3
valid_sources[0x2e]	627	1			T20	1		T8	1		T31	38
valid_sources[0x2f]	780	1			T23	1		T73	3		T8	1
valid_sources[0x30]	495	1			T7	1		T134	2		T31	24
valid_sources[0x31]	475	1			T31	10		T136	1		T49	3
valid_sources[0x32]	648	1			T3	1		T31	22		T84	1
valid_sources[0x33]	562	1			T20	1		T31	23		T136	1
valid_sources[0x34]	559	1			T6	1		T7	1		T31	1
valid_sources[0x35]	818	1			T31	3		T32	56		T44	1
valid_sources[0x36]	507	1			T8	1		T6	1		T7	4
valid_sources[0x37]	986	1			T20	324		T6	3		T31	13
valid_sources[0x38]	713	1			T31	11		T32	3		T133	1
valid_sources[0x39]	633	1			T31	1		T29	1		T127	40
valid_sources[0x3a]	595	1			T3	1		T40	1		T31	13
valid_sources[0x3b]	662	1			T10	1		T7	1		T31	30
valid_sources[0x3c]	820	1			T6	4		T31	4		T32	1
valid_sources[0x3d]	710	1			T6	2		T7	1		T31	46
valid_sources[0x3e]	1111	1			T31	28		T136	1		T137	1
valid_sources[0x3f]	552	1			T24	3		T31	8		T49	3
valid_sources[0x40]	482	1			T31	12		T32	1		T49	6
valid_sources[0x41]	594	1			T6	1		T134	1		T31	17
valid_sources[0x42]	504	1			T8	1		T39	1		T7	3
valid_sources[0x43]	598	1			T31	10		T60	2		T49	4
valid_sources[0x44]	937	1			T7	2		T134	1		T31	10
valid_sources[0x45]	870	1			T24	3		T80	1		T31	15
valid_sources[0x46]	927	1			T6	1		T31	15		T49	14
valid_sources[0x47]	469	1			T20	41		T31	7		T29	1
valid_sources[0x48]	598	1			T12	1		T6	1		T31	3
valid_sources[0x49]	795	1			T20	3		T6	1		T31	17
valid_sources[0x4a]	601	1			T20	2		T6	1		T31	12
valid_sources[0x4b]	815	1			T8	1		T31	15		T136	2
valid_sources[0x4c]	442	1			T8	2		T24	3		T109	1
valid_sources[0x4d]	551	1			T31	5		T49	6		T51	7
valid_sources[0x4e]	551	1			T3	1		T8	1		T7	2
valid_sources[0x4f]	574	1			T3	1		T31	16		T109	1
valid_sources[0x50]	425	1			T134	1		T31	4		T49	12
valid_sources[0x51]	541	1			T6	2		T31	16		T109	1
valid_sources[0x52]	715	1			T6	1		T134	2		T31	23
valid_sources[0x53]	1213	1			T6	2		T31	9		T136	1
valid_sources[0x54]	613	1			T12	1		T8	1		T31	19
valid_sources[0x55]	737	1			T6	1		T40	1		T31	18
valid_sources[0x56]	592	1			T20	4		T6	1		T134	1
valid_sources[0x57]	490	1			T3	1		T31	21		T109	1
valid_sources[0x58]	1228	1			T3	1		T10	1		T6	2
valid_sources[0x59]	836	1			T8	2		T7	3		T31	10
valid_sources[0x5a]	640	1			T31	9		T32	1		T138	1
valid_sources[0x5b]	906	1			T3	1		T31	18		T81	1
valid_sources[0x5c]	1157	1			T3	1		T20	681		T6	2
valid_sources[0x5d]	597	1			T6	1		T31	5		T29	1
valid_sources[0x5e]	675	1			T6	1		T31	10		T32	2
valid_sources[0x5f]	545	1			T31	13		T136	1		T139	1
valid_sources[0x60]	569	1			T38	1		T6	1		T40	1
valid_sources[0x61]	410	1			T3	1		T134	1		T31	6
valid_sources[0x62]	676	1			T11	14		T15	1		T31	3
valid_sources[0x63]	827	1			T20	5		T6	2		T31	17
valid_sources[0x64]	1292	1			T24	1		T31	9		T49	4
valid_sources[0x65]	645	1			T20	4		T6	1		T7	3
valid_sources[0x66]	394	1			T6	1		T31	28		T44	1
valid_sources[0x67]	679	1			T31	14		T44	1		T49	2
valid_sources[0x68]	583	1			T3	1		T20	30		T31	11
valid_sources[0x69]	588	1			T19	1		T40	1		T31	25
valid_sources[0x6a]	514	1			T12	1		T6	3		T31	10
valid_sources[0x6b]	606	1			T3	1		T4	1		T31	8
valid_sources[0x6c]	586	1			T31	13		T49	6		T51	17
valid_sources[0x6d]	855	1			T12	1		T31	1		T60	8
valid_sources[0x6e]	711	1			T31	8		T25	6		T49	9
valid_sources[0x6f]	460	1			T31	11		T140	3		T51	11
valid_sources[0x70]	1010	1			T8	1		T31	10		T32	135
valid_sources[0x71]	469	1			T8	1		T94	2		T31	34
valid_sources[0x72]	685	1			T10	1		T6	1		T39	1
valid_sources[0x73]	789	1			T20	55		T31	1		T32	1
valid_sources[0x74]	700	1			T58	26		T31	13		T49	10
valid_sources[0x75]	781	1			T20	176		T41	1		T31	28
valid_sources[0x76]	797	1			T8	1		T7	2		T31	10
valid_sources[0x77]	792	1			T6	1		T31	27		T29	1
valid_sources[0x78]	1020	1			T4	1		T40	1		T31	18
valid_sources[0x79]	828	1			T10	1		T31	8		T49	3
valid_sources[0x7a]	693	1			T40	1		T31	23		T135	1
valid_sources[0x7b]	785	1			T20	252		T31	14		T60	4
valid_sources[0x7c]	612	1			T10	1		T12	2		T6	1
valid_sources[0x7d]	786	1			T20	60		T31	12		T49	3
valid_sources[0x7e]	521	1			T12	1		T20	1		T6	1
valid_sources[0x7f]	613	1			T20	3		T31	12		T136	1
valid_sources[0x80]	1075	1			T31	25		T49	5		T135	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

39739

1

T5

6

T18

7

T20

1046

values[0x0]

all_enables

biggest_size

53381

1

T3

3

T5

3

T12

9

values[0x1]

all_enables

biggest_size

51649

1

T3

2

T5

1

T11

2