Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16655574

1

T1

217023

T3

12291

T4

1567

full_word

165928253

1

T1

48388

T3

123045

T4

15390

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	182583527	1			T1	265411		T3	135336		T4	16957
auto[TlIntgErrCmd]	101	1			T99	7		T100	8		T101	3
auto[TlIntgErrData]	97	1			T99	8		T100	6		T101	4
auto[TlIntgErrBoth]	102	1			T99	5		T100	6		T101	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

88421372

1

T1

132624

T3

59408

T4

6350

auto[1]

94162455

1

T1

132787

T3

75928

T4

10607

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	8180328	1			T1	108397		T3	5402		T4	601
auto[TlIntgErrNone]	partial	auto[1]	8474966	1			T1	108626		T3	6889		T4	966
auto[TlIntgErrNone]	full_word	auto[0]	80240911	1			T1	24227		T3	54006		T4	5749
auto[TlIntgErrNone]	full_word	auto[1]	85687322	1			T1	24161		T3	69039		T4	9641
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T99	3		T100	2		T101	1
auto[TlIntgErrCmd]	partial	auto[1]	57	1			T99	4		T100	5		T101	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T115	1		T117	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T100	1		T101	1		T118	1
auto[TlIntgErrData]	partial	auto[0]	43	1			T99	3		T100	4		T101	1
auto[TlIntgErrData]	partial	auto[1]	48	1			T99	4		T100	2		T101	2
auto[TlIntgErrData]	full_word	auto[0]	3	1			T101	1		T117	1		T120	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T99	1		T116	1		T119	1
auto[TlIntgErrBoth]	partial	auto[0]	46	1			T99	3		T100	2		T101	2
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T99	1		T100	3		T101	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T99	1		T115	1		T121	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T100	1		T115	1		T119	1