Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	791707	1			T5	1396		T14	1123		T15	475
auto[1]	11216521	1			T1	15330		T3	5042		T4	33
auto[2]	615643	1			T5	1329		T14	928		T15	364
auto[3]	10948917	1			T1	15247		T3	3694		T4	52

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13924446	1			T1	371		T3	7270		T4	54
auto[1]	2228966	1			T1	3453		T3	653		T4	15
auto[2]	2268388	1			T1	3516		T3	742		T4	12
auto[3]	5150988	1			T1	23237		T3	71		T4	4

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9373726

1

T1

3

T3

8736

T4

85

auto[1]

14199062

1

T1

30574

T9

1

T10

198477

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	258787	1			T5	1144		T14	35		T15	17
auto[0]	auto[0]	auto[1]	27139	1			T5	118		T14	170		T15	82
auto[0]	auto[0]	auto[2]	26971	1			T5	112		T14	171		T15	72
auto[0]	auto[0]	auto[3]	68339	1			T5	21		T14	747		T15	304
auto[0]	auto[1]	auto[0]	3139847	1			T3	4201		T4	19		T9	3389
auto[0]	auto[1]	auto[1]	334743	1			T3	371		T4	9		T9	694
auto[0]	auto[1]	auto[2]	370132	1			T3	430		T4	3		T9	783
auto[0]	auto[1]	auto[3]	617052	1			T1	1		T3	40		T4	2
auto[0]	auto[2]	auto[0]	180676	1			T5	1109		T14	28		T15	12
auto[0]	auto[2]	auto[1]	23493	1			T5	109		T14	174		T15	61
auto[0]	auto[2]	auto[2]	18380	1			T5	102		T14	133		T15	51
auto[0]	auto[2]	auto[3]	48381	1			T5	9		T14	593		T15	240
auto[0]	auto[3]	auto[0]	2986510	1			T3	3069		T4	35		T9	3315
auto[0]	auto[3]	auto[1]	349359	1			T3	282		T4	6		T9	741
auto[0]	auto[3]	auto[2]	361449	1			T3	312		T4	9		T9	742
auto[0]	auto[3]	auto[3]	562468	1			T1	2		T3	31		T4	2
auto[1]	auto[0]	auto[0]	13654	1			T5	1		T47	1		T128	421
auto[1]	auto[0]	auto[1]	61136	1			T128	2066		T130	2723		T131	2453
auto[1]	auto[0]	auto[2]	61120	1			T128	2084		T130	2586		T131	2530
auto[1]	auto[0]	auto[3]	274561	1			T81	1		T128	9367		T129	2
auto[1]	auto[1]	auto[0]	3667904	1			T1	200		T10	82013		T13	88103
auto[1]	auto[1]	auto[1]	707697	1			T1	2594		T10	8617		T13	8075
auto[1]	auto[1]	auto[2]	681918	1			T1	905		T10	8033		T13	8955
auto[1]	auto[1]	auto[3]	1697228	1			T1	11630		T10	834		T13	805
auto[1]	auto[2]	auto[0]	11528	1			T128	286		T130	506		T132	1
auto[1]	auto[2]	auto[1]	52492	1			T128	1290		T130	2557		T131	1433
auto[1]	auto[2]	auto[2]	50998	1			T128	1920		T130	2300		T131	2658
auto[1]	auto[2]	auto[3]	229695	1			T128	8652		T129	1		T130	10210
auto[1]	auto[3]	auto[0]	3665540	1			T1	171		T10	81577		T13	88655
auto[1]	auto[3]	auto[1]	672907	1			T1	859		T9	1		T10	8342
auto[1]	auto[3]	auto[2]	697420	1			T1	2611		T10	8258		T13	7927
auto[1]	auto[3]	auto[3]	1653264	1			T1	11604		T10	803		T13	830