Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.39	100.00	94.62	100.00		100.00	92.31	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1212492477	136100	0	0
ctrl_regwen_rd_A	1212492477	8272	0	0
exec_rd_A	1212492477	7800	0	0
exec_regwen_rd_A	1212492477	9005	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1212492477	136100	0	0
T6	257644	0	0	0
T8	11226	0	0	0
T14	121956	0	0	0
T20	133009	3617	0	0
T31	0	2825	0	0
T32	0	3994	0	0
T33	34745	0	0	0
T37	85988	0	0	0
T38	95268	0	0	0
T49	0	867	0	0
T50	0	465	0	0
T51	0	2330	0	0
T52	0	3265	0	0
T53	0	3390	0	0
T54	0	5012	0	0
T55	0	1956	0	0
T56	49670	0	0	0
T57	76165	0	0	0
T58	265495	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1212492477	8272	0	0
T25	1597	0	0	0
T29	609927	0	0	0
T31	96666	660	0	0
T46	316302	0	0	0
T49	0	105	0	0
T50	0	160	0	0
T81	242631	0	0	0
T82	95101	0	0	0
T102	0	488	0	0
T103	0	969	0	0
T104	0	749	0	0
T105	0	323	0	0
T106	0	438	0	0
T107	0	103	0	0
T108	0	130	0	0
T109	1514	0	0	0
T110	33695	0	0	0
T111	700	0	0	0
T112	108757	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1212492477	7800	0	0
T25	1597	0	0	0
T29	609927	0	0	0
T31	96666	544	0	0
T46	316302	0	0	0
T49	0	88	0	0
T50	0	214	0	0
T81	242631	0	0	0
T82	95101	0	0	0
T102	0	453	0	0
T103	0	970	0	0
T104	0	574	0	0
T105	0	193	0	0
T106	0	574	0	0
T107	0	107	0	0
T108	0	216	0	0
T109	1514	0	0	0
T110	33695	0	0	0
T111	700	0	0	0
T112	108757	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1212492477	9005	0	0
T25	1597	0	0	0
T29	609927	0	0	0
T31	96666	758	0	0
T46	316302	0	0	0
T49	0	151	0	0
T50	0	212	0	0
T81	242631	0	0	0
T82	95101	0	0	0
T102	0	466	0	0
T103	0	997	0	0
T104	0	836	0	0
T105	0	327	0	0
T106	0	445	0	0
T107	0	131	0	0
T108	0	191	0	0
T109	1514	0	0	0
T110	33695	0	0	0
T111	700	0	0	0
T112	108757	0	0	0