Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.09 99.81 96.99 100.00 100.00 98.60 99.70 98.52


Total test records in report: 1034
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
T788 /workspace/coverage/default/8.sram_ctrl_regwen.1868801723 May 19 12:54:57 PM PDT 24 May 19 01:12:14 PM PDT 24 22606437471 ps
T789 /workspace/coverage/default/0.sram_ctrl_smoke.3105645540 May 19 12:54:15 PM PDT 24 May 19 12:54:32 PM PDT 24 2859628207 ps
T790 /workspace/coverage/default/21.sram_ctrl_max_throughput.3187617145 May 19 12:55:41 PM PDT 24 May 19 12:56:06 PM PDT 24 1558462596 ps
T791 /workspace/coverage/default/38.sram_ctrl_regwen.412965355 May 19 12:56:40 PM PDT 24 May 19 01:20:03 PM PDT 24 80788810802 ps
T792 /workspace/coverage/default/7.sram_ctrl_regwen.2887099296 May 19 12:54:52 PM PDT 24 May 19 01:02:32 PM PDT 24 43373870449 ps
T793 /workspace/coverage/default/5.sram_ctrl_smoke.1076176844 May 19 12:54:43 PM PDT 24 May 19 12:54:51 PM PDT 24 740593450 ps
T794 /workspace/coverage/default/15.sram_ctrl_stress_all.447729914 May 19 12:55:17 PM PDT 24 May 19 02:18:56 PM PDT 24 149189407737 ps
T795 /workspace/coverage/default/49.sram_ctrl_stress_pipeline.1013768844 May 19 12:57:50 PM PDT 24 May 19 01:01:52 PM PDT 24 12066925443 ps
T796 /workspace/coverage/default/26.sram_ctrl_ram_cfg.1346645469 May 19 12:55:46 PM PDT 24 May 19 12:55:50 PM PDT 24 357946784 ps
T797 /workspace/coverage/default/44.sram_ctrl_alert_test.867309278 May 19 12:57:23 PM PDT 24 May 19 12:57:24 PM PDT 24 13495839 ps
T798 /workspace/coverage/default/34.sram_ctrl_lc_escalation.1475680513 May 19 12:56:17 PM PDT 24 May 19 12:57:59 PM PDT 24 31204994590 ps
T799 /workspace/coverage/default/24.sram_ctrl_mem_partial_access.3608084707 May 19 12:55:39 PM PDT 24 May 19 12:56:43 PM PDT 24 1123353404 ps
T800 /workspace/coverage/default/44.sram_ctrl_bijection.867122072 May 19 12:57:17 PM PDT 24 May 19 01:30:27 PM PDT 24 45686569839 ps
T801 /workspace/coverage/default/11.sram_ctrl_ram_cfg.2564027291 May 19 12:55:06 PM PDT 24 May 19 12:55:13 PM PDT 24 725907397 ps
T802 /workspace/coverage/default/23.sram_ctrl_access_during_key_req.4150242236 May 19 12:55:34 PM PDT 24 May 19 01:02:23 PM PDT 24 6043412445 ps
T803 /workspace/coverage/default/32.sram_ctrl_multiple_keys.1818305426 May 19 12:56:00 PM PDT 24 May 19 01:19:21 PM PDT 24 10787202801 ps
T804 /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.2200168891 May 19 12:55:57 PM PDT 24 May 19 12:56:08 PM PDT 24 931489617 ps
T805 /workspace/coverage/default/39.sram_ctrl_multiple_keys.473333675 May 19 12:56:42 PM PDT 24 May 19 01:12:56 PM PDT 24 19249084137 ps
T806 /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.3964166112 May 19 12:54:57 PM PDT 24 May 19 12:55:13 PM PDT 24 2682107727 ps
T807 /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1605412561 May 19 12:57:48 PM PDT 24 May 19 12:58:11 PM PDT 24 466501843 ps
T808 /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.854730069 May 19 12:55:38 PM PDT 24 May 19 01:04:19 PM PDT 24 23616737102 ps
T809 /workspace/coverage/default/18.sram_ctrl_stress_all.4020162793 May 19 12:55:18 PM PDT 24 May 19 01:44:59 PM PDT 24 384498414577 ps
T810 /workspace/coverage/default/46.sram_ctrl_mem_partial_access.2066606642 May 19 12:57:32 PM PDT 24 May 19 12:59:37 PM PDT 24 7098730207 ps
T811 /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.2393665125 May 19 12:57:07 PM PDT 24 May 19 01:03:33 PM PDT 24 15040279720 ps
T812 /workspace/coverage/default/45.sram_ctrl_lc_escalation.708860654 May 19 12:57:26 PM PDT 24 May 19 12:58:42 PM PDT 24 24681462566 ps
T813 /workspace/coverage/default/2.sram_ctrl_mem_walk.141695095 May 19 12:54:27 PM PDT 24 May 19 12:58:30 PM PDT 24 16408932332 ps
T814 /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.300928078 May 19 12:54:22 PM PDT 24 May 19 12:55:10 PM PDT 24 1703237521 ps
T815 /workspace/coverage/default/18.sram_ctrl_regwen.1044621111 May 19 12:55:17 PM PDT 24 May 19 01:02:11 PM PDT 24 6877216505 ps
T816 /workspace/coverage/default/22.sram_ctrl_smoke.3054552204 May 19 12:55:35 PM PDT 24 May 19 12:55:48 PM PDT 24 813415212 ps
T817 /workspace/coverage/default/10.sram_ctrl_stress_all.1897011962 May 19 12:55:02 PM PDT 24 May 19 02:16:39 PM PDT 24 780059765739 ps
T818 /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.3165598234 May 19 12:55:07 PM PDT 24 May 19 12:56:43 PM PDT 24 1372204098 ps
T819 /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.2923735347 May 19 12:54:21 PM PDT 24 May 19 01:00:04 PM PDT 24 15991448189 ps
T820 /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.3561862842 May 19 12:55:25 PM PDT 24 May 19 01:04:36 PM PDT 24 25370225267 ps
T821 /workspace/coverage/default/30.sram_ctrl_lc_escalation.2337720198 May 19 12:55:59 PM PDT 24 May 19 12:57:02 PM PDT 24 81243558193 ps
T822 /workspace/coverage/default/35.sram_ctrl_mem_walk.3208980089 May 19 12:56:25 PM PDT 24 May 19 01:01:35 PM PDT 24 21512821724 ps
T823 /workspace/coverage/default/43.sram_ctrl_stress_pipeline.2593308952 May 19 12:57:14 PM PDT 24 May 19 01:01:20 PM PDT 24 23838712853 ps
T824 /workspace/coverage/default/21.sram_ctrl_partial_access.1138027824 May 19 12:55:25 PM PDT 24 May 19 12:55:46 PM PDT 24 919099130 ps
T825 /workspace/coverage/default/11.sram_ctrl_regwen.866780395 May 19 12:55:01 PM PDT 24 May 19 01:07:15 PM PDT 24 22543150628 ps
T826 /workspace/coverage/default/31.sram_ctrl_smoke.2708512757 May 19 12:55:59 PM PDT 24 May 19 12:56:06 PM PDT 24 1968640538 ps
T827 /workspace/coverage/default/23.sram_ctrl_mem_walk.3916546230 May 19 12:55:41 PM PDT 24 May 19 01:00:30 PM PDT 24 28664303933 ps
T828 /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.3461753403 May 19 12:56:03 PM PDT 24 May 19 01:01:14 PM PDT 24 28279933660 ps
T829 /workspace/coverage/default/38.sram_ctrl_mem_walk.4048882808 May 19 12:56:39 PM PDT 24 May 19 12:58:57 PM PDT 24 7259153055 ps
T830 /workspace/coverage/default/0.sram_ctrl_access_during_key_req.4236502941 May 19 12:54:16 PM PDT 24 May 19 01:03:20 PM PDT 24 79752112989 ps
T831 /workspace/coverage/default/39.sram_ctrl_stress_all.1259010064 May 19 12:56:53 PM PDT 24 May 19 01:27:12 PM PDT 24 158697742293 ps
T832 /workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.1023040903 May 19 12:56:34 PM PDT 24 May 19 12:56:46 PM PDT 24 1509081953 ps
T833 /workspace/coverage/default/12.sram_ctrl_regwen.1255921858 May 19 12:55:04 PM PDT 24 May 19 01:19:27 PM PDT 24 11977815484 ps
T36 /workspace/coverage/default/2.sram_ctrl_sec_cm.105504642 May 19 12:54:24 PM PDT 24 May 19 12:54:29 PM PDT 24 255862516 ps
T834 /workspace/coverage/default/36.sram_ctrl_multiple_keys.2651978061 May 19 12:56:24 PM PDT 24 May 19 01:18:04 PM PDT 24 48965320910 ps
T835 /workspace/coverage/default/11.sram_ctrl_bijection.3274134551 May 19 12:55:08 PM PDT 24 May 19 01:25:32 PM PDT 24 27109387396 ps
T836 /workspace/coverage/default/7.sram_ctrl_max_throughput.942381429 May 19 12:54:50 PM PDT 24 May 19 12:55:00 PM PDT 24 1313533409 ps
T837 /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.3614892999 May 19 12:57:19 PM PDT 24 May 19 12:57:37 PM PDT 24 2359926559 ps
T838 /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.2811192648 May 19 12:57:43 PM PDT 24 May 19 01:00:47 PM PDT 24 12906987228 ps
T839 /workspace/coverage/default/5.sram_ctrl_mem_walk.2315527376 May 19 12:54:40 PM PDT 24 May 19 12:56:44 PM PDT 24 2060004206 ps
T840 /workspace/coverage/default/14.sram_ctrl_executable.4281959104 May 19 12:55:07 PM PDT 24 May 19 01:09:11 PM PDT 24 21550208225 ps
T841 /workspace/coverage/default/13.sram_ctrl_mem_walk.3345901551 May 19 12:55:06 PM PDT 24 May 19 01:00:07 PM PDT 24 20663376555 ps
T842 /workspace/coverage/default/0.sram_ctrl_stress_pipeline.4280938178 May 19 12:54:13 PM PDT 24 May 19 01:00:13 PM PDT 24 5439639953 ps
T843 /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.3028359318 May 19 12:55:10 PM PDT 24 May 19 12:55:40 PM PDT 24 3713577383 ps
T844 /workspace/coverage/default/41.sram_ctrl_alert_test.1646761693 May 19 12:57:03 PM PDT 24 May 19 12:57:04 PM PDT 24 12449371 ps
T845 /workspace/coverage/default/8.sram_ctrl_multiple_keys.165760441 May 19 12:54:46 PM PDT 24 May 19 01:00:52 PM PDT 24 8396246889 ps
T846 /workspace/coverage/default/15.sram_ctrl_alert_test.2606322981 May 19 12:55:09 PM PDT 24 May 19 12:55:14 PM PDT 24 38524942 ps
T847 /workspace/coverage/default/17.sram_ctrl_max_throughput.3660935954 May 19 12:55:15 PM PDT 24 May 19 12:56:40 PM PDT 24 1557722339 ps
T848 /workspace/coverage/default/5.sram_ctrl_stress_all.697073690 May 19 12:54:37 PM PDT 24 May 19 02:07:50 PM PDT 24 76977817624 ps
T849 /workspace/coverage/default/24.sram_ctrl_multiple_keys.3151316982 May 19 12:55:32 PM PDT 24 May 19 01:07:49 PM PDT 24 9727188093 ps
T850 /workspace/coverage/default/1.sram_ctrl_bijection.1245241870 May 19 12:54:18 PM PDT 24 May 19 01:38:08 PM PDT 24 165271609571 ps
T851 /workspace/coverage/default/0.sram_ctrl_stress_all.1416053226 May 19 12:54:13 PM PDT 24 May 19 01:24:37 PM PDT 24 722536575249 ps
T852 /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.885051094 May 19 12:55:12 PM PDT 24 May 19 12:55:24 PM PDT 24 724777446 ps
T853 /workspace/coverage/default/13.sram_ctrl_regwen.930066548 May 19 12:55:10 PM PDT 24 May 19 01:02:35 PM PDT 24 11578691425 ps
T854 /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.2254625492 May 19 12:55:03 PM PDT 24 May 19 12:57:12 PM PDT 24 1589180165 ps
T855 /workspace/coverage/default/12.sram_ctrl_alert_test.3501683697 May 19 12:55:01 PM PDT 24 May 19 12:55:04 PM PDT 24 15963341 ps
T856 /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.1076198061 May 19 12:55:36 PM PDT 24 May 19 12:56:00 PM PDT 24 2243072481 ps
T857 /workspace/coverage/default/28.sram_ctrl_max_throughput.4247687733 May 19 12:55:44 PM PDT 24 May 19 12:58:08 PM PDT 24 3055623176 ps
T858 /workspace/coverage/default/9.sram_ctrl_executable.939781513 May 19 12:54:49 PM PDT 24 May 19 01:04:39 PM PDT 24 28186409952 ps
T859 /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.1346100136 May 19 12:55:13 PM PDT 24 May 19 12:57:05 PM PDT 24 4519201734 ps
T860 /workspace/coverage/default/26.sram_ctrl_mem_walk.1478959203 May 19 12:55:44 PM PDT 24 May 19 12:58:13 PM PDT 24 20661806150 ps
T861 /workspace/coverage/default/5.sram_ctrl_lc_escalation.1206353791 May 19 12:54:40 PM PDT 24 May 19 12:55:55 PM PDT 24 12928930038 ps
T862 /workspace/coverage/default/22.sram_ctrl_ram_cfg.1578771635 May 19 12:55:37 PM PDT 24 May 19 12:55:43 PM PDT 24 365494094 ps
T863 /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.797187196 May 19 12:55:19 PM PDT 24 May 19 12:56:14 PM PDT 24 6552552050 ps
T864 /workspace/coverage/default/35.sram_ctrl_multiple_keys.2398472366 May 19 12:56:17 PM PDT 24 May 19 01:09:17 PM PDT 24 25065028394 ps
T865 /workspace/coverage/default/12.sram_ctrl_partial_access.2931610766 May 19 12:55:06 PM PDT 24 May 19 12:56:11 PM PDT 24 4876063919 ps
T866 /workspace/coverage/default/49.sram_ctrl_lc_escalation.744589639 May 19 12:57:55 PM PDT 24 May 19 12:59:03 PM PDT 24 11465014866 ps
T867 /workspace/coverage/default/33.sram_ctrl_partial_access.3164291369 May 19 12:56:17 PM PDT 24 May 19 12:56:37 PM PDT 24 929349935 ps
T868 /workspace/coverage/default/14.sram_ctrl_regwen.2594019761 May 19 12:55:09 PM PDT 24 May 19 01:25:48 PM PDT 24 59925221654 ps
T869 /workspace/coverage/default/32.sram_ctrl_partial_access.2227240795 May 19 12:56:10 PM PDT 24 May 19 12:56:27 PM PDT 24 3349275651 ps
T870 /workspace/coverage/default/28.sram_ctrl_multiple_keys.1199943933 May 19 12:55:46 PM PDT 24 May 19 01:10:17 PM PDT 24 16023396671 ps
T871 /workspace/coverage/default/4.sram_ctrl_bijection.1771477147 May 19 12:54:37 PM PDT 24 May 19 01:32:46 PM PDT 24 111415762902 ps
T872 /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3955279608 May 19 12:54:45 PM PDT 24 May 19 12:55:03 PM PDT 24 566661805 ps
T873 /workspace/coverage/default/11.sram_ctrl_max_throughput.4282772578 May 19 12:55:03 PM PDT 24 May 19 12:55:26 PM PDT 24 1440259352 ps
T874 /workspace/coverage/default/10.sram_ctrl_ram_cfg.3117015849 May 19 12:55:03 PM PDT 24 May 19 12:55:09 PM PDT 24 1535515287 ps
T875 /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.70705813 May 19 12:54:58 PM PDT 24 May 19 12:55:20 PM PDT 24 5202325326 ps
T876 /workspace/coverage/default/15.sram_ctrl_ram_cfg.1778699568 May 19 12:55:09 PM PDT 24 May 19 12:55:16 PM PDT 24 706252519 ps
T877 /workspace/coverage/default/33.sram_ctrl_stress_pipeline.3284659296 May 19 12:56:12 PM PDT 24 May 19 01:00:08 PM PDT 24 21101847327 ps
T878 /workspace/coverage/default/19.sram_ctrl_multiple_keys.3987270762 May 19 12:55:18 PM PDT 24 May 19 01:04:39 PM PDT 24 38207613188 ps
T879 /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.820272225 May 19 12:55:18 PM PDT 24 May 19 01:00:57 PM PDT 24 29413484464 ps
T880 /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.4235490093 May 19 12:55:12 PM PDT 24 May 19 01:03:48 PM PDT 24 78586847194 ps
T881 /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.2578051986 May 19 12:56:44 PM PDT 24 May 19 12:59:05 PM PDT 24 3262177376 ps
T882 /workspace/coverage/default/35.sram_ctrl_access_during_key_req.385188929 May 19 12:56:24 PM PDT 24 May 19 01:01:47 PM PDT 24 13548031410 ps
T883 /workspace/coverage/default/26.sram_ctrl_max_throughput.434570544 May 19 12:55:41 PM PDT 24 May 19 12:55:50 PM PDT 24 697621559 ps
T884 /workspace/coverage/default/29.sram_ctrl_partial_access.920714217 May 19 12:55:55 PM PDT 24 May 19 12:57:05 PM PDT 24 3769969178 ps
T885 /workspace/coverage/default/29.sram_ctrl_executable.4216803886 May 19 12:55:51 PM PDT 24 May 19 01:15:35 PM PDT 24 48455241006 ps
T886 /workspace/coverage/default/45.sram_ctrl_stress_pipeline.2697591589 May 19 12:57:23 PM PDT 24 May 19 01:02:02 PM PDT 24 26489708613 ps
T887 /workspace/coverage/default/27.sram_ctrl_regwen.602673371 May 19 12:55:40 PM PDT 24 May 19 01:05:53 PM PDT 24 36267726485 ps
T888 /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.3319723642 May 19 12:57:55 PM PDT 24 May 19 12:58:50 PM PDT 24 5686376257 ps
T889 /workspace/coverage/default/41.sram_ctrl_executable.42837629 May 19 12:57:01 PM PDT 24 May 19 01:02:14 PM PDT 24 57830709850 ps
T890 /workspace/coverage/default/47.sram_ctrl_bijection.2904091591 May 19 12:57:39 PM PDT 24 May 19 01:27:43 PM PDT 24 399035693865 ps
T891 /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.430760052 May 19 12:54:54 PM PDT 24 May 19 12:56:58 PM PDT 24 1589025815 ps
T892 /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.885860334 May 19 12:57:37 PM PDT 24 May 19 01:00:07 PM PDT 24 1591371525 ps
T893 /workspace/coverage/default/40.sram_ctrl_partial_access.174817119 May 19 12:56:54 PM PDT 24 May 19 12:57:05 PM PDT 24 3650745775 ps
T894 /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.1256173457 May 19 12:55:23 PM PDT 24 May 19 12:55:31 PM PDT 24 826588992 ps
T895 /workspace/coverage/default/42.sram_ctrl_multiple_keys.2442184401 May 19 12:57:05 PM PDT 24 May 19 01:11:57 PM PDT 24 72045184822 ps
T896 /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.1844939501 May 19 12:54:17 PM PDT 24 May 19 12:55:32 PM PDT 24 1551211164 ps
T897 /workspace/coverage/default/12.sram_ctrl_stress_pipeline.474548738 May 19 12:55:06 PM PDT 24 May 19 01:00:17 PM PDT 24 18843200768 ps
T898 /workspace/coverage/default/17.sram_ctrl_stress_pipeline.2419761850 May 19 12:55:13 PM PDT 24 May 19 12:58:32 PM PDT 24 5140147314 ps
T899 /workspace/coverage/default/6.sram_ctrl_stress_pipeline.3030909880 May 19 12:54:45 PM PDT 24 May 19 12:59:29 PM PDT 24 8942849610 ps
T900 /workspace/coverage/default/44.sram_ctrl_ram_cfg.2602022522 May 19 12:57:17 PM PDT 24 May 19 12:57:21 PM PDT 24 348880437 ps
T901 /workspace/coverage/default/48.sram_ctrl_alert_test.3657741123 May 19 12:57:49 PM PDT 24 May 19 12:57:50 PM PDT 24 21953117 ps
T902 /workspace/coverage/default/41.sram_ctrl_ram_cfg.3685783580 May 19 12:57:01 PM PDT 24 May 19 12:57:06 PM PDT 24 1304096010 ps
T903 /workspace/coverage/default/37.sram_ctrl_bijection.3069215587 May 19 12:56:30 PM PDT 24 May 19 01:35:05 PM PDT 24 422065647080 ps
T904 /workspace/coverage/default/3.sram_ctrl_max_throughput.877356520 May 19 12:54:26 PM PDT 24 May 19 12:54:43 PM PDT 24 724185036 ps
T905 /workspace/coverage/default/29.sram_ctrl_regwen.2044242540 May 19 12:55:49 PM PDT 24 May 19 01:20:20 PM PDT 24 32518782277 ps
T906 /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.2598982875 May 19 12:55:38 PM PDT 24 May 19 12:55:49 PM PDT 24 706509380 ps
T907 /workspace/coverage/default/9.sram_ctrl_partial_access.3322885244 May 19 12:55:04 PM PDT 24 May 19 12:57:14 PM PDT 24 2309946225 ps
T908 /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.1056298475 May 19 12:54:28 PM PDT 24 May 19 12:59:48 PM PDT 24 14399387429 ps
T909 /workspace/coverage/default/8.sram_ctrl_access_during_key_req.3670920063 May 19 12:54:52 PM PDT 24 May 19 01:00:51 PM PDT 24 15805514085 ps
T910 /workspace/coverage/default/20.sram_ctrl_multiple_keys.2087720365 May 19 12:55:17 PM PDT 24 May 19 12:55:43 PM PDT 24 3047669952 ps
T911 /workspace/coverage/default/35.sram_ctrl_executable.935016329 May 19 12:56:22 PM PDT 24 May 19 01:15:29 PM PDT 24 21269685151 ps
T912 /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.724554584 May 19 12:55:16 PM PDT 24 May 19 12:58:53 PM PDT 24 4728684246 ps
T913 /workspace/coverage/default/19.sram_ctrl_bijection.3177937620 May 19 12:55:31 PM PDT 24 May 19 01:22:24 PM PDT 24 77664192110 ps
T914 /workspace/coverage/default/45.sram_ctrl_partial_access.1181273607 May 19 12:57:21 PM PDT 24 May 19 12:57:28 PM PDT 24 390731833 ps
T915 /workspace/coverage/default/29.sram_ctrl_max_throughput.23964588 May 19 12:55:52 PM PDT 24 May 19 12:56:30 PM PDT 24 2882544807 ps
T916 /workspace/coverage/default/16.sram_ctrl_stress_all.1186397777 May 19 12:55:14 PM PDT 24 May 19 02:26:38 PM PDT 24 86842134075 ps
T917 /workspace/coverage/default/7.sram_ctrl_multiple_keys.203652853 May 19 12:54:51 PM PDT 24 May 19 01:02:13 PM PDT 24 8148309327 ps
T918 /workspace/coverage/default/45.sram_ctrl_access_during_key_req.2429307434 May 19 12:57:23 PM PDT 24 May 19 01:01:25 PM PDT 24 4472132781 ps
T919 /workspace/coverage/default/10.sram_ctrl_alert_test.2584383171 May 19 12:54:55 PM PDT 24 May 19 12:54:57 PM PDT 24 20262391 ps
T920 /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.3521014229 May 19 12:56:29 PM PDT 24 May 19 12:56:38 PM PDT 24 2801271346 ps
T921 /workspace/coverage/default/25.sram_ctrl_stress_all.2738913715 May 19 12:55:43 PM PDT 24 May 19 01:49:37 PM PDT 24 132828611062 ps
T922 /workspace/coverage/default/9.sram_ctrl_mem_walk.1380256279 May 19 12:54:49 PM PDT 24 May 19 12:57:32 PM PDT 24 43075219893 ps
T923 /workspace/coverage/default/48.sram_ctrl_bijection.2005395365 May 19 12:57:45 PM PDT 24 May 19 01:07:05 PM PDT 24 36226442314 ps
T924 /workspace/coverage/default/32.sram_ctrl_alert_test.3820129089 May 19 12:56:11 PM PDT 24 May 19 12:56:13 PM PDT 24 16670083 ps
T925 /workspace/coverage/default/39.sram_ctrl_partial_access.694759861 May 19 12:56:40 PM PDT 24 May 19 12:58:17 PM PDT 24 1234571301 ps
T926 /workspace/coverage/default/27.sram_ctrl_max_throughput.25348104 May 19 12:55:48 PM PDT 24 May 19 12:56:09 PM PDT 24 3055188025 ps
T927 /workspace/coverage/default/41.sram_ctrl_smoke.635617703 May 19 12:57:01 PM PDT 24 May 19 12:57:11 PM PDT 24 6278367731 ps
T928 /workspace/coverage/default/0.sram_ctrl_ram_cfg.824792837 May 19 12:54:12 PM PDT 24 May 19 12:54:21 PM PDT 24 1763306369 ps
T929 /workspace/coverage/default/24.sram_ctrl_executable.457491925 May 19 12:55:37 PM PDT 24 May 19 12:59:51 PM PDT 24 5169558463 ps
T930 /workspace/coverage/default/39.sram_ctrl_bijection.3748667558 May 19 12:56:40 PM PDT 24 May 19 01:04:28 PM PDT 24 7044157748 ps
T931 /workspace/coverage/default/40.sram_ctrl_multiple_keys.1408909494 May 19 12:56:51 PM PDT 24 May 19 01:06:58 PM PDT 24 23426668606 ps
T932 /workspace/coverage/default/43.sram_ctrl_lc_escalation.1512853925 May 19 12:57:15 PM PDT 24 May 19 12:57:56 PM PDT 24 29306392765 ps
T933 /workspace/coverage/default/31.sram_ctrl_partial_access.3438846399 May 19 12:56:02 PM PDT 24 May 19 12:56:07 PM PDT 24 383902896 ps
T934 /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.3959378995 May 19 12:55:35 PM PDT 24 May 19 01:01:58 PM PDT 24 12929543552 ps
T935 /workspace/coverage/default/45.sram_ctrl_stress_all.543716548 May 19 12:57:32 PM PDT 24 May 19 03:18:21 PM PDT 24 369880437618 ps
T99 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.377136451 May 19 12:50:53 PM PDT 24 May 19 12:50:58 PM PDT 24 134829471 ps
T936 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.252752310 May 19 12:51:05 PM PDT 24 May 19 12:51:11 PM PDT 24 371946319 ps
T100 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1224475641 May 19 12:51:03 PM PDT 24 May 19 12:51:07 PM PDT 24 520816728 ps
T937 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2179907719 May 19 12:50:55 PM PDT 24 May 19 12:51:02 PM PDT 24 382907195 ps
T92 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3046057823 May 19 12:51:06 PM PDT 24 May 19 12:51:08 PM PDT 24 40380762 ps
T96 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3788552872 May 19 12:50:51 PM PDT 24 May 19 12:50:55 PM PDT 24 22258658 ps
T63 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1026939273 May 19 12:50:50 PM PDT 24 May 19 12:50:54 PM PDT 24 39480636 ps
T64 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2845057998 May 19 12:51:13 PM PDT 24 May 19 12:51:16 PM PDT 24 32885088 ps
T101 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.699501317 May 19 12:51:08 PM PDT 24 May 19 12:51:11 PM PDT 24 330132038 ps
T65 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2810977785 May 19 12:50:58 PM PDT 24 May 19 12:51:02 PM PDT 24 16710679 ps
T66 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2770232721 May 19 12:50:56 PM PDT 24 May 19 12:51:00 PM PDT 24 168424867 ps
T97 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2703720611 May 19 12:50:58 PM PDT 24 May 19 12:51:03 PM PDT 24 51504079 ps
T67 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3815226074 May 19 12:50:50 PM PDT 24 May 19 12:50:54 PM PDT 24 19157171 ps
T98 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2549857386 May 19 12:51:10 PM PDT 24 May 19 12:51:13 PM PDT 24 43845193 ps
T68 /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1982467438 May 19 12:50:56 PM PDT 24 May 19 12:51:51 PM PDT 24 7313092845 ps
T114 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1863588243 May 19 12:50:59 PM PDT 24 May 19 12:51:05 PM PDT 24 793778853 ps
T69 /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1935895558 May 19 12:51:11 PM PDT 24 May 19 12:51:14 PM PDT 24 28554977 ps
T70 /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3457934304 May 19 12:50:53 PM PDT 24 May 19 12:51:25 PM PDT 24 10125142695 ps
T71 /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2185389039 May 19 12:51:11 PM PDT 24 May 19 12:51:14 PM PDT 24 203779433 ps
T72 /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1132698377 May 19 12:50:57 PM PDT 24 May 19 12:51:50 PM PDT 24 54279581093 ps
T93 /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3586633091 May 19 12:51:06 PM PDT 24 May 19 12:51:08 PM PDT 24 42505533 ps
T938 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2881089064 May 19 12:50:53 PM PDT 24 May 19 12:50:58 PM PDT 24 93852946 ps
T939 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.46898602 May 19 12:50:53 PM PDT 24 May 19 12:51:00 PM PDT 24 134174806 ps
T940 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2331125999 May 19 12:50:53 PM PDT 24 May 19 12:50:56 PM PDT 24 14721916 ps
T75 /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2030936671 May 19 12:51:10 PM PDT 24 May 19 12:51:58 PM PDT 24 61566769330 ps
T941 /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2341596153 May 19 12:51:06 PM PDT 24 May 19 12:51:08 PM PDT 24 15962484 ps
T942 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3743568905 May 19 12:51:06 PM PDT 24 May 19 12:51:11 PM PDT 24 40405206 ps
T943 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.687622207 May 19 12:50:59 PM PDT 24 May 19 12:51:03 PM PDT 24 15511257 ps
T76 /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2076652625 May 19 12:51:00 PM PDT 24 May 19 12:51:51 PM PDT 24 7535004493 ps
T944 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1863763753 May 19 12:50:52 PM PDT 24 May 19 12:50:58 PM PDT 24 359119921 ps
T945 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1341024522 May 19 12:51:03 PM PDT 24 May 19 12:51:09 PM PDT 24 1433482678 ps
T946 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1251265285 May 19 12:50:51 PM PDT 24 May 19 12:50:55 PM PDT 24 50038205 ps
T947 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.17230341 May 19 12:51:05 PM PDT 24 May 19 12:51:08 PM PDT 24 155648412 ps
T948 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1504277603 May 19 12:50:57 PM PDT 24 May 19 12:51:04 PM PDT 24 1380194434 ps
T949 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.4139192411 May 19 12:51:09 PM PDT 24 May 19 12:51:10 PM PDT 24 12776574 ps
T950 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1066727338 May 19 12:50:44 PM PDT 24 May 19 12:50:51 PM PDT 24 2146340517 ps
T951 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3387317344 May 19 12:51:11 PM PDT 24 May 19 12:51:17 PM PDT 24 1571126744 ps
T77 /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.4113597082 May 19 12:51:05 PM PDT 24 May 19 12:51:34 PM PDT 24 14749049104 ps
T952 /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.70350738 May 19 12:51:01 PM PDT 24 May 19 12:51:04 PM PDT 24 182417646 ps
T115 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.44774876 May 19 12:50:54 PM PDT 24 May 19 12:51:00 PM PDT 24 689962115 ps
T78 /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3579034115 May 19 12:50:51 PM PDT 24 May 19 12:51:22 PM PDT 24 14887184714 ps
T116 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3852370358 May 19 12:50:52 PM PDT 24 May 19 12:50:57 PM PDT 24 237215178 ps
T953 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3682670936 May 19 12:51:18 PM PDT 24 May 19 12:51:25 PM PDT 24 31694926 ps
T87 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.24594299 May 19 12:51:00 PM PDT 24 May 19 12:51:04 PM PDT 24 107698924 ps
T117 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3066975102 May 19 12:51:04 PM PDT 24 May 19 12:51:08 PM PDT 24 259636311 ps
T954 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.533990218 May 19 12:50:53 PM PDT 24 May 19 12:50:58 PM PDT 24 44115418 ps
T955 /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1751954927 May 19 12:50:52 PM PDT 24 May 19 12:50:56 PM PDT 24 51417299 ps
T956 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.4270819661 May 19 12:51:05 PM PDT 24 May 19 12:51:07 PM PDT 24 10488172 ps
T957 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2610018478 May 19 12:50:58 PM PDT 24 May 19 12:51:06 PM PDT 24 141868127 ps
T118 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3470717702 May 19 12:51:12 PM PDT 24 May 19 12:51:16 PM PDT 24 332475978 ps
T958 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2369530794 May 19 12:50:59 PM PDT 24 May 19 12:51:03 PM PDT 24 35694530 ps
T959 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3844038684 May 19 12:50:58 PM PDT 24 May 19 12:51:06 PM PDT 24 441985238 ps
T960 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2407397155 May 19 12:50:48 PM PDT 24 May 19 12:50:53 PM PDT 24 138578470 ps
T961 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2974852615 May 19 12:51:06 PM PDT 24 May 19 12:51:11 PM PDT 24 55702031 ps
T962 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.378785430 May 19 12:51:13 PM PDT 24 May 19 12:51:18 PM PDT 24 422689819 ps
T963 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.164406644 May 19 12:51:04 PM PDT 24 May 19 12:51:09 PM PDT 24 129455515 ps
T964 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1688725190 May 19 12:50:58 PM PDT 24 May 19 12:51:03 PM PDT 24 398140637 ps
T965 /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2530855257 May 19 12:51:06 PM PDT 24 May 19 12:51:08 PM PDT 24 26018754 ps
T966 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.4066750214 May 19 12:51:06 PM PDT 24 May 19 12:51:11 PM PDT 24 1481263459 ps
T967 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1630454311 May 19 12:50:51 PM PDT 24 May 19 12:50:57 PM PDT 24 31693873 ps
T968 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2470423571 May 19 12:50:57 PM PDT 24 May 19 12:51:05 PM PDT 24 781385345 ps
T969 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2908187405 May 19 12:50:55 PM PDT 24 May 19 12:50:58 PM PDT 24 29389526 ps
T970 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.370867046 May 19 12:51:06 PM PDT 24 May 19 12:51:11 PM PDT 24 753565869 ps
T971 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.284490910 May 19 12:51:07 PM PDT 24 May 19 12:51:11 PM PDT 24 1026915120 ps
T972 /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3056782700 May 19 12:50:58 PM PDT 24 May 19 12:51:02 PM PDT 24 52248585 ps
T973 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1820778969 May 19 12:50:55 PM PDT 24 May 19 12:51:01 PM PDT 24 99455374 ps
T974 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1860604208 May 19 12:51:03 PM PDT 24 May 19 12:51:06 PM PDT 24 79787543 ps
T975 /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3808228273 May 19 12:50:51 PM PDT 24 May 19 12:50:55 PM PDT 24 37784962 ps
T976 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.388388943 May 19 12:51:05 PM PDT 24 May 19 12:51:07 PM PDT 24 44750724 ps
T120 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2283500912 May 19 12:50:59 PM PDT 24 May 19 12:51:04 PM PDT 24 1231509461 ps
T977 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2889430912 May 19 12:51:10 PM PDT 24 May 19 12:51:13 PM PDT 24 29974507 ps
T978 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.4238559696 May 19 12:50:53 PM PDT 24 May 19 12:50:57 PM PDT 24 49187479 ps
T121 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3419922180 May 19 12:51:00 PM PDT 24 May 19 12:51:05 PM PDT 24 194657381 ps
T979 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.360983188 May 19 12:50:49 PM PDT 24 May 19 12:50:52 PM PDT 24 14535098 ps
T980 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2037045247 May 19 12:50:59 PM PDT 24 May 19 12:51:05 PM PDT 24 664433851 ps
T119 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.775860476 May 19 12:50:59 PM PDT 24 May 19 12:51:05 PM PDT 24 927383373 ps
T981 /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3223474949 May 19 12:51:05 PM PDT 24 May 19 12:51:07 PM PDT 24 34253298 ps
T86 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2398276370 May 19 12:50:45 PM PDT 24 May 19 12:50:49 PM PDT 24 19281231 ps
T88 /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1774028208 May 19 12:50:52 PM PDT 24 May 19 12:51:23 PM PDT 24 3921243782 ps
T982 /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1771893464 May 19 12:51:04 PM PDT 24 May 19 12:51:55 PM PDT 24 7285471499 ps
T983 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2323203679 May 19 12:51:10 PM PDT 24 May 19 12:51:13 PM PDT 24 111378034 ps
T984 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.801820500 May 19 12:50:50 PM PDT 24 May 19 12:50:58 PM PDT 24 1529747661 ps
T985 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3903021767 May 19 12:51:06 PM PDT 24 May 19 12:51:08 PM PDT 24 13906489 ps
T986 /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3174430942 May 19 12:51:05 PM PDT 24 May 19 12:51:07 PM PDT 24 39963705 ps
T89 /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.729061411 May 19 12:51:01 PM PDT 24 May 19 12:52:02 PM PDT 24 100640960659 ps
T987 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1867801316 May 19 12:50:49 PM PDT 24 May 19 12:50:54 PM PDT 24 92354339 ps
T988 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1297306285 May 19 12:50:52 PM PDT 24 May 19 12:50:57 PM PDT 24 194636282 ps
T989 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3571776443 May 19 12:51:11 PM PDT 24 May 19 12:51:17 PM PDT 24 1409295174 ps
T990 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3109598631 May 19 12:51:11 PM PDT 24 May 19 12:51:17 PM PDT 24 720515806 ps
T991 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.4025302774 May 19 12:50:50 PM PDT 24 May 19 12:50:56 PM PDT 24 30045614 ps
T992 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2562000698 May 19 12:50:57 PM PDT 24 May 19 12:51:04 PM PDT 24 364629769 ps
T993 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3797277830 May 19 12:51:15 PM PDT 24 May 19 12:51:21 PM PDT 24 33049002 ps
T994 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.690522004 May 19 12:51:09 PM PDT 24 May 19 12:51:13 PM PDT 24 1429175717 ps
T995 /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.276905224 May 19 12:51:11 PM PDT 24 May 19 12:51:38 PM PDT 24 7724760659 ps
T90 /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3014051102 May 19 12:50:58 PM PDT 24 May 19 12:51:28 PM PDT 24 3852233497 ps
T996 /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3074681313 May 19 12:51:11 PM PDT 24 May 19 12:51:39 PM PDT 24 4088772420 ps
T997 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1824164169 May 19 12:51:03 PM PDT 24 May 19 12:51:07 PM PDT 24 109352346 ps
T998 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2319053005 May 19 12:51:04 PM PDT 24 May 19 12:51:09 PM PDT 24 116691150 ps
T999 /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2172181882 May 19 12:50:50 PM PDT 24 May 19 12:50:53 PM PDT 24 22433611 ps
T1000 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.391377887 May 19 12:50:56 PM PDT 24 May 19 12:51:03 PM PDT 24 428201433 ps
T1001 /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2999985304 May 19 12:51:09 PM PDT 24 May 19 12:51:11 PM PDT 24 27083106 ps
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%