Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	341239174	1			T1	31376		T2	20000		T3	917504
instr_valid_dis	293904798	1			T1	31376		T2	20000		T3	917504
instr_en	29957771	1			T9	128784		T6	61264		T13	229862

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	17113185	1			T9	33604		T6	189754		T13	58730
sram_ifetch_valid_disable	294783423	1			T1	31376		T2	20000		T3	917504
sram_ifetch_enable	29342566	1			T9	229506		T6	207462		T13	161182

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	341239174	1			T1	31376		T2	20000		T3	917504
hw_debug_en_valid_off	297962812	1			T1	31376		T2	20000		T3	917504
hw_debug_en_on	30557446	1			T9	237644		T6	419976		T13	104

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	294783423	1			T1	31376		T2	20000		T3	917504
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	280396594	1			T1	31376		T2	20000		T3	917504
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	10297583	1			T9	124168		T6	22680		T13	9950
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4884067	1			T9	11384		T6	130330		T13	58670
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1363688	1			T6	130330		T14	18128		T24	15894
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2556900	1			T13	58670		T23	41216		T8	26032
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	9701046	1			T9	10750		T6	51764		T13	60
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	3981232	1			T23	17044		T8	30970		T25	46872
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	2297260	1			T6	33810		T13	60		T14	65818
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	9651396	1			T9	36534		T6	295314		T14	3296
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3761942	1			T9	20458		T6	295314		T14	3296
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4522666	1			T9	16076		T17	13024		T23	117876

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	13383656	1			T9	4616		T6	4774		T13	161182
lc_exec_en	11205004	1			T9	190360		T6	72898		T13	44
valid_exec_dis	288764049	1			T1	31376		T2	20000		T3	917504
invalid_exec_dis	46455751	1			T9	263110		T6	397216		T13	219912