Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	139645463	1			T1	2407		T2	8222		T3	458752
triple_byte_access	2982614	1			T2	354		T4	201		T9	2039
halfword_access	4563475	1			T2	526		T4	334		T9	3015
byte_access	6362889	1			T2	731		T4	459		T9	3956
zero_access	1902884	1			T2	167		T4	99		T9	974

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

77716557

1

T2

4979

T3

229376

T5

4382

auto[1]

77740768

1

T1

2407

T2

5021

T3

229376

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	69662373	1			T2	4099		T3	229376		T5	4382
auto[0]	triple_byte_access	1430727	1			T2	173		T4	96		T9	1087
auto[0]	halfword_access	2236923	1			T2	252		T4	181		T9	1546
auto[0]	byte_access	3258771	1			T2	369		T4	225		T9	2091
auto[0]	zero_access	1127763	1			T2	86		T4	47		T9	500
auto[1]	word_access	69983090	1			T1	2407		T2	4123		T3	229376
auto[1]	triple_byte_access	1551887	1			T2	181		T4	105		T9	952
auto[1]	halfword_access	2326552	1			T2	274		T4	153		T9	1469
auto[1]	byte_access	3104118	1			T2	362		T4	234		T9	1865
auto[1]	zero_access	775121	1			T2	81		T4	52		T9	474