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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.09 99.81 96.99 100.00 100.00 98.60 99.70 98.52


Total test records in report: 1035
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T802 /workspace/coverage/default/12.sram_ctrl_mem_walk.3529894113 May 21 02:57:56 PM PDT 24 May 21 03:00:31 PM PDT 24 32782646499 ps
T803 /workspace/coverage/default/30.sram_ctrl_mem_partial_access.138930624 May 21 02:59:46 PM PDT 24 May 21 03:01:07 PM PDT 24 32663666575 ps
T122 /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.1631921595 May 21 02:57:56 PM PDT 24 May 21 02:58:23 PM PDT 24 1341801741 ps
T804 /workspace/coverage/default/6.sram_ctrl_lc_escalation.115634981 May 21 02:57:37 PM PDT 24 May 21 02:57:52 PM PDT 24 780857746 ps
T805 /workspace/coverage/default/35.sram_ctrl_bijection.1010086345 May 21 03:00:38 PM PDT 24 May 21 03:33:07 PM PDT 24 42954972497 ps
T806 /workspace/coverage/default/7.sram_ctrl_mem_walk.1892226642 May 21 02:57:38 PM PDT 24 May 21 03:00:13 PM PDT 24 18126238436 ps
T807 /workspace/coverage/default/31.sram_ctrl_bijection.2408680317 May 21 02:59:53 PM PDT 24 May 21 03:15:54 PM PDT 24 44257901789 ps
T808 /workspace/coverage/default/21.sram_ctrl_multiple_keys.984786202 May 21 02:58:46 PM PDT 24 May 21 03:22:22 PM PDT 24 40234907676 ps
T809 /workspace/coverage/default/1.sram_ctrl_executable.1712237071 May 21 02:57:28 PM PDT 24 May 21 03:22:58 PM PDT 24 14836154771 ps
T810 /workspace/coverage/default/20.sram_ctrl_multiple_keys.275365124 May 21 02:58:25 PM PDT 24 May 21 03:00:50 PM PDT 24 1428983556 ps
T811 /workspace/coverage/default/48.sram_ctrl_alert_test.2980963188 May 21 03:02:59 PM PDT 24 May 21 03:03:01 PM PDT 24 35035905 ps
T812 /workspace/coverage/default/20.sram_ctrl_bijection.4191998526 May 21 02:58:26 PM PDT 24 May 21 03:21:56 PM PDT 24 21330527859 ps
T813 /workspace/coverage/default/5.sram_ctrl_max_throughput.1585446065 May 21 02:57:36 PM PDT 24 May 21 02:58:06 PM PDT 24 1431979862 ps
T814 /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.947228649 May 21 03:01:38 PM PDT 24 May 21 03:01:52 PM PDT 24 3141722853 ps
T815 /workspace/coverage/default/13.sram_ctrl_max_throughput.3688840044 May 21 02:57:56 PM PDT 24 May 21 02:58:36 PM PDT 24 2851928228 ps
T816 /workspace/coverage/default/17.sram_ctrl_ram_cfg.2128765766 May 21 02:58:05 PM PDT 24 May 21 02:58:18 PM PDT 24 676347586 ps
T817 /workspace/coverage/default/18.sram_ctrl_regwen.1696080898 May 21 02:58:18 PM PDT 24 May 21 03:15:36 PM PDT 24 164605400698 ps
T818 /workspace/coverage/default/37.sram_ctrl_lc_escalation.2550165342 May 21 03:00:59 PM PDT 24 May 21 03:02:03 PM PDT 24 45195046530 ps
T819 /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.3999164254 May 21 03:01:14 PM PDT 24 May 21 03:03:19 PM PDT 24 3128983183 ps
T820 /workspace/coverage/default/28.sram_ctrl_smoke.2107377463 May 21 02:59:27 PM PDT 24 May 21 02:59:48 PM PDT 24 4289048385 ps
T821 /workspace/coverage/default/42.sram_ctrl_partial_access.4065122407 May 21 03:01:43 PM PDT 24 May 21 03:01:50 PM PDT 24 416874412 ps
T123 /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.908763887 May 21 02:59:58 PM PDT 24 May 21 03:00:23 PM PDT 24 6624925796 ps
T822 /workspace/coverage/default/44.sram_ctrl_bijection.3183566138 May 21 03:02:09 PM PDT 24 May 21 03:48:55 PM PDT 24 501600026791 ps
T823 /workspace/coverage/default/11.sram_ctrl_mem_walk.754381756 May 21 02:57:54 PM PDT 24 May 21 03:00:33 PM PDT 24 49142574083 ps
T824 /workspace/coverage/default/33.sram_ctrl_regwen.2807788669 May 21 03:00:17 PM PDT 24 May 21 03:08:40 PM PDT 24 29765463040 ps
T825 /workspace/coverage/default/35.sram_ctrl_stress_all.2367718004 May 21 03:00:45 PM PDT 24 May 21 03:52:55 PM PDT 24 103863469545 ps
T826 /workspace/coverage/default/12.sram_ctrl_access_during_key_req.2184087342 May 21 02:57:55 PM PDT 24 May 21 03:03:16 PM PDT 24 8877353754 ps
T827 /workspace/coverage/default/8.sram_ctrl_executable.1146597230 May 21 02:57:47 PM PDT 24 May 21 03:10:00 PM PDT 24 71372716051 ps
T828 /workspace/coverage/default/30.sram_ctrl_access_during_key_req.2183076229 May 21 02:59:46 PM PDT 24 May 21 03:19:25 PM PDT 24 299959376158 ps
T829 /workspace/coverage/default/2.sram_ctrl_stress_pipeline.2217305503 May 21 02:57:25 PM PDT 24 May 21 03:02:42 PM PDT 24 5278636632 ps
T830 /workspace/coverage/default/3.sram_ctrl_max_throughput.466096105 May 21 02:57:30 PM PDT 24 May 21 02:57:59 PM PDT 24 1410940727 ps
T831 /workspace/coverage/default/15.sram_ctrl_smoke.2617582397 May 21 02:58:03 PM PDT 24 May 21 02:58:38 PM PDT 24 6929884319 ps
T832 /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.3556666105 May 21 02:57:28 PM PDT 24 May 21 03:00:12 PM PDT 24 26374954796 ps
T833 /workspace/coverage/default/26.sram_ctrl_stress_all.2424473646 May 21 02:59:16 PM PDT 24 May 21 05:13:47 PM PDT 24 1595158206234 ps
T834 /workspace/coverage/default/27.sram_ctrl_access_during_key_req.3202324543 May 21 02:59:20 PM PDT 24 May 21 03:36:55 PM PDT 24 21040127899 ps
T835 /workspace/coverage/default/15.sram_ctrl_regwen.487832970 May 21 02:58:01 PM PDT 24 May 21 02:59:41 PM PDT 24 2954570478 ps
T836 /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.1413671963 May 21 03:03:07 PM PDT 24 May 21 03:05:03 PM PDT 24 811906955 ps
T837 /workspace/coverage/default/25.sram_ctrl_lc_escalation.688139854 May 21 02:59:09 PM PDT 24 May 21 03:01:06 PM PDT 24 40897588415 ps
T838 /workspace/coverage/default/16.sram_ctrl_alert_test.2841197503 May 21 02:58:05 PM PDT 24 May 21 02:58:15 PM PDT 24 18892194 ps
T839 /workspace/coverage/default/34.sram_ctrl_max_throughput.4200706029 May 21 03:00:28 PM PDT 24 May 21 03:03:10 PM PDT 24 882914045 ps
T840 /workspace/coverage/default/8.sram_ctrl_partial_access.364603572 May 21 02:57:51 PM PDT 24 May 21 02:58:21 PM PDT 24 1446378518 ps
T841 /workspace/coverage/default/18.sram_ctrl_partial_access.3352846487 May 21 02:58:11 PM PDT 24 May 21 02:58:33 PM PDT 24 2114404689 ps
T842 /workspace/coverage/default/20.sram_ctrl_smoke.3207166667 May 21 02:58:23 PM PDT 24 May 21 02:58:44 PM PDT 24 3204459837 ps
T843 /workspace/coverage/default/37.sram_ctrl_bijection.2505052196 May 21 03:00:52 PM PDT 24 May 21 03:11:30 PM PDT 24 81635787381 ps
T844 /workspace/coverage/default/41.sram_ctrl_access_during_key_req.1153484577 May 21 03:01:37 PM PDT 24 May 21 03:02:16 PM PDT 24 8803754030 ps
T845 /workspace/coverage/default/2.sram_ctrl_smoke.3387755455 May 21 02:57:25 PM PDT 24 May 21 02:57:54 PM PDT 24 5213052784 ps
T846 /workspace/coverage/default/13.sram_ctrl_stress_pipeline.681575387 May 21 02:57:54 PM PDT 24 May 21 03:01:57 PM PDT 24 15533276557 ps
T847 /workspace/coverage/default/15.sram_ctrl_ram_cfg.2962175599 May 21 02:58:10 PM PDT 24 May 21 02:58:21 PM PDT 24 364324587 ps
T848 /workspace/coverage/default/1.sram_ctrl_access_during_key_req.628767255 May 21 02:57:24 PM PDT 24 May 21 03:11:57 PM PDT 24 44230121032 ps
T849 /workspace/coverage/default/36.sram_ctrl_stress_pipeline.3448049586 May 21 03:00:45 PM PDT 24 May 21 03:03:00 PM PDT 24 4754671404 ps
T850 /workspace/coverage/default/16.sram_ctrl_executable.392816748 May 21 02:58:05 PM PDT 24 May 21 03:05:35 PM PDT 24 7437343010 ps
T851 /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.2282342874 May 21 02:57:35 PM PDT 24 May 21 03:06:32 PM PDT 24 22043036061 ps
T852 /workspace/coverage/default/48.sram_ctrl_regwen.2453398571 May 21 03:03:01 PM PDT 24 May 21 03:19:56 PM PDT 24 15431243490 ps
T853 /workspace/coverage/default/12.sram_ctrl_regwen.806611907 May 21 02:57:57 PM PDT 24 May 21 03:32:26 PM PDT 24 128755272212 ps
T854 /workspace/coverage/default/13.sram_ctrl_access_during_key_req.3478802833 May 21 02:57:51 PM PDT 24 May 21 03:10:09 PM PDT 24 53347524691 ps
T855 /workspace/coverage/default/20.sram_ctrl_partial_access.3449891420 May 21 02:58:25 PM PDT 24 May 21 02:58:47 PM PDT 24 4396086441 ps
T856 /workspace/coverage/default/7.sram_ctrl_stress_pipeline.1281532845 May 21 02:57:36 PM PDT 24 May 21 03:02:05 PM PDT 24 8743149267 ps
T857 /workspace/coverage/default/32.sram_ctrl_multiple_keys.4246509286 May 21 03:00:00 PM PDT 24 May 21 03:16:22 PM PDT 24 17160693425 ps
T858 /workspace/coverage/default/21.sram_ctrl_lc_escalation.3137465658 May 21 02:58:32 PM PDT 24 May 21 02:59:13 PM PDT 24 6167684721 ps
T859 /workspace/coverage/default/32.sram_ctrl_lc_escalation.2676331020 May 21 03:00:03 PM PDT 24 May 21 03:01:43 PM PDT 24 53225221296 ps
T860 /workspace/coverage/default/17.sram_ctrl_smoke.963616783 May 21 02:58:11 PM PDT 24 May 21 02:58:22 PM PDT 24 727410210 ps
T861 /workspace/coverage/default/36.sram_ctrl_partial_access.3426079105 May 21 03:00:47 PM PDT 24 May 21 03:01:08 PM PDT 24 1198938548 ps
T862 /workspace/coverage/default/10.sram_ctrl_partial_access.3176981261 May 21 02:57:51 PM PDT 24 May 21 03:00:57 PM PDT 24 1093389257 ps
T863 /workspace/coverage/default/12.sram_ctrl_mem_partial_access.3806771154 May 21 02:57:53 PM PDT 24 May 21 02:59:13 PM PDT 24 4787982194 ps
T864 /workspace/coverage/default/37.sram_ctrl_ram_cfg.4185679462 May 21 03:00:59 PM PDT 24 May 21 03:01:04 PM PDT 24 1354214743 ps
T865 /workspace/coverage/default/33.sram_ctrl_lc_escalation.3087408410 May 21 03:00:15 PM PDT 24 May 21 03:02:10 PM PDT 24 83021985416 ps
T866 /workspace/coverage/default/29.sram_ctrl_executable.4077332817 May 21 02:59:34 PM PDT 24 May 21 03:14:01 PM PDT 24 21830453714 ps
T867 /workspace/coverage/default/21.sram_ctrl_stress_all.2301807531 May 21 02:58:41 PM PDT 24 May 21 04:28:49 PM PDT 24 54320505249 ps
T868 /workspace/coverage/default/39.sram_ctrl_access_during_key_req.4294435468 May 21 03:01:18 PM PDT 24 May 21 03:04:34 PM PDT 24 4465100322 ps
T869 /workspace/coverage/default/24.sram_ctrl_bijection.4014153613 May 21 02:58:57 PM PDT 24 May 21 03:16:16 PM PDT 24 86791031196 ps
T870 /workspace/coverage/default/33.sram_ctrl_max_throughput.3143069410 May 21 03:00:16 PM PDT 24 May 21 03:01:25 PM PDT 24 8092076792 ps
T871 /workspace/coverage/default/16.sram_ctrl_mem_partial_access.2356178085 May 21 02:58:06 PM PDT 24 May 21 03:00:41 PM PDT 24 8977622937 ps
T872 /workspace/coverage/default/7.sram_ctrl_alert_test.2545827504 May 21 02:57:46 PM PDT 24 May 21 02:57:55 PM PDT 24 42162384 ps
T873 /workspace/coverage/default/13.sram_ctrl_alert_test.13284241 May 21 02:57:56 PM PDT 24 May 21 02:58:07 PM PDT 24 39796186 ps
T874 /workspace/coverage/default/26.sram_ctrl_multiple_keys.1725572129 May 21 02:59:10 PM PDT 24 May 21 03:08:30 PM PDT 24 3690216466 ps
T875 /workspace/coverage/default/46.sram_ctrl_stress_all.938128306 May 21 03:02:44 PM PDT 24 May 21 04:50:43 PM PDT 24 86981986702 ps
T876 /workspace/coverage/default/22.sram_ctrl_partial_access.438899052 May 21 02:58:40 PM PDT 24 May 21 02:58:56 PM PDT 24 1119973503 ps
T877 /workspace/coverage/default/44.sram_ctrl_stress_all.3202309815 May 21 03:02:20 PM PDT 24 May 21 05:13:10 PM PDT 24 385823423637 ps
T878 /workspace/coverage/default/47.sram_ctrl_access_during_key_req.1806889393 May 21 03:02:49 PM PDT 24 May 21 03:15:20 PM PDT 24 39820224347 ps
T879 /workspace/coverage/default/29.sram_ctrl_bijection.832403969 May 21 02:59:34 PM PDT 24 May 21 03:32:51 PM PDT 24 123703835793 ps
T880 /workspace/coverage/default/35.sram_ctrl_alert_test.2177380827 May 21 03:00:48 PM PDT 24 May 21 03:00:51 PM PDT 24 36370087 ps
T881 /workspace/coverage/default/23.sram_ctrl_max_throughput.1701289767 May 21 02:58:53 PM PDT 24 May 21 03:01:11 PM PDT 24 1629891404 ps
T882 /workspace/coverage/default/49.sram_ctrl_access_during_key_req.305661712 May 21 03:03:06 PM PDT 24 May 21 03:21:20 PM PDT 24 24505428044 ps
T883 /workspace/coverage/default/44.sram_ctrl_regwen.4925406 May 21 03:02:14 PM PDT 24 May 21 03:26:36 PM PDT 24 17468943033 ps
T884 /workspace/coverage/default/21.sram_ctrl_smoke.1392606361 May 21 02:58:31 PM PDT 24 May 21 03:01:16 PM PDT 24 1853676047 ps
T885 /workspace/coverage/default/10.sram_ctrl_alert_test.1228111347 May 21 02:57:54 PM PDT 24 May 21 02:58:04 PM PDT 24 18401849 ps
T886 /workspace/coverage/default/12.sram_ctrl_stress_all.2394920623 May 21 02:57:59 PM PDT 24 May 21 03:55:01 PM PDT 24 266126097110 ps
T887 /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.1391869184 May 21 03:00:23 PM PDT 24 May 21 03:03:49 PM PDT 24 8342078982 ps
T888 /workspace/coverage/default/36.sram_ctrl_smoke.3723847339 May 21 03:00:49 PM PDT 24 May 21 03:01:05 PM PDT 24 868904356 ps
T889 /workspace/coverage/default/9.sram_ctrl_max_throughput.3301535679 May 21 02:57:42 PM PDT 24 May 21 02:59:14 PM PDT 24 4959856042 ps
T890 /workspace/coverage/default/8.sram_ctrl_max_throughput.23001695 May 21 02:57:44 PM PDT 24 May 21 02:58:36 PM PDT 24 769700321 ps
T891 /workspace/coverage/default/23.sram_ctrl_multiple_keys.4274574416 May 21 02:58:54 PM PDT 24 May 21 03:19:14 PM PDT 24 52767246503 ps
T892 /workspace/coverage/default/5.sram_ctrl_lc_escalation.111397282 May 21 02:57:38 PM PDT 24 May 21 02:58:45 PM PDT 24 38014228888 ps
T893 /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.3914207370 May 21 03:00:27 PM PDT 24 May 21 03:00:39 PM PDT 24 365470912 ps
T894 /workspace/coverage/default/16.sram_ctrl_mem_walk.3003150859 May 21 02:58:06 PM PDT 24 May 21 03:02:44 PM PDT 24 29329641391 ps
T895 /workspace/coverage/default/45.sram_ctrl_stress_pipeline.1761162454 May 21 03:02:27 PM PDT 24 May 21 03:08:08 PM PDT 24 8576399657 ps
T896 /workspace/coverage/default/27.sram_ctrl_max_throughput.1972264384 May 21 02:59:22 PM PDT 24 May 21 02:59:34 PM PDT 24 707184892 ps
T897 /workspace/coverage/default/26.sram_ctrl_lc_escalation.2938973988 May 21 02:59:12 PM PDT 24 May 21 02:59:45 PM PDT 24 8320812411 ps
T898 /workspace/coverage/default/19.sram_ctrl_mem_walk.4161390700 May 21 02:58:25 PM PDT 24 May 21 03:02:28 PM PDT 24 16421369768 ps
T899 /workspace/coverage/default/9.sram_ctrl_partial_access.2375102168 May 21 02:57:43 PM PDT 24 May 21 02:57:59 PM PDT 24 1581115110 ps
T900 /workspace/coverage/default/2.sram_ctrl_partial_access.169162944 May 21 02:57:24 PM PDT 24 May 21 02:57:50 PM PDT 24 962963816 ps
T901 /workspace/coverage/default/46.sram_ctrl_mem_partial_access.1659793999 May 21 03:02:44 PM PDT 24 May 21 03:04:05 PM PDT 24 29457709222 ps
T902 /workspace/coverage/default/7.sram_ctrl_executable.40079959 May 21 02:57:38 PM PDT 24 May 21 03:05:03 PM PDT 24 7362088317 ps
T903 /workspace/coverage/default/1.sram_ctrl_smoke.2189895960 May 21 02:57:26 PM PDT 24 May 21 02:58:32 PM PDT 24 4616917532 ps
T904 /workspace/coverage/default/35.sram_ctrl_stress_pipeline.1667521152 May 21 03:00:34 PM PDT 24 May 21 03:07:02 PM PDT 24 4922940825 ps
T905 /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.1509375224 May 21 03:01:34 PM PDT 24 May 21 03:01:45 PM PDT 24 1287572414 ps
T906 /workspace/coverage/default/47.sram_ctrl_ram_cfg.1932932256 May 21 03:03:14 PM PDT 24 May 21 03:03:19 PM PDT 24 374961119 ps
T907 /workspace/coverage/default/49.sram_ctrl_lc_escalation.2856309257 May 21 03:03:06 PM PDT 24 May 21 03:03:21 PM PDT 24 3333687652 ps
T908 /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.1393129082 May 21 03:02:08 PM PDT 24 May 21 03:02:21 PM PDT 24 3149378159 ps
T909 /workspace/coverage/default/45.sram_ctrl_mem_partial_access.2391347349 May 21 03:02:31 PM PDT 24 May 21 03:03:51 PM PDT 24 6663090022 ps
T910 /workspace/coverage/default/18.sram_ctrl_stress_pipeline.352088209 May 21 02:58:20 PM PDT 24 May 21 03:01:36 PM PDT 24 5202420756 ps
T911 /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.572508620 May 21 02:57:48 PM PDT 24 May 21 02:58:04 PM PDT 24 192990220 ps
T912 /workspace/coverage/default/8.sram_ctrl_mem_partial_access.3098614152 May 21 02:57:45 PM PDT 24 May 21 03:00:15 PM PDT 24 4539001058 ps
T913 /workspace/coverage/default/3.sram_ctrl_mem_walk.1520519232 May 21 02:57:30 PM PDT 24 May 21 03:02:24 PM PDT 24 72515059537 ps
T914 /workspace/coverage/default/11.sram_ctrl_lc_escalation.548793127 May 21 02:57:53 PM PDT 24 May 21 02:58:33 PM PDT 24 4973962115 ps
T915 /workspace/coverage/default/29.sram_ctrl_regwen.3552905812 May 21 02:59:32 PM PDT 24 May 21 03:05:34 PM PDT 24 8382767449 ps
T916 /workspace/coverage/default/46.sram_ctrl_mem_walk.960003831 May 21 03:02:43 PM PDT 24 May 21 03:05:21 PM PDT 24 41342873142 ps
T917 /workspace/coverage/default/34.sram_ctrl_bijection.1026658472 May 21 03:00:26 PM PDT 24 May 21 03:16:20 PM PDT 24 56121600518 ps
T918 /workspace/coverage/default/44.sram_ctrl_lc_escalation.2786351220 May 21 03:02:15 PM PDT 24 May 21 03:03:06 PM PDT 24 27415933343 ps
T919 /workspace/coverage/default/3.sram_ctrl_lc_escalation.973429903 May 21 02:57:32 PM PDT 24 May 21 02:58:46 PM PDT 24 25872922582 ps
T920 /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.183296680 May 21 02:57:40 PM PDT 24 May 21 03:00:03 PM PDT 24 1592005411 ps
T921 /workspace/coverage/default/8.sram_ctrl_smoke.1308565255 May 21 02:57:44 PM PDT 24 May 21 02:59:52 PM PDT 24 9709602683 ps
T922 /workspace/coverage/default/30.sram_ctrl_mem_walk.4214877540 May 21 02:59:46 PM PDT 24 May 21 03:02:04 PM PDT 24 6890406537 ps
T923 /workspace/coverage/default/0.sram_ctrl_regwen.3359431135 May 21 02:57:20 PM PDT 24 May 21 03:03:57 PM PDT 24 3054217425 ps
T924 /workspace/coverage/default/42.sram_ctrl_mem_walk.274172837 May 21 03:01:49 PM PDT 24 May 21 03:04:22 PM PDT 24 9229571470 ps
T925 /workspace/coverage/default/37.sram_ctrl_stress_pipeline.4268704096 May 21 03:00:53 PM PDT 24 May 21 03:06:20 PM PDT 24 11243853202 ps
T926 /workspace/coverage/default/29.sram_ctrl_mem_partial_access.1645934926 May 21 02:59:35 PM PDT 24 May 21 03:00:42 PM PDT 24 1889067178 ps
T927 /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.428364960 May 21 03:02:41 PM PDT 24 May 21 03:04:27 PM PDT 24 790043086 ps
T928 /workspace/coverage/default/24.sram_ctrl_partial_access.2967704591 May 21 02:59:01 PM PDT 24 May 21 02:59:20 PM PDT 24 1099094663 ps
T929 /workspace/coverage/default/44.sram_ctrl_smoke.4160146413 May 21 03:02:16 PM PDT 24 May 21 03:02:28 PM PDT 24 781702777 ps
T930 /workspace/coverage/default/6.sram_ctrl_ram_cfg.3638957060 May 21 02:57:36 PM PDT 24 May 21 02:57:47 PM PDT 24 364274885 ps
T931 /workspace/coverage/default/42.sram_ctrl_executable.3854439759 May 21 03:01:49 PM PDT 24 May 21 03:21:37 PM PDT 24 93350352503 ps
T932 /workspace/coverage/default/49.sram_ctrl_stress_all.4203270591 May 21 03:03:12 PM PDT 24 May 21 04:53:01 PM PDT 24 129821383949 ps
T933 /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.539812672 May 21 02:57:57 PM PDT 24 May 21 03:05:03 PM PDT 24 71646174419 ps
T934 /workspace/coverage/default/30.sram_ctrl_max_throughput.1683911813 May 21 02:59:44 PM PDT 24 May 21 03:00:30 PM PDT 24 742952438 ps
T935 /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.593700353 May 21 02:57:59 PM PDT 24 May 21 02:58:39 PM PDT 24 3105384438 ps
T936 /workspace/coverage/default/11.sram_ctrl_executable.3668851158 May 21 02:57:54 PM PDT 24 May 21 03:08:45 PM PDT 24 7291951285 ps
T937 /workspace/coverage/default/22.sram_ctrl_executable.1050627009 May 21 02:58:46 PM PDT 24 May 21 03:08:42 PM PDT 24 52055669570 ps
T938 /workspace/coverage/default/25.sram_ctrl_max_throughput.2190671682 May 21 02:59:09 PM PDT 24 May 21 03:00:13 PM PDT 24 818078716 ps
T939 /workspace/coverage/default/31.sram_ctrl_mem_walk.3076342000 May 21 03:00:00 PM PDT 24 May 21 03:05:07 PM PDT 24 71530514002 ps
T940 /workspace/coverage/default/13.sram_ctrl_regwen.4119951434 May 21 02:57:55 PM PDT 24 May 21 03:01:03 PM PDT 24 14713590458 ps
T941 /workspace/coverage/default/24.sram_ctrl_stress_all.4050782487 May 21 02:59:04 PM PDT 24 May 21 04:01:40 PM PDT 24 114774746765 ps
T942 /workspace/coverage/default/36.sram_ctrl_bijection.1728327925 May 21 03:00:47 PM PDT 24 May 21 03:20:50 PM PDT 24 28511719819 ps
T943 /workspace/coverage/default/16.sram_ctrl_access_during_key_req.3123893054 May 21 02:58:05 PM PDT 24 May 21 03:03:10 PM PDT 24 9426987081 ps
T944 /workspace/coverage/default/33.sram_ctrl_smoke.3578497308 May 21 03:00:11 PM PDT 24 May 21 03:00:27 PM PDT 24 822537519 ps
T945 /workspace/coverage/default/45.sram_ctrl_partial_access.1760651809 May 21 03:02:28 PM PDT 24 May 21 03:02:36 PM PDT 24 4000852151 ps
T946 /workspace/coverage/default/35.sram_ctrl_partial_access.4064534861 May 21 03:00:37 PM PDT 24 May 21 03:03:29 PM PDT 24 4573455330 ps
T947 /workspace/coverage/default/41.sram_ctrl_mem_partial_access.2655563455 May 21 03:01:44 PM PDT 24 May 21 03:02:56 PM PDT 24 2643617208 ps
T948 /workspace/coverage/default/21.sram_ctrl_partial_access.241498553 May 21 02:58:31 PM PDT 24 May 21 02:58:40 PM PDT 24 3137390063 ps
T949 /workspace/coverage/default/19.sram_ctrl_alert_test.2490375852 May 21 02:58:21 PM PDT 24 May 21 02:58:28 PM PDT 24 37303198 ps
T56 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.283843978 May 21 12:26:03 PM PDT 24 May 21 12:26:25 PM PDT 24 17630947 ps
T950 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3820101165 May 21 12:26:02 PM PDT 24 May 21 12:26:27 PM PDT 24 368783207 ps
T112 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2604314871 May 21 12:26:10 PM PDT 24 May 21 12:26:42 PM PDT 24 80880901 ps
T951 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.365182880 May 21 12:26:07 PM PDT 24 May 21 12:26:37 PM PDT 24 360713667 ps
T952 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3137468458 May 21 12:26:02 PM PDT 24 May 21 12:26:27 PM PDT 24 1465581510 ps
T96 /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3355406328 May 21 12:26:20 PM PDT 24 May 21 12:27:08 PM PDT 24 30886290 ps
T113 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3443705318 May 21 12:25:55 PM PDT 24 May 21 12:26:18 PM PDT 24 193476365 ps
T114 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.949941168 May 21 12:25:44 PM PDT 24 May 21 12:26:06 PM PDT 24 210290375 ps
T57 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2812618266 May 21 12:25:41 PM PDT 24 May 21 12:26:04 PM PDT 24 87154979 ps
T58 /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3850857901 May 21 12:25:36 PM PDT 24 May 21 12:25:58 PM PDT 24 53865534 ps
T59 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2853966398 May 21 12:26:03 PM PDT 24 May 21 12:26:26 PM PDT 24 82357684 ps
T60 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2237136688 May 21 12:25:52 PM PDT 24 May 21 12:26:13 PM PDT 24 126059012 ps
T97 /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.4226668450 May 21 12:25:37 PM PDT 24 May 21 12:26:35 PM PDT 24 41069348383 ps
T127 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.783273596 May 21 12:26:05 PM PDT 24 May 21 12:26:31 PM PDT 24 90823322 ps
T61 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1059964268 May 21 12:25:37 PM PDT 24 May 21 12:25:59 PM PDT 24 70281235 ps
T111 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3264060351 May 21 12:26:00 PM PDT 24 May 21 12:26:23 PM PDT 24 50289926 ps
T62 /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1646198786 May 21 12:26:09 PM PDT 24 May 21 12:26:37 PM PDT 24 33875961 ps
T953 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3717078913 May 21 12:26:04 PM PDT 24 May 21 12:26:30 PM PDT 24 25513450 ps
T98 /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.316443993 May 21 12:26:12 PM PDT 24 May 21 12:26:46 PM PDT 24 69949778 ps
T63 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2746652440 May 21 12:26:09 PM PDT 24 May 21 12:26:37 PM PDT 24 15247302 ps
T131 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.703969169 May 21 12:26:14 PM PDT 24 May 21 12:26:54 PM PDT 24 72591459 ps
T954 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2793900468 May 21 12:25:49 PM PDT 24 May 21 12:26:14 PM PDT 24 980396087 ps
T135 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1636760468 May 21 12:25:54 PM PDT 24 May 21 12:26:17 PM PDT 24 289339089 ps
T955 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1846879230 May 21 12:25:39 PM PDT 24 May 21 12:26:01 PM PDT 24 39050564 ps
T956 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3301122944 May 21 12:25:42 PM PDT 24 May 21 12:26:05 PM PDT 24 612119854 ps
T99 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1071807822 May 21 12:25:40 PM PDT 24 May 21 12:26:02 PM PDT 24 14697600 ps
T957 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.4089132532 May 21 12:26:03 PM PDT 24 May 21 12:26:28 PM PDT 24 86888196 ps
T64 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.145475783 May 21 12:26:14 PM PDT 24 May 21 12:26:53 PM PDT 24 15087903 ps
T65 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.371152079 May 21 12:26:17 PM PDT 24 May 21 12:27:00 PM PDT 24 11401124 ps
T100 /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2712243847 May 21 12:25:26 PM PDT 24 May 21 12:25:43 PM PDT 24 23592319 ps
T958 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.427627503 May 21 12:26:13 PM PDT 24 May 21 12:26:52 PM PDT 24 300483905 ps
T959 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2128460759 May 21 12:25:43 PM PDT 24 May 21 12:26:05 PM PDT 24 29261304 ps
T960 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.132587353 May 21 12:26:25 PM PDT 24 May 21 12:27:18 PM PDT 24 291350024 ps
T961 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1399504426 May 21 12:25:50 PM PDT 24 May 21 12:26:19 PM PDT 24 359157501 ps
T101 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.453705538 May 21 12:25:46 PM PDT 24 May 21 12:26:07 PM PDT 24 21079373 ps
T69 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1230070738 May 21 12:25:53 PM PDT 24 May 21 12:26:14 PM PDT 24 23717568 ps
T962 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2420831805 May 21 12:26:13 PM PDT 24 May 21 12:26:50 PM PDT 24 25879900 ps
T102 /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.935381709 May 21 12:26:00 PM PDT 24 May 21 12:26:22 PM PDT 24 15350092 ps
T103 /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3601862595 May 21 12:25:41 PM PDT 24 May 21 12:26:03 PM PDT 24 58167189 ps
T963 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2167320002 May 21 12:25:56 PM PDT 24 May 21 12:26:21 PM PDT 24 393028384 ps
T964 /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.707076846 May 21 12:26:04 PM PDT 24 May 21 12:26:27 PM PDT 24 12633716 ps
T965 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3366312378 May 21 12:26:03 PM PDT 24 May 21 12:26:28 PM PDT 24 42418233 ps
T966 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1163178405 May 21 12:26:12 PM PDT 24 May 21 12:26:49 PM PDT 24 384714538 ps
T967 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3968982379 May 21 12:26:03 PM PDT 24 May 21 12:26:31 PM PDT 24 139980992 ps
T968 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.4078982847 May 21 12:25:38 PM PDT 24 May 21 12:26:00 PM PDT 24 38506443 ps
T133 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3685459924 May 21 12:26:07 PM PDT 24 May 21 12:26:36 PM PDT 24 296187887 ps
T969 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1030298496 May 21 12:25:40 PM PDT 24 May 21 12:26:04 PM PDT 24 362095448 ps
T970 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.775825705 May 21 12:26:02 PM PDT 24 May 21 12:26:27 PM PDT 24 1494314804 ps
T70 /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3107375982 May 21 12:26:13 PM PDT 24 May 21 12:27:41 PM PDT 24 58745675568 ps
T971 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.568098759 May 21 12:26:19 PM PDT 24 May 21 12:27:06 PM PDT 24 50184433 ps
T972 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3788467940 May 21 12:26:01 PM PDT 24 May 21 12:26:26 PM PDT 24 937986944 ps
T973 /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1572426339 May 21 12:26:24 PM PDT 24 May 21 12:27:16 PM PDT 24 252946049 ps
T974 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.991906139 May 21 12:25:51 PM PDT 24 May 21 12:26:13 PM PDT 24 74241581 ps
T71 /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2994641890 May 21 12:26:08 PM PDT 24 May 21 12:27:11 PM PDT 24 36841543104 ps
T975 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.823087700 May 21 12:26:09 PM PDT 24 May 21 12:26:40 PM PDT 24 119483483 ps
T976 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.254850298 May 21 12:26:03 PM PDT 24 May 21 12:26:26 PM PDT 24 40596205 ps
T977 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1386836489 May 21 12:25:48 PM PDT 24 May 21 12:26:13 PM PDT 24 1401546430 ps
T978 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3071521082 May 21 12:25:56 PM PDT 24 May 21 12:26:20 PM PDT 24 687693186 ps
T979 /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2002366263 May 21 12:26:00 PM PDT 24 May 21 12:26:21 PM PDT 24 15551003 ps
T980 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2163752531 May 21 12:26:11 PM PDT 24 May 21 12:26:43 PM PDT 24 15063647 ps
T981 /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1065150648 May 21 12:25:38 PM PDT 24 May 21 12:26:51 PM PDT 24 7309605172 ps
T136 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.892706173 May 21 12:26:00 PM PDT 24 May 21 12:26:23 PM PDT 24 700255203 ps
T982 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.49406589 May 21 12:26:23 PM PDT 24 May 21 12:27:16 PM PDT 24 1871917737 ps
T983 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2699822780 May 21 12:25:57 PM PDT 24 May 21 12:26:22 PM PDT 24 155937710 ps
T984 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.4171764869 May 21 12:26:05 PM PDT 24 May 21 12:26:31 PM PDT 24 21060328 ps
T985 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2097422402 May 21 12:25:59 PM PDT 24 May 21 12:26:22 PM PDT 24 49082867 ps
T986 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.368724418 May 21 12:25:57 PM PDT 24 May 21 12:26:22 PM PDT 24 359908197 ps
T72 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.4137786181 May 21 12:26:04 PM PDT 24 May 21 12:26:30 PM PDT 24 22766059 ps
T987 /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1112555166 May 21 12:26:09 PM PDT 24 May 21 12:26:37 PM PDT 24 19977630 ps
T73 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.368278196 May 21 12:25:51 PM PDT 24 May 21 12:26:12 PM PDT 24 19748310 ps
T74 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.73512722 May 21 12:26:16 PM PDT 24 May 21 12:26:58 PM PDT 24 25535934 ps
T988 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1647654301 May 21 12:25:59 PM PDT 24 May 21 12:26:24 PM PDT 24 1576361616 ps
T75 /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3006923187 May 21 12:25:45 PM PDT 24 May 21 12:26:33 PM PDT 24 3870591321 ps
T132 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.54233386 May 21 12:26:10 PM PDT 24 May 21 12:26:43 PM PDT 24 705443980 ps
T84 /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2226692627 May 21 12:26:08 PM PDT 24 May 21 12:27:02 PM PDT 24 7891647840 ps
T989 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2792398765 May 21 12:26:23 PM PDT 24 May 21 12:27:15 PM PDT 24 44951486 ps
T990 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.802972583 May 21 12:26:05 PM PDT 24 May 21 12:26:30 PM PDT 24 140975813 ps
T991 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2120549852 May 21 12:26:21 PM PDT 24 May 21 12:27:08 PM PDT 24 16086537 ps
T85 /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1809772886 May 21 12:25:56 PM PDT 24 May 21 12:26:45 PM PDT 24 4075393809 ps
T86 /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2612704944 May 21 12:25:42 PM PDT 24 May 21 12:26:30 PM PDT 24 3778966840 ps
T87 /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.4145690864 May 21 12:26:08 PM PDT 24 May 21 12:27:02 PM PDT 24 8200043728 ps
T992 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2041670625 May 21 12:25:38 PM PDT 24 May 21 12:26:00 PM PDT 24 236418171 ps
T88 /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1717840411 May 21 12:25:40 PM PDT 24 May 21 12:26:52 PM PDT 24 7300886678 ps
T993 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2915026684 May 21 12:25:39 PM PDT 24 May 21 12:26:01 PM PDT 24 15364131 ps
T994 /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.418075975 May 21 12:25:37 PM PDT 24 May 21 12:25:59 PM PDT 24 15340827 ps
T995 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2959569951 May 21 12:25:54 PM PDT 24 May 21 12:26:17 PM PDT 24 297878777 ps
T128 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2707792141 May 21 12:25:53 PM PDT 24 May 21 12:26:15 PM PDT 24 2607405855 ps
T996 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1095000377 May 21 12:25:50 PM PDT 24 May 21 12:26:11 PM PDT 24 33027873 ps
T997 /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3887260368 May 21 12:26:29 PM PDT 24 May 21 12:27:23 PM PDT 24 28769875 ps
T139 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2820366634 May 21 12:26:11 PM PDT 24 May 21 12:26:45 PM PDT 24 103150712 ps
T998 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1200333465 May 21 12:26:09 PM PDT 24 May 21 12:26:40 PM PDT 24 382889925 ps
T999 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1931993580 May 21 12:25:46 PM PDT 24 May 21 12:26:08 PM PDT 24 24548106 ps
T1000 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1109248284 May 21 12:25:46 PM PDT 24 May 21 12:26:12 PM PDT 24 871882929 ps
T129 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2928670621 May 21 12:26:05 PM PDT 24 May 21 12:26:33 PM PDT 24 340474261 ps
T1001 /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2574631518 May 21 12:25:28 PM PDT 24 May 21 12:25:39 PM PDT 24 129265545 ps
T1002 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3530314428 May 21 12:26:11 PM PDT 24 May 21 12:26:44 PM PDT 24 40664789 ps
T137 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3472067296 May 21 12:26:00 PM PDT 24 May 21 12:26:23 PM PDT 24 174700251 ps
T138 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2600490067 May 21 12:26:11 PM PDT 24 May 21 12:26:47 PM PDT 24 478464182 ps
T89 /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.4012560708 May 21 12:26:14 PM PDT 24 May 21 12:27:39 PM PDT 24 13605279131 ps
T1003 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3437987093 May 21 12:26:08 PM PDT 24 May 21 12:26:38 PM PDT 24 97840474 ps
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