Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	366532754	1			T1	288048		T2	267198		T3	492652
instr_valid_dis	316188604	1			T1	288048		T2	267198		T3	492652
instr_en	35975980	1			T5	35918		T6	325676		T28	40268

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	12697030	1			T6	71052		T29	32068		T8	131232
sram_ifetch_valid_disable	326474674	1			T1	288048		T2	267198		T3	492652
sram_ifetch_enable	27361050	1			T5	56256		T6	133712		T28	6710

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	366532754	1			T1	288048		T2	267198		T3	492652
hw_debug_en_valid_off	319460316	1			T1	288048		T2	267198		T3	492652
hw_debug_en_on	35486924	1			T6	82908		T28	9498		T29	49588

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	326474674	1			T1	288048		T2	267198		T3	492652
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	303367138	1			T1	288048		T2	267198		T3	492652
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	18260638	1			T5	16998		T6	120912		T28	40268
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4093836	1			T6	11628		T29	32068		T8	73290
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1311934	1			T46	52010		T60	20000		T21	61576
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2203258	1			T6	11628		T29	32068		T8	73290
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4575022	1			T6	40062		T8	57942		T46	74106
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	2261050	1			T46	74106		T60	65158		T139	70830
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1838744	1			T6	40062		T8	57942		T60	28444
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	16646166	1			T6	7194		T28	9498		T8	117582
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	8475941	1			T8	30054		T46	101888		T60	265982
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	7028437	1			T6	7194		T28	9498		T8	87528

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	10955568	1			T5	18920		T6	133712		T29	20660
lc_exec_en	14265736	1			T6	35652		T29	49588		T8	66588
valid_exec_dis	314382162	1			T1	288048		T2	267198		T3	492652
invalid_exec_dis	40058080	1			T5	56256		T6	204764		T28	6710