Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	153477251	1			T1	130818		T2	121525		T3	44738
triple_byte_access	3004132	1			T1	2464		T2	2400		T3	40542
halfword_access	4606378	1			T1	4061		T2	3725		T3	60330
byte_access	6432907	1			T1	5394		T2	4715		T3	80570
zero_access	1941414	1			T1	1287		T2	1234		T3	20146

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

84450675

1

T1

72174

T2

66532

T3

123602

auto[1]

85011407

1

T1

71850

T2

67067

T3

122724

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	76315080	1			T1	65553		T2	60561		T3	22327
auto[0]	triple_byte_access	1433996	1			T1	1241		T2	1188		T3	20295
auto[0]	halfword_access	2252384	1			T1	2026		T2	1832		T3	30127
auto[0]	byte_access	3293001	1			T1	2699		T2	2353		T3	40742
auto[0]	zero_access	1156214	1			T1	655		T2	598		T3	10111
auto[1]	word_access	77162171	1			T1	65265		T2	60964		T3	22411
auto[1]	triple_byte_access	1570136	1			T1	1223		T2	1212		T3	20247
auto[1]	halfword_access	2353994	1			T1	2035		T2	1893		T3	30203
auto[1]	byte_access	3139906	1			T1	2695		T2	2362		T3	39828
auto[1]	zero_access	785200	1			T1	632		T2	636		T3	10035