Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	204322030	1			T1	6826		T3	19948		T4	2322
instr_valid_dis	188836293	1			T1	6826		T3	19948		T4	2322
instr_en	10766076	1			T24	2190		T25	166082		T41	81610

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	5796298	1			T19	22668		T25	21704		T26	94766
sram_ifetch_valid_disable	187905756	1			T1	6826		T3	19948		T4	2322
sram_ifetch_enable	10619976	1			T19	188170		T24	43252		T25	96498

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	204322030	1			T1	6826		T3	19948		T4	2322
hw_debug_en_valid_off	187798292	1			T1	6826		T3	19948		T4	2322
hw_debug_en_on	11207956	1			T19	130458		T24	11018		T25	142054

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	187905756	1			T1	6826		T3	19948		T4	2322
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	181782255	1			T1	6826		T3	19948		T4	2322
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	4408168	1			T25	103768		T41	20000		T51	93046
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	2480804	1			T19	8934		T25	10802		T26	64986
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1077312	1			T26	64986		T41	37534		T42	31038
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1101644	1			T25	3334		T41	19850		T51	48200
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	2245698	1			T19	13734		T25	64		T26	20000
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	873294	1			T25	64		T26	20000		T41	16278
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	909274	1			T41	33834		T51	13766		T20	24782
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	4287130	1			T19	69038		T25	55480		T26	63620
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	1801602	1			T26	63620		T41	21038		T42	110860
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	1826912	1			T25	35480		T41	20000		T51	26062

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	3910632	1			T24	2190		T25	48142		T41	7926
lc_exec_en	4675128	1			T19	47686		T24	11018		T25	86510
valid_exec_dis	185979994	1			T1	6826		T3	19948		T4	2322
invalid_exec_dis	16416274	1			T19	210838		T24	43252		T25	118202