Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

---

Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	81397209	1			T1	192		T3	1837		T4	210
triple_byte_access	2462531	1			T1	5		T3	1622		T4	193
halfword_access	3790789	1			T1	8		T3	2454		T4	289
byte_access	5327909	1			T1	8		T3	3253		T4	366
zero_access	1645601	1			T1	1		T3	808		T4	103

---

Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46618717

1

T1

109

T3

4948

T4

592

auto[1]

48005322

1

T1

105

T3

5026

T4

569

---

Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	39913588	1			T1	96		T3	916		T4	112
auto[0]	triple_byte_access	1159814	1			T1	5		T3	817		T4	95
auto[0]	halfword_access	1834120	1			T1	4		T3	1216		T4	165
auto[0]	byte_access	2718283	1			T1	3		T3	1592		T4	178
auto[0]	zero_access	992912	1			T1	1		T3	407		T4	42
auto[1]	word_access	41483621	1			T1	96		T3	921		T4	98
auto[1]	triple_byte_access	1302717	1			T3	805		T4	98		T11	653
auto[1]	halfword_access	1956669	1			T1	4		T3	1238		T4	124
auto[1]	byte_access	2609626	1			T1	5		T3	1661		T4	188
auto[1]	zero_access	652689	1			T3	401		T4	61		T11	320