Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	201018730	1			T1	11236		T2	16692		T3	17944
instr_valid_dis	183086888	1			T1	11236		T2	16692		T3	17944
instr_en	13632213	1			T12	92056		T14	157980		T33	222610

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	4925008	1			T12	19446		T14	64030		T33	51222
sram_ifetch_valid_disable	185028750	1			T1	11236		T2	16692		T3	17944
sram_ifetch_enable	11064972	1			T12	37664		T14	78640		T33	392320

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	201018730	1			T1	11236		T2	16692		T3	17944
hw_debug_en_valid_off	184283766	1			T1	11236		T2	16692		T3	17944
hw_debug_en_on	10685382	1			T12	49128		T14	116648		T33	251638

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	185028750	1			T1	11236		T2	16692		T3	17944
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	177354230	1			T1	11236		T2	16692		T3	17944
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	5750429	1			T12	34946		T14	45964		T33	51160
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	1670326	1			T12	19446		T14	13204		T33	32230
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	489300	1			T48	8162		T129	20070		T152	2622
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	966332	1			T12	19446		T14	13204		T33	32230
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	1701048	1			T33	18992		T55	39322		T152	57986
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	560724	1			T55	39322		T152	37986		T155	22810
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	886944	1			T155	760		T81	94714		T82	14190
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	5035500	1			T12	11554		T14	98644		T33	94904
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	1947722	1			T14	60472		T33	63744		T55	44248
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	2519906	1			T12	11554		T14	27966		T33	31160

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	5339818	1			T12	37664		T14	47986		T33	139220
lc_exec_en	3948834	1			T12	37574		T14	18004		T33	137742
valid_exec_dis	182199732	1			T1	11236		T2	16692		T3	17944
invalid_exec_dis	15989980	1			T12	57110		T14	142670		T33	443542