Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	80434746	1			T1	5618		T2	1578		T3	8972
triple_byte_access	2351960	1			T2	1309		T5	36599		T7	41
halfword_access	3618945	1			T2	2061		T5	55294		T7	64
byte_access	5093495	1			T2	2735		T5	73476		T7	94
zero_access	1584140	1			T2	663		T5	18514		T7	21

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45965302

1

T1

2777

T2

4125

T3

4393

auto[1]

47117984

1

T1

2841

T2

4221

T3

4579

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	39542576	1			T1	2777		T2	804		T3	4393
auto[0]	triple_byte_access	1106005	1			T2	618		T5	18381		T7	15
auto[0]	halfword_access	1750028	1			T2	1017		T5	27546		T7	31
auto[0]	byte_access	2605346	1			T2	1353		T5	36743		T7	46
auto[0]	zero_access	961347	1			T2	333		T5	9294		T7	11
auto[1]	word_access	40892170	1			T1	2841		T2	774		T3	4579
auto[1]	triple_byte_access	1245955	1			T2	691		T5	18218		T7	26
auto[1]	halfword_access	1868917	1			T2	1044		T5	27748		T7	33
auto[1]	byte_access	2488149	1			T2	1382		T5	36733		T7	48
auto[1]	zero_access	622793	1			T2	330		T5	9220		T7	10