Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	352259886	1			T1	93874		T2	5020		T3	61012
instr_valid_dis	311100409	1			T1	93874		T2	5020		T3	61012
instr_en	30002858	1			T5	405104		T30	260994		T7	198454

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	12355409	1			T5	301588		T30	30850		T7	61018
sram_ifetch_valid_disable	307238581	1			T1	93874		T2	5020		T3	61012
sram_ifetch_enable	32665896	1			T5	108726		T30	219220		T7	150388

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	352259886	1			T1	93874		T2	5020		T3	61012
hw_debug_en_valid_off	313188267	1			T1	93874		T2	5020		T3	61012
hw_debug_en_on	26196753	1			T5	101504		T30	269092		T7	185636

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	307238581	1			T1	93874		T2	5020		T3	61012
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	292436844	1			T1	93874		T2	5020		T3	61012
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	11187138	1			T5	117806		T30	116502		T7	70656
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	5919115	1			T5	301588		T7	23342		T25	100988
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	3193427	1			T5	36164		T25	44330		T45	12494
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2066518	1			T5	265424		T7	23342		T25	56658
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4210578	1			T30	30850		T7	37676		T25	207734
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1852976	1			T30	21882		T7	23000		T25	113314
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1674018	1			T30	8968		T7	14676		T25	94420
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	9484061	1			T5	87236		T30	56234		T7	91446
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	4494656	1			T5	28426		T30	33010		T7	6340
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3488458	1			T5	58810		T30	23224		T7	42790

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	13984132	1			T5	21874		T30	135524		T7	89780
lc_exec_en	12502114	1			T5	14268		T30	182008		T7	56514
valid_exec_dis	305994572	1			T1	93874		T2	5020		T3	61012
invalid_exec_dis	45021305	1			T5	410314		T30	250070		T7	211406