| Name |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.792079428 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3260976981 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1190880867 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3001307170 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2840180150 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.142690582 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3017999128 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.422664177 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3216324407 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.548364080 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1002098268 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3180673361 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.851611071 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3692456079 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.642012255 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3819838851 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1277255422 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.456026977 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1618866326 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1772850082 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3478653940 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1150636376 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.53449202 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1436068663 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2972692767 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.4099579160 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.782619765 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.861239471 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.4232771256 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2778084792 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.964175781 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2052201702 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2763975222 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3294954461 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.877542615 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.987758586 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1894484118 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2941754319 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.683710957 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.4154140435 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.269820729 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2296601883 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1105631562 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3890321183 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3783615282 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.4089820508 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2445472148 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3581672348 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.79406056 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1594058265 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.622715812 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.122543728 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.403201610 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1217435994 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3761138489 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.4204952405 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1471964513 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.175454409 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1984192243 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3207861050 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2677087092 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1071682174 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2792367615 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.892481895 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.912080131 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2897302525 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2888780859 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1460374387 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.4057499863 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.780234096 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.521618846 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3722781994 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.471906123 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2215418253 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2680270222 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1170032484 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.112128569 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2049057086 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1379153151 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.4253797072 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.530355743 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3012185645 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2887825326 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2118659264 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1596649526 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.781026636 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.911224708 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.4136153495 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3492487348 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1326794815 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3390234471 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.479346448 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3475563122 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1316140914 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2799050778 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1427001019 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1034504651 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1664693609 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3152090954 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2909843874 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.679476830 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.818685562 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.4142390708 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1415985140 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2371580400 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3293459224 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3793138316 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1912858825 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2941727140 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.932016220 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1841843813 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2572661053 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1655666118 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1339494932 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.4255778698 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.4172291557 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.386743987 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1989904819 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1910718884 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2559434724 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2050276278 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1265446543 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.4063576699 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1876514719 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.4101213810 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1291142141 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3995654487 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.4039445058 |
| /workspace/coverage/default/0.sram_ctrl_access_during_key_req.2751246181 |
| /workspace/coverage/default/0.sram_ctrl_alert_test.4132592376 |
| /workspace/coverage/default/0.sram_ctrl_bijection.1273913841 |
| /workspace/coverage/default/0.sram_ctrl_executable.2990671928 |
| /workspace/coverage/default/0.sram_ctrl_lc_escalation.3796703702 |
| /workspace/coverage/default/0.sram_ctrl_max_throughput.511539895 |
| /workspace/coverage/default/0.sram_ctrl_mem_partial_access.906879240 |
| /workspace/coverage/default/0.sram_ctrl_mem_walk.2335826175 |
| /workspace/coverage/default/0.sram_ctrl_multiple_keys.4000486858 |
| /workspace/coverage/default/0.sram_ctrl_partial_access.3167528189 |
| /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1286020864 |
| /workspace/coverage/default/0.sram_ctrl_ram_cfg.263240686 |
| /workspace/coverage/default/0.sram_ctrl_regwen.2313814237 |
| /workspace/coverage/default/0.sram_ctrl_sec_cm.2179629520 |
| /workspace/coverage/default/0.sram_ctrl_smoke.3898779606 |
| /workspace/coverage/default/0.sram_ctrl_stress_all.338446899 |
| /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.3931910314 |
| /workspace/coverage/default/0.sram_ctrl_stress_pipeline.526211591 |
| /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.3641924101 |
| /workspace/coverage/default/1.sram_ctrl_access_during_key_req.1065320555 |
| /workspace/coverage/default/1.sram_ctrl_alert_test.1623113359 |
| /workspace/coverage/default/1.sram_ctrl_bijection.2077372219 |
| /workspace/coverage/default/1.sram_ctrl_executable.1193064921 |
| /workspace/coverage/default/1.sram_ctrl_lc_escalation.3097122222 |
| /workspace/coverage/default/1.sram_ctrl_max_throughput.816919331 |
| /workspace/coverage/default/1.sram_ctrl_mem_partial_access.453856169 |
| /workspace/coverage/default/1.sram_ctrl_mem_walk.1380500710 |
| /workspace/coverage/default/1.sram_ctrl_multiple_keys.60921422 |
| /workspace/coverage/default/1.sram_ctrl_partial_access.2137195668 |
| /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.1553510070 |
| /workspace/coverage/default/1.sram_ctrl_ram_cfg.3495284058 |
| /workspace/coverage/default/1.sram_ctrl_regwen.3418951966 |
| /workspace/coverage/default/1.sram_ctrl_sec_cm.3336346628 |
| /workspace/coverage/default/1.sram_ctrl_smoke.2614146235 |
| /workspace/coverage/default/1.sram_ctrl_stress_all.4137461008 |
| /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.119185522 |
| /workspace/coverage/default/1.sram_ctrl_stress_pipeline.50635652 |
| /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.2126128774 |
| /workspace/coverage/default/10.sram_ctrl_access_during_key_req.2583493643 |
| /workspace/coverage/default/10.sram_ctrl_alert_test.2188248574 |
| /workspace/coverage/default/10.sram_ctrl_bijection.523380676 |
| /workspace/coverage/default/10.sram_ctrl_lc_escalation.1888505537 |
| /workspace/coverage/default/10.sram_ctrl_max_throughput.2402018067 |
| /workspace/coverage/default/10.sram_ctrl_mem_partial_access.2566190805 |
| /workspace/coverage/default/10.sram_ctrl_mem_walk.3709184310 |
| /workspace/coverage/default/10.sram_ctrl_multiple_keys.169095510 |
| /workspace/coverage/default/10.sram_ctrl_partial_access.2777292854 |
| /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.1867186018 |
| /workspace/coverage/default/10.sram_ctrl_ram_cfg.1469011558 |
| /workspace/coverage/default/10.sram_ctrl_regwen.2660959843 |
| /workspace/coverage/default/10.sram_ctrl_smoke.2149131655 |
| /workspace/coverage/default/10.sram_ctrl_stress_all.1831624932 |
| /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3929007397 |
| /workspace/coverage/default/10.sram_ctrl_stress_pipeline.641127595 |
| /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2178679784 |
| /workspace/coverage/default/11.sram_ctrl_access_during_key_req.392247667 |
| /workspace/coverage/default/11.sram_ctrl_alert_test.946644305 |
| /workspace/coverage/default/11.sram_ctrl_bijection.2694546509 |
| /workspace/coverage/default/11.sram_ctrl_executable.4213710448 |
| /workspace/coverage/default/11.sram_ctrl_lc_escalation.1849036347 |
| /workspace/coverage/default/11.sram_ctrl_max_throughput.2864162109 |
| /workspace/coverage/default/11.sram_ctrl_mem_partial_access.986928794 |
| /workspace/coverage/default/11.sram_ctrl_mem_walk.214518050 |
| /workspace/coverage/default/11.sram_ctrl_multiple_keys.2494291962 |
| /workspace/coverage/default/11.sram_ctrl_partial_access.2740554476 |
| /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.2176672481 |
| /workspace/coverage/default/11.sram_ctrl_ram_cfg.3291190059 |
| /workspace/coverage/default/11.sram_ctrl_regwen.172211836 |
| /workspace/coverage/default/11.sram_ctrl_smoke.2254541044 |
| /workspace/coverage/default/11.sram_ctrl_stress_all.4177101439 |
| /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1691746928 |
| /workspace/coverage/default/11.sram_ctrl_stress_pipeline.3816989861 |
| /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.2693742988 |
| /workspace/coverage/default/12.sram_ctrl_access_during_key_req.217652391 |
| /workspace/coverage/default/12.sram_ctrl_alert_test.324784501 |
| /workspace/coverage/default/12.sram_ctrl_bijection.2167191126 |
| /workspace/coverage/default/12.sram_ctrl_executable.2410491758 |
| /workspace/coverage/default/12.sram_ctrl_lc_escalation.2763472990 |
| /workspace/coverage/default/12.sram_ctrl_max_throughput.3535726737 |
| /workspace/coverage/default/12.sram_ctrl_mem_partial_access.3835458318 |
| /workspace/coverage/default/12.sram_ctrl_mem_walk.850846571 |
| /workspace/coverage/default/12.sram_ctrl_multiple_keys.4218960571 |
| /workspace/coverage/default/12.sram_ctrl_partial_access.278223107 |
| /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.118066424 |
| /workspace/coverage/default/12.sram_ctrl_ram_cfg.2550746062 |
| /workspace/coverage/default/12.sram_ctrl_regwen.2978540733 |
| /workspace/coverage/default/12.sram_ctrl_smoke.4065475199 |
| /workspace/coverage/default/12.sram_ctrl_stress_all.914898544 |
| /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.1440111118 |
| /workspace/coverage/default/12.sram_ctrl_stress_pipeline.3040570759 |
| /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.1537642978 |
| /workspace/coverage/default/13.sram_ctrl_access_during_key_req.4000008588 |
| /workspace/coverage/default/13.sram_ctrl_alert_test.151496356 |
| /workspace/coverage/default/13.sram_ctrl_executable.3941522589 |
| /workspace/coverage/default/13.sram_ctrl_lc_escalation.1189764308 |
| /workspace/coverage/default/13.sram_ctrl_max_throughput.213400779 |
| /workspace/coverage/default/13.sram_ctrl_mem_partial_access.3099305062 |
| /workspace/coverage/default/13.sram_ctrl_mem_walk.3043699248 |
| /workspace/coverage/default/13.sram_ctrl_multiple_keys.284762410 |
| /workspace/coverage/default/13.sram_ctrl_partial_access.1535033460 |
| /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.3888046730 |
| /workspace/coverage/default/13.sram_ctrl_ram_cfg.1023064948 |
| /workspace/coverage/default/13.sram_ctrl_regwen.3676794182 |
| /workspace/coverage/default/13.sram_ctrl_smoke.575484060 |
| /workspace/coverage/default/13.sram_ctrl_stress_all.3108529385 |
| /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.2510824727 |
| /workspace/coverage/default/13.sram_ctrl_stress_pipeline.3916059857 |
| /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.395832993 |
| /workspace/coverage/default/14.sram_ctrl_access_during_key_req.428774036 |
| /workspace/coverage/default/14.sram_ctrl_bijection.3836289023 |
| /workspace/coverage/default/14.sram_ctrl_executable.2693033957 |
| /workspace/coverage/default/14.sram_ctrl_lc_escalation.1444793949 |
| /workspace/coverage/default/14.sram_ctrl_max_throughput.478732448 |
| /workspace/coverage/default/14.sram_ctrl_mem_partial_access.3532070441 |
| /workspace/coverage/default/14.sram_ctrl_mem_walk.1673026481 |
| /workspace/coverage/default/14.sram_ctrl_multiple_keys.2912586935 |
| /workspace/coverage/default/14.sram_ctrl_partial_access.1587811657 |
| /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.2019229557 |
| /workspace/coverage/default/14.sram_ctrl_ram_cfg.104006305 |
| /workspace/coverage/default/14.sram_ctrl_regwen.3559082668 |
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| /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.3595119714 |
| /workspace/coverage/default/43.sram_ctrl_access_during_key_req.1148572153 |
| /workspace/coverage/default/43.sram_ctrl_alert_test.2783069400 |
| /workspace/coverage/default/43.sram_ctrl_bijection.127052089 |
| /workspace/coverage/default/43.sram_ctrl_executable.843257982 |
| /workspace/coverage/default/43.sram_ctrl_lc_escalation.2393852158 |
| /workspace/coverage/default/43.sram_ctrl_max_throughput.3580190199 |
| /workspace/coverage/default/43.sram_ctrl_mem_walk.3150959858 |
| /workspace/coverage/default/43.sram_ctrl_multiple_keys.2502676280 |
| /workspace/coverage/default/43.sram_ctrl_partial_access.1495489377 |
| /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.4129200205 |
| /workspace/coverage/default/43.sram_ctrl_ram_cfg.4121472026 |
| /workspace/coverage/default/43.sram_ctrl_regwen.1717785165 |
| /workspace/coverage/default/43.sram_ctrl_smoke.268949664 |
| /workspace/coverage/default/43.sram_ctrl_stress_all.2852245813 |
| /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.1301258467 |
| /workspace/coverage/default/43.sram_ctrl_stress_pipeline.802882481 |
| /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.1127571341 |
| /workspace/coverage/default/44.sram_ctrl_access_during_key_req.582400362 |
| /workspace/coverage/default/44.sram_ctrl_alert_test.3895028318 |
| /workspace/coverage/default/44.sram_ctrl_bijection.1502695414 |
| /workspace/coverage/default/44.sram_ctrl_executable.11348865 |
| /workspace/coverage/default/44.sram_ctrl_lc_escalation.3315241195 |
| /workspace/coverage/default/44.sram_ctrl_max_throughput.3909276905 |
| /workspace/coverage/default/44.sram_ctrl_mem_partial_access.3169428328 |
| /workspace/coverage/default/44.sram_ctrl_mem_walk.4127250615 |
| /workspace/coverage/default/44.sram_ctrl_multiple_keys.1828485551 |
| /workspace/coverage/default/44.sram_ctrl_partial_access.3461941322 |
| /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.2842909790 |
| /workspace/coverage/default/44.sram_ctrl_ram_cfg.694612037 |
| /workspace/coverage/default/44.sram_ctrl_regwen.2706909279 |
| /workspace/coverage/default/44.sram_ctrl_smoke.2101139222 |
| /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.1059953486 |
| /workspace/coverage/default/44.sram_ctrl_stress_pipeline.3707035128 |
| /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.795874911 |
| /workspace/coverage/default/45.sram_ctrl_access_during_key_req.1362137750 |
| /workspace/coverage/default/45.sram_ctrl_alert_test.3111780633 |
| /workspace/coverage/default/45.sram_ctrl_bijection.3480395962 |
| /workspace/coverage/default/45.sram_ctrl_executable.261173770 |
| /workspace/coverage/default/45.sram_ctrl_lc_escalation.714764480 |
| /workspace/coverage/default/45.sram_ctrl_max_throughput.46748529 |
| /workspace/coverage/default/45.sram_ctrl_mem_partial_access.1781554948 |
| /workspace/coverage/default/45.sram_ctrl_mem_walk.1025717721 |
| /workspace/coverage/default/45.sram_ctrl_multiple_keys.202509823 |
| /workspace/coverage/default/45.sram_ctrl_partial_access.1248990269 |
| /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.1807297782 |
| /workspace/coverage/default/45.sram_ctrl_ram_cfg.1622313489 |
| /workspace/coverage/default/45.sram_ctrl_regwen.4238022952 |
| /workspace/coverage/default/45.sram_ctrl_smoke.188726406 |
| /workspace/coverage/default/45.sram_ctrl_stress_all.2704866902 |
| /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1614680859 |
| /workspace/coverage/default/45.sram_ctrl_stress_pipeline.3264029721 |
| /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.43298321 |
| /workspace/coverage/default/46.sram_ctrl_access_during_key_req.126555844 |
| /workspace/coverage/default/46.sram_ctrl_alert_test.1414201154 |
| /workspace/coverage/default/46.sram_ctrl_bijection.2448565725 |
| /workspace/coverage/default/46.sram_ctrl_executable.2181062132 |
| /workspace/coverage/default/46.sram_ctrl_lc_escalation.3058707516 |
| /workspace/coverage/default/46.sram_ctrl_max_throughput.1369936994 |
| /workspace/coverage/default/46.sram_ctrl_mem_partial_access.3196626448 |
| /workspace/coverage/default/46.sram_ctrl_mem_walk.215136475 |
| /workspace/coverage/default/46.sram_ctrl_multiple_keys.3159259349 |
| /workspace/coverage/default/46.sram_ctrl_partial_access.529107426 |
| /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.3020335837 |
| /workspace/coverage/default/46.sram_ctrl_ram_cfg.2976613614 |
| /workspace/coverage/default/46.sram_ctrl_regwen.456850763 |
| /workspace/coverage/default/46.sram_ctrl_smoke.1016769642 |
| /workspace/coverage/default/46.sram_ctrl_stress_pipeline.3037425706 |
| /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.1061956572 |
| /workspace/coverage/default/47.sram_ctrl_access_during_key_req.2075363917 |
| /workspace/coverage/default/47.sram_ctrl_alert_test.608105485 |
| /workspace/coverage/default/47.sram_ctrl_bijection.137503131 |
| /workspace/coverage/default/47.sram_ctrl_executable.1778964472 |
| /workspace/coverage/default/47.sram_ctrl_lc_escalation.4196362918 |
| /workspace/coverage/default/47.sram_ctrl_max_throughput.3379489607 |
| /workspace/coverage/default/47.sram_ctrl_mem_partial_access.1783878766 |
| /workspace/coverage/default/47.sram_ctrl_mem_walk.1701150119 |
| /workspace/coverage/default/47.sram_ctrl_multiple_keys.3070432598 |
| /workspace/coverage/default/47.sram_ctrl_partial_access.2126438322 |
| /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2678823910 |
| /workspace/coverage/default/47.sram_ctrl_ram_cfg.3730641055 |
| /workspace/coverage/default/47.sram_ctrl_regwen.231661534 |
| /workspace/coverage/default/47.sram_ctrl_smoke.421078461 |
| /workspace/coverage/default/47.sram_ctrl_stress_all.1192100467 |
| /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.3989282882 |
| /workspace/coverage/default/47.sram_ctrl_stress_pipeline.2942207321 |
| /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.1764935689 |
| /workspace/coverage/default/48.sram_ctrl_access_during_key_req.1697070597 |
| /workspace/coverage/default/48.sram_ctrl_alert_test.639440340 |
| /workspace/coverage/default/48.sram_ctrl_bijection.2136992479 |
| /workspace/coverage/default/48.sram_ctrl_executable.1591065294 |
| /workspace/coverage/default/48.sram_ctrl_lc_escalation.3223201714 |
| /workspace/coverage/default/48.sram_ctrl_max_throughput.161763336 |
| /workspace/coverage/default/48.sram_ctrl_mem_partial_access.2868393244 |
| /workspace/coverage/default/48.sram_ctrl_mem_walk.725341206 |
| /workspace/coverage/default/48.sram_ctrl_multiple_keys.262558613 |
| /workspace/coverage/default/48.sram_ctrl_partial_access.427190823 |
| /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.2622417125 |
| /workspace/coverage/default/48.sram_ctrl_ram_cfg.787152700 |
| /workspace/coverage/default/48.sram_ctrl_regwen.1958701970 |
| /workspace/coverage/default/48.sram_ctrl_smoke.766504572 |
| /workspace/coverage/default/48.sram_ctrl_stress_all.3480131634 |
| /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1142433593 |
| /workspace/coverage/default/48.sram_ctrl_stress_pipeline.2230646988 |
| /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.3468939352 |
| /workspace/coverage/default/49.sram_ctrl_access_during_key_req.3664632002 |
| /workspace/coverage/default/49.sram_ctrl_alert_test.351690981 |
| /workspace/coverage/default/49.sram_ctrl_bijection.207285101 |
| /workspace/coverage/default/49.sram_ctrl_executable.2304596603 |
| /workspace/coverage/default/49.sram_ctrl_lc_escalation.3069677923 |
| /workspace/coverage/default/49.sram_ctrl_max_throughput.2608861852 |
| /workspace/coverage/default/49.sram_ctrl_mem_partial_access.2181551670 |
| /workspace/coverage/default/49.sram_ctrl_mem_walk.3976763946 |
| /workspace/coverage/default/49.sram_ctrl_multiple_keys.1070749383 |
| /workspace/coverage/default/49.sram_ctrl_partial_access.2863818783 |
| /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.4077547852 |
| /workspace/coverage/default/49.sram_ctrl_ram_cfg.2295439478 |
| /workspace/coverage/default/49.sram_ctrl_regwen.1430675886 |
| /workspace/coverage/default/49.sram_ctrl_smoke.3736379756 |
| /workspace/coverage/default/49.sram_ctrl_stress_all.1756211546 |
| /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.379358375 |
| /workspace/coverage/default/49.sram_ctrl_stress_pipeline.3523935724 |
| /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.721674731 |
| /workspace/coverage/default/5.sram_ctrl_access_during_key_req.1898381957 |
| /workspace/coverage/default/5.sram_ctrl_alert_test.1319095798 |
| /workspace/coverage/default/5.sram_ctrl_bijection.2917431824 |
| /workspace/coverage/default/5.sram_ctrl_executable.3041018326 |
| /workspace/coverage/default/5.sram_ctrl_lc_escalation.2574798641 |
| /workspace/coverage/default/5.sram_ctrl_max_throughput.641582428 |
| /workspace/coverage/default/5.sram_ctrl_mem_partial_access.570210902 |
| /workspace/coverage/default/5.sram_ctrl_mem_walk.910405509 |
| /workspace/coverage/default/5.sram_ctrl_multiple_keys.492657517 |
| /workspace/coverage/default/5.sram_ctrl_partial_access.1513869565 |
| /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.518386169 |
| /workspace/coverage/default/5.sram_ctrl_ram_cfg.294503872 |
| /workspace/coverage/default/5.sram_ctrl_regwen.94558495 |
| /workspace/coverage/default/5.sram_ctrl_smoke.4014832241 |
| /workspace/coverage/default/5.sram_ctrl_stress_all.284357749 |
| /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2257830758 |
| /workspace/coverage/default/5.sram_ctrl_stress_pipeline.4265722257 |
| /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.3810546008 |
| /workspace/coverage/default/6.sram_ctrl_access_during_key_req.3769196165 |
| /workspace/coverage/default/6.sram_ctrl_alert_test.1921754285 |
| /workspace/coverage/default/6.sram_ctrl_bijection.582718137 |
| /workspace/coverage/default/6.sram_ctrl_executable.2055992083 |
| /workspace/coverage/default/6.sram_ctrl_lc_escalation.949234567 |
| /workspace/coverage/default/6.sram_ctrl_max_throughput.1909050017 |
| /workspace/coverage/default/6.sram_ctrl_mem_partial_access.3499896926 |
| /workspace/coverage/default/6.sram_ctrl_mem_walk.2300328309 |
| /workspace/coverage/default/6.sram_ctrl_multiple_keys.1320840530 |
| /workspace/coverage/default/6.sram_ctrl_partial_access.4070640178 |
| /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.34996074 |
| /workspace/coverage/default/6.sram_ctrl_ram_cfg.2232189547 |
| /workspace/coverage/default/6.sram_ctrl_regwen.2004483835 |
| /workspace/coverage/default/6.sram_ctrl_smoke.1748280582 |
| /workspace/coverage/default/6.sram_ctrl_stress_all.3093622666 |
| /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.283746314 |
| /workspace/coverage/default/6.sram_ctrl_stress_pipeline.2700615048 |
| /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.3055886212 |
| /workspace/coverage/default/7.sram_ctrl_access_during_key_req.3509984639 |
| /workspace/coverage/default/7.sram_ctrl_alert_test.1428238355 |
| /workspace/coverage/default/7.sram_ctrl_bijection.4124520130 |
| /workspace/coverage/default/7.sram_ctrl_executable.2066157178 |
| /workspace/coverage/default/7.sram_ctrl_lc_escalation.4131482480 |
| /workspace/coverage/default/7.sram_ctrl_max_throughput.2064447425 |
| /workspace/coverage/default/7.sram_ctrl_mem_partial_access.2292915473 |
| /workspace/coverage/default/7.sram_ctrl_mem_walk.4034518313 |
| /workspace/coverage/default/7.sram_ctrl_multiple_keys.3415520370 |
| /workspace/coverage/default/7.sram_ctrl_partial_access.3986608965 |
| /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.3448951242 |
| /workspace/coverage/default/7.sram_ctrl_ram_cfg.686750393 |
| /workspace/coverage/default/7.sram_ctrl_regwen.4064566903 |
| /workspace/coverage/default/7.sram_ctrl_smoke.1769679125 |
| /workspace/coverage/default/7.sram_ctrl_stress_all.2243727180 |
| /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3913479133 |
| /workspace/coverage/default/7.sram_ctrl_stress_pipeline.3503740828 |
| /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.441939931 |
| /workspace/coverage/default/8.sram_ctrl_access_during_key_req.2980092157 |
| /workspace/coverage/default/8.sram_ctrl_alert_test.1247143409 |
| /workspace/coverage/default/8.sram_ctrl_bijection.2211863826 |
| /workspace/coverage/default/8.sram_ctrl_executable.4073886134 |
| /workspace/coverage/default/8.sram_ctrl_lc_escalation.2214657784 |
| /workspace/coverage/default/8.sram_ctrl_max_throughput.3357551721 |
| /workspace/coverage/default/8.sram_ctrl_mem_partial_access.1176368636 |
| /workspace/coverage/default/8.sram_ctrl_mem_walk.1611108967 |
| /workspace/coverage/default/8.sram_ctrl_multiple_keys.2301921635 |
| /workspace/coverage/default/8.sram_ctrl_partial_access.943751560 |
| /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.381666630 |
| /workspace/coverage/default/8.sram_ctrl_ram_cfg.37974283 |
| /workspace/coverage/default/8.sram_ctrl_regwen.2699079717 |
| /workspace/coverage/default/8.sram_ctrl_smoke.647248603 |
| /workspace/coverage/default/8.sram_ctrl_stress_all.1995745425 |
| /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2571104601 |
| /workspace/coverage/default/8.sram_ctrl_stress_pipeline.3420587321 |
| /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.1690433366 |
| /workspace/coverage/default/9.sram_ctrl_access_during_key_req.4150131046 |
| /workspace/coverage/default/9.sram_ctrl_alert_test.3452727111 |
| /workspace/coverage/default/9.sram_ctrl_bijection.4204473391 |
| /workspace/coverage/default/9.sram_ctrl_executable.1932101555 |
| /workspace/coverage/default/9.sram_ctrl_lc_escalation.2603926539 |
| /workspace/coverage/default/9.sram_ctrl_max_throughput.991120666 |
| /workspace/coverage/default/9.sram_ctrl_mem_partial_access.2846048724 |
| /workspace/coverage/default/9.sram_ctrl_mem_walk.1192643114 |
| /workspace/coverage/default/9.sram_ctrl_multiple_keys.3884879943 |
| /workspace/coverage/default/9.sram_ctrl_partial_access.3207862649 |
| /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.2939701432 |
| /workspace/coverage/default/9.sram_ctrl_ram_cfg.1005154655 |
| /workspace/coverage/default/9.sram_ctrl_regwen.2903030587 |
| /workspace/coverage/default/9.sram_ctrl_smoke.4109121759 |
| /workspace/coverage/default/9.sram_ctrl_stress_all.1330931511 |
| /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.378450822 |
| /workspace/coverage/default/9.sram_ctrl_stress_pipeline.2585198147 |
| /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.337857513 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
| T1 |
/workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.1012797320 |
|
|
Jun 05 03:59:05 PM PDT 24 |
Jun 05 04:00:39 PM PDT 24 |
10368977787 ps |
| T2 |
/workspace/coverage/default/9.sram_ctrl_partial_access.3207862649 |
|
|
Jun 05 03:58:44 PM PDT 24 |
Jun 05 03:58:52 PM PDT 24 |
1637158280 ps |
| T3 |
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.1500056149 |
|
|
Jun 05 04:01:37 PM PDT 24 |
Jun 05 04:03:04 PM PDT 24 |
2884675430 ps |
| T4 |
/workspace/coverage/default/18.sram_ctrl_smoke.4256615296 |
|
|
Jun 05 03:59:01 PM PDT 24 |
Jun 05 03:59:17 PM PDT 24 |
1084791755 ps |
| T8 |
/workspace/coverage/default/13.sram_ctrl_max_throughput.213400779 |
|
|
Jun 05 03:58:51 PM PDT 24 |
Jun 05 03:59:25 PM PDT 24 |
749800796 ps |
| T9 |
/workspace/coverage/default/11.sram_ctrl_ram_cfg.3291190059 |
|
|
Jun 05 03:58:45 PM PDT 24 |
Jun 05 03:58:50 PM PDT 24 |
1407999243 ps |
| T10 |
/workspace/coverage/default/27.sram_ctrl_mem_partial_access.2203081242 |
|
|
Jun 05 03:59:55 PM PDT 24 |
Jun 05 04:02:25 PM PDT 24 |
4490598695 ps |
| T5 |
/workspace/coverage/default/44.sram_ctrl_stress_all.786349929 |
|
|
Jun 05 04:01:46 PM PDT 24 |
Jun 05 04:31:01 PM PDT 24 |
82864754108 ps |
| T11 |
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.378450822 |
|
|
Jun 05 03:58:50 PM PDT 24 |
Jun 05 04:00:18 PM PDT 24 |
2080890376 ps |
| T12 |
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.1061956572 |
|
|
Jun 05 04:01:57 PM PDT 24 |
Jun 05 04:02:48 PM PDT 24 |
772346904 ps |
| T17 |
/workspace/coverage/default/33.sram_ctrl_mem_partial_access.31097950 |
|
|
Jun 05 04:00:33 PM PDT 24 |
Jun 05 04:01:58 PM PDT 24 |
9772822893 ps |
| T18 |
/workspace/coverage/default/15.sram_ctrl_access_during_key_req.50881015 |
|
|
Jun 05 03:58:52 PM PDT 24 |
Jun 05 04:00:53 PM PDT 24 |
1549507504 ps |
| T6 |
/workspace/coverage/default/15.sram_ctrl_lc_escalation.3863706762 |
|
|
Jun 05 03:58:56 PM PDT 24 |
Jun 05 04:00:01 PM PDT 24 |
9211933112 ps |
| T29 |
/workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.1695201379 |
|
|
Jun 05 03:58:22 PM PDT 24 |
Jun 05 03:58:44 PM PDT 24 |
634609372 ps |
| T13 |
/workspace/coverage/default/16.sram_ctrl_partial_access.156515775 |
|
|
Jun 05 03:59:01 PM PDT 24 |
Jun 05 04:01:32 PM PDT 24 |
1782685822 ps |
| T16 |
/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.711446041 |
|
|
Jun 05 04:00:33 PM PDT 24 |
Jun 05 04:00:42 PM PDT 24 |
897155193 ps |
| T71 |
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.453856169 |
|
|
Jun 05 03:58:25 PM PDT 24 |
Jun 05 04:00:47 PM PDT 24 |
4542245215 ps |
| T58 |
/workspace/coverage/default/45.sram_ctrl_max_throughput.46748529 |
|
|
Jun 05 04:01:44 PM PDT 24 |
Jun 05 04:02:52 PM PDT 24 |
1043942417 ps |
| T15 |
/workspace/coverage/default/35.sram_ctrl_bijection.3748214491 |
|
|
Jun 05 04:00:33 PM PDT 24 |
Jun 05 04:26:41 PM PDT 24 |
100722563116 ps |
| T104 |
/workspace/coverage/default/36.sram_ctrl_bijection.1876010430 |
|
|
Jun 05 04:00:41 PM PDT 24 |
Jun 05 04:50:37 PM PDT 24 |
351788459450 ps |
| T140 |
/workspace/coverage/default/28.sram_ctrl_max_throughput.1611667720 |
|
|
Jun 05 03:59:57 PM PDT 24 |
Jun 05 04:01:38 PM PDT 24 |
759716984 ps |
| T30 |
/workspace/coverage/default/19.sram_ctrl_executable.1173996174 |
|
|
Jun 05 03:59:06 PM PDT 24 |
Jun 05 04:13:35 PM PDT 24 |
31547028147 ps |
| T80 |
/workspace/coverage/default/8.sram_ctrl_multiple_keys.2301921635 |
|
|
Jun 05 03:58:31 PM PDT 24 |
Jun 05 04:12:05 PM PDT 24 |
12130837361 ps |
| T141 |
/workspace/coverage/default/25.sram_ctrl_partial_access.654599030 |
|
|
Jun 05 03:59:43 PM PDT 24 |
Jun 05 03:59:54 PM PDT 24 |
691405348 ps |
| T142 |
/workspace/coverage/default/27.sram_ctrl_bijection.3804232530 |
|
|
Jun 05 03:59:48 PM PDT 24 |
Jun 05 04:14:00 PM PDT 24 |
151817085483 ps |
| T50 |
/workspace/coverage/default/16.sram_ctrl_mem_partial_access.1667870889 |
|
|
Jun 05 03:59:01 PM PDT 24 |
Jun 05 04:00:25 PM PDT 24 |
10848749890 ps |
| T7 |
/workspace/coverage/default/16.sram_ctrl_stress_all.4117995956 |
|
|
Jun 05 03:59:06 PM PDT 24 |
Jun 05 04:41:59 PM PDT 24 |
37764205395 ps |
| T143 |
/workspace/coverage/default/12.sram_ctrl_stress_all.914898544 |
|
|
Jun 05 03:58:50 PM PDT 24 |
Jun 05 04:56:53 PM PDT 24 |
267370049248 ps |
| T144 |
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.795874911 |
|
|
Jun 05 04:01:45 PM PDT 24 |
Jun 05 04:03:39 PM PDT 24 |
3912231375 ps |
| T145 |
/workspace/coverage/default/16.sram_ctrl_multiple_keys.3746511657 |
|
|
Jun 05 03:58:59 PM PDT 24 |
Jun 05 04:15:29 PM PDT 24 |
54288946882 ps |
| T146 |
/workspace/coverage/default/15.sram_ctrl_bijection.266286295 |
|
|
Jun 05 03:58:52 PM PDT 24 |
Jun 05 04:13:09 PM PDT 24 |
50093551833 ps |
| T147 |
/workspace/coverage/default/42.sram_ctrl_executable.4122713577 |
|
|
Jun 05 04:01:32 PM PDT 24 |
Jun 05 04:02:30 PM PDT 24 |
4481755507 ps |
| T62 |
/workspace/coverage/default/11.sram_ctrl_regwen.172211836 |
|
|
Jun 05 03:58:43 PM PDT 24 |
Jun 05 04:12:43 PM PDT 24 |
6397128188 ps |
| T31 |
/workspace/coverage/default/48.sram_ctrl_ram_cfg.787152700 |
|
|
Jun 05 04:02:10 PM PDT 24 |
Jun 05 04:02:14 PM PDT 24 |
436536694 ps |
| T14 |
/workspace/coverage/default/29.sram_ctrl_partial_access_b2b.16462030 |
|
|
Jun 05 03:59:54 PM PDT 24 |
Jun 05 04:09:14 PM PDT 24 |
23187152052 ps |
| T148 |
/workspace/coverage/default/1.sram_ctrl_bijection.2077372219 |
|
|
Jun 05 03:58:15 PM PDT 24 |
Jun 05 04:36:51 PM PDT 24 |
142229924581 ps |
| T51 |
/workspace/coverage/default/19.sram_ctrl_mem_partial_access.1890365394 |
|
|
Jun 05 03:59:07 PM PDT 24 |
Jun 05 04:00:43 PM PDT 24 |
29094423562 ps |
| T66 |
/workspace/coverage/default/2.sram_ctrl_lc_escalation.1285650672 |
|
|
Jun 05 03:58:23 PM PDT 24 |
Jun 05 03:59:26 PM PDT 24 |
10594446794 ps |
| T99 |
/workspace/coverage/default/31.sram_ctrl_stress_pipeline.2574076705 |
|
|
Jun 05 04:00:12 PM PDT 24 |
Jun 05 04:03:37 PM PDT 24 |
37790762958 ps |
| T149 |
/workspace/coverage/default/43.sram_ctrl_partial_access.1495489377 |
|
|
Jun 05 04:01:30 PM PDT 24 |
Jun 05 04:02:52 PM PDT 24 |
858923910 ps |
| T150 |
/workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.2922063460 |
|
|
Jun 05 04:00:06 PM PDT 24 |
Jun 05 04:00:17 PM PDT 24 |
736221901 ps |
| T151 |
/workspace/coverage/default/24.sram_ctrl_max_throughput.2353729516 |
|
|
Jun 05 03:59:30 PM PDT 24 |
Jun 05 03:59:58 PM PDT 24 |
751164571 ps |
| T32 |
/workspace/coverage/default/26.sram_ctrl_ram_cfg.3751763311 |
|
|
Jun 05 03:59:46 PM PDT 24 |
Jun 05 03:59:50 PM PDT 24 |
712954883 ps |
| T85 |
/workspace/coverage/default/41.sram_ctrl_mem_partial_access.2758008428 |
|
|
Jun 05 04:01:17 PM PDT 24 |
Jun 05 04:03:44 PM PDT 24 |
12113507257 ps |
| T54 |
/workspace/coverage/default/20.sram_ctrl_mem_partial_access.3875381498 |
|
|
Jun 05 03:59:14 PM PDT 24 |
Jun 05 04:02:05 PM PDT 24 |
18778802172 ps |
| T152 |
/workspace/coverage/default/38.sram_ctrl_multiple_keys.672090895 |
|
|
Jun 05 04:00:57 PM PDT 24 |
Jun 05 04:12:31 PM PDT 24 |
28018805527 ps |
| T43 |
/workspace/coverage/default/3.sram_ctrl_smoke.4084893023 |
|
|
Jun 05 03:58:23 PM PDT 24 |
Jun 05 03:58:31 PM PDT 24 |
774347588 ps |
| T139 |
/workspace/coverage/default/45.sram_ctrl_mem_walk.1025717721 |
|
|
Jun 05 04:01:52 PM PDT 24 |
Jun 05 04:06:13 PM PDT 24 |
15769258383 ps |
| T25 |
/workspace/coverage/default/0.sram_ctrl_stress_all.338446899 |
|
|
Jun 05 03:58:10 PM PDT 24 |
Jun 05 05:21:59 PM PDT 24 |
81947159134 ps |
| T55 |
/workspace/coverage/default/39.sram_ctrl_mem_partial_access.2709062104 |
|
|
Jun 05 04:00:59 PM PDT 24 |
Jun 05 04:02:34 PM PDT 24 |
10429400463 ps |
| T100 |
/workspace/coverage/default/40.sram_ctrl_partial_access_b2b.2258955000 |
|
|
Jun 05 04:01:10 PM PDT 24 |
Jun 05 04:09:52 PM PDT 24 |
48171344454 ps |
| T93 |
/workspace/coverage/default/2.sram_ctrl_mem_partial_access.3921951441 |
|
|
Jun 05 03:58:23 PM PDT 24 |
Jun 05 03:59:35 PM PDT 24 |
2352162863 ps |
| T26 |
/workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.335032691 |
|
|
Jun 05 04:00:41 PM PDT 24 |
Jun 05 04:01:31 PM PDT 24 |
1339310090 ps |
| T153 |
/workspace/coverage/default/0.sram_ctrl_max_throughput.511539895 |
|
|
Jun 05 03:58:11 PM PDT 24 |
Jun 05 03:58:33 PM PDT 24 |
4402760861 ps |
| T134 |
/workspace/coverage/default/46.sram_ctrl_executable.2181062132 |
|
|
Jun 05 04:01:54 PM PDT 24 |
Jun 05 04:03:03 PM PDT 24 |
2587115248 ps |
| T101 |
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.3448951242 |
|
|
Jun 05 03:58:34 PM PDT 24 |
Jun 05 04:06:22 PM PDT 24 |
75136029934 ps |
| T22 |
/workspace/coverage/default/3.sram_ctrl_sec_cm.904587199 |
|
|
Jun 05 03:58:19 PM PDT 24 |
Jun 05 03:58:23 PM PDT 24 |
1661112538 ps |
| T19 |
/workspace/coverage/default/7.sram_ctrl_alert_test.1428238355 |
|
|
Jun 05 03:58:30 PM PDT 24 |
Jun 05 03:58:31 PM PDT 24 |
30753014 ps |
| T35 |
/workspace/coverage/default/10.sram_ctrl_executable.1214398368 |
|
|
Jun 05 03:58:50 PM PDT 24 |
Jun 05 04:14:01 PM PDT 24 |
30101678544 ps |
| T36 |
/workspace/coverage/default/4.sram_ctrl_access_during_key_req.791985497 |
|
|
Jun 05 03:58:20 PM PDT 24 |
Jun 05 04:09:25 PM PDT 24 |
50831607563 ps |
| T37 |
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.34996074 |
|
|
Jun 05 03:58:28 PM PDT 24 |
Jun 05 04:04:05 PM PDT 24 |
23883662797 ps |
| T38 |
/workspace/coverage/default/14.sram_ctrl_smoke.1417536222 |
|
|
Jun 05 03:58:55 PM PDT 24 |
Jun 05 03:59:21 PM PDT 24 |
9609331293 ps |
| T20 |
/workspace/coverage/default/49.sram_ctrl_alert_test.351690981 |
|
|
Jun 05 04:02:27 PM PDT 24 |
Jun 05 04:02:28 PM PDT 24 |
24063088 ps |
| T39 |
/workspace/coverage/default/17.sram_ctrl_lc_escalation.2156373435 |
|
|
Jun 05 03:59:04 PM PDT 24 |
Jun 05 04:00:34 PM PDT 24 |
56404414775 ps |
| T40 |
/workspace/coverage/default/3.sram_ctrl_ram_cfg.626281841 |
|
|
Jun 05 03:58:21 PM PDT 24 |
Jun 05 03:58:25 PM PDT 24 |
356063230 ps |
| T41 |
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.3707035128 |
|
|
Jun 05 04:01:38 PM PDT 24 |
Jun 05 04:07:55 PM PDT 24 |
5942960711 ps |
| T21 |
/workspace/coverage/default/41.sram_ctrl_alert_test.2181682623 |
|
|
Jun 05 04:01:19 PM PDT 24 |
Jun 05 04:01:20 PM PDT 24 |
11440220 ps |
| T42 |
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.3509984639 |
|
|
Jun 05 03:58:32 PM PDT 24 |
Jun 05 04:27:29 PM PDT 24 |
19917012768 ps |
| T52 |
/workspace/coverage/default/38.sram_ctrl_mem_walk.1165793190 |
|
|
Jun 05 04:00:52 PM PDT 24 |
Jun 05 04:06:32 PM PDT 24 |
20636313094 ps |
| T136 |
/workspace/coverage/default/5.sram_ctrl_partial_access.1513869565 |
|
|
Jun 05 03:58:32 PM PDT 24 |
Jun 05 03:58:47 PM PDT 24 |
2186207460 ps |
| T154 |
/workspace/coverage/default/6.sram_ctrl_partial_access.4070640178 |
|
|
Jun 05 03:58:33 PM PDT 24 |
Jun 05 03:58:50 PM PDT 24 |
3762212817 ps |
| T44 |
/workspace/coverage/default/27.sram_ctrl_executable.2268681521 |
|
|
Jun 05 03:59:47 PM PDT 24 |
Jun 05 04:06:03 PM PDT 24 |
33182218530 ps |
| T102 |
/workspace/coverage/default/17.sram_ctrl_mem_partial_access.991971919 |
|
|
Jun 05 03:59:07 PM PDT 24 |
Jun 05 04:00:11 PM PDT 24 |
4597089981 ps |
| T155 |
/workspace/coverage/default/44.sram_ctrl_max_throughput.3909276905 |
|
|
Jun 05 04:01:39 PM PDT 24 |
Jun 05 04:02:39 PM PDT 24 |
735082498 ps |
| T156 |
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.3595119714 |
|
|
Jun 05 04:01:26 PM PDT 24 |
Jun 05 04:01:49 PM PDT 24 |
4202940635 ps |
| T157 |
/workspace/coverage/default/15.sram_ctrl_stress_all.248222225 |
|
|
Jun 05 03:59:01 PM PDT 24 |
Jun 05 05:25:46 PM PDT 24 |
77633080931 ps |
| T158 |
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.2583493643 |
|
|
Jun 05 03:58:42 PM PDT 24 |
Jun 05 04:03:06 PM PDT 24 |
2809694970 ps |
| T138 |
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.1783878766 |
|
|
Jun 05 04:02:10 PM PDT 24 |
Jun 05 04:03:32 PM PDT 24 |
11088336317 ps |
| T159 |
/workspace/coverage/default/12.sram_ctrl_max_throughput.3535726737 |
|
|
Jun 05 03:58:53 PM PDT 24 |
Jun 05 03:59:16 PM PDT 24 |
1896396031 ps |
| T135 |
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.3835458318 |
|
|
Jun 05 03:58:55 PM PDT 24 |
Jun 05 04:01:35 PM PDT 24 |
5046075224 ps |
| T160 |
/workspace/coverage/default/21.sram_ctrl_stress_pipeline.1909539906 |
|
|
Jun 05 03:59:18 PM PDT 24 |
Jun 05 04:05:25 PM PDT 24 |
23730432466 ps |
| T161 |
/workspace/coverage/default/42.sram_ctrl_bijection.2660914602 |
|
|
Jun 05 04:01:26 PM PDT 24 |
Jun 05 04:27:20 PM PDT 24 |
100729965663 ps |
| T162 |
/workspace/coverage/default/27.sram_ctrl_stress_pipeline.819250126 |
|
|
Jun 05 03:59:45 PM PDT 24 |
Jun 05 04:01:06 PM PDT 24 |
6784110680 ps |
| T45 |
/workspace/coverage/default/37.sram_ctrl_stress_all.1266424090 |
|
|
Jun 05 04:00:50 PM PDT 24 |
Jun 05 04:17:16 PM PDT 24 |
58405905453 ps |
| T163 |
/workspace/coverage/default/31.sram_ctrl_alert_test.3988339715 |
|
|
Jun 05 04:00:11 PM PDT 24 |
Jun 05 04:00:12 PM PDT 24 |
14587503 ps |
| T164 |
/workspace/coverage/default/44.sram_ctrl_alert_test.3895028318 |
|
|
Jun 05 04:01:45 PM PDT 24 |
Jun 05 04:01:46 PM PDT 24 |
15103124 ps |
| T165 |
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.337857513 |
|
|
Jun 05 03:58:50 PM PDT 24 |
Jun 05 04:01:23 PM PDT 24 |
1183784090 ps |
| T166 |
/workspace/coverage/default/0.sram_ctrl_partial_access.3167528189 |
|
|
Jun 05 03:58:13 PM PDT 24 |
Jun 05 04:00:28 PM PDT 24 |
3293610646 ps |
| T28 |
/workspace/coverage/default/34.sram_ctrl_lc_escalation.3908780765 |
|
|
Jun 05 04:00:33 PM PDT 24 |
Jun 05 04:02:00 PM PDT 24 |
13999805562 ps |
| T167 |
/workspace/coverage/default/28.sram_ctrl_alert_test.4246631067 |
|
|
Jun 05 03:59:54 PM PDT 24 |
Jun 05 03:59:55 PM PDT 24 |
12245529 ps |
| T168 |
/workspace/coverage/default/31.sram_ctrl_executable.2632029593 |
|
|
Jun 05 04:00:14 PM PDT 24 |
Jun 05 04:10:37 PM PDT 24 |
182058730651 ps |
| T169 |
/workspace/coverage/default/49.sram_ctrl_max_throughput.2608861852 |
|
|
Jun 05 04:02:20 PM PDT 24 |
Jun 05 04:03:04 PM PDT 24 |
778010431 ps |
| T67 |
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.1301258467 |
|
|
Jun 05 04:01:45 PM PDT 24 |
Jun 05 04:02:12 PM PDT 24 |
3315258439 ps |
| T170 |
/workspace/coverage/default/26.sram_ctrl_access_during_key_req.3031104212 |
|
|
Jun 05 03:59:41 PM PDT 24 |
Jun 05 04:13:44 PM PDT 24 |
12634616869 ps |
| T171 |
/workspace/coverage/default/19.sram_ctrl_max_throughput.3239040497 |
|
|
Jun 05 03:59:12 PM PDT 24 |
Jun 05 04:00:24 PM PDT 24 |
764313401 ps |
| T172 |
/workspace/coverage/default/23.sram_ctrl_stress_pipeline.2618762967 |
|
|
Jun 05 03:59:31 PM PDT 24 |
Jun 05 04:03:28 PM PDT 24 |
8136379267 ps |
| T173 |
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.126555844 |
|
|
Jun 05 04:01:53 PM PDT 24 |
Jun 05 04:05:48 PM PDT 24 |
19058881245 ps |
| T174 |
/workspace/coverage/default/40.sram_ctrl_ram_cfg.2784048417 |
|
|
Jun 05 04:01:09 PM PDT 24 |
Jun 05 04:01:12 PM PDT 24 |
1350435996 ps |
| T68 |
/workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.3262727625 |
|
|
Jun 05 03:58:25 PM PDT 24 |
Jun 05 03:58:35 PM PDT 24 |
475551170 ps |
| T175 |
/workspace/coverage/default/19.sram_ctrl_stress_pipeline.2320929311 |
|
|
Jun 05 03:59:07 PM PDT 24 |
Jun 05 04:04:18 PM PDT 24 |
4306850044 ps |
| T176 |
/workspace/coverage/default/19.sram_ctrl_bijection.1678954575 |
|
|
Jun 05 03:59:12 PM PDT 24 |
Jun 05 04:35:50 PM PDT 24 |
127769261072 ps |
| T27 |
/workspace/coverage/default/13.sram_ctrl_regwen.3676794182 |
|
|
Jun 05 03:58:50 PM PDT 24 |
Jun 05 04:13:38 PM PDT 24 |
20378775160 ps |
| T56 |
/workspace/coverage/default/31.sram_ctrl_mem_partial_access.2301145640 |
|
|
Jun 05 04:00:15 PM PDT 24 |
Jun 05 04:02:35 PM PDT 24 |
4857287812 ps |
| T177 |
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.906879240 |
|
|
Jun 05 03:58:11 PM PDT 24 |
Jun 05 03:59:17 PM PDT 24 |
1412197833 ps |
| T178 |
/workspace/coverage/default/21.sram_ctrl_multiple_keys.3430101076 |
|
|
Jun 05 03:59:13 PM PDT 24 |
Jun 05 04:13:23 PM PDT 24 |
62387921800 ps |
| T179 |
/workspace/coverage/default/28.sram_ctrl_regwen.3059551968 |
|
|
Jun 05 03:59:55 PM PDT 24 |
Jun 05 04:00:43 PM PDT 24 |
816499906 ps |
| T180 |
/workspace/coverage/default/18.sram_ctrl_multiple_keys.2783329310 |
|
|
Jun 05 03:59:01 PM PDT 24 |
Jun 05 04:16:49 PM PDT 24 |
98891445981 ps |
| T69 |
/workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.1834113205 |
|
|
Jun 05 03:59:22 PM PDT 24 |
Jun 05 03:59:33 PM PDT 24 |
1419678561 ps |
| T53 |
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.3196626448 |
|
|
Jun 05 04:02:02 PM PDT 24 |
Jun 05 04:05:07 PM PDT 24 |
79389082690 ps |
| T109 |
/workspace/coverage/default/22.sram_ctrl_access_during_key_req.2651591606 |
|
|
Jun 05 03:59:22 PM PDT 24 |
Jun 05 04:25:56 PM PDT 24 |
43281780089 ps |
| T110 |
/workspace/coverage/default/41.sram_ctrl_ram_cfg.4204624552 |
|
|
Jun 05 04:01:17 PM PDT 24 |
Jun 05 04:01:21 PM PDT 24 |
2108058603 ps |
| T111 |
/workspace/coverage/default/18.sram_ctrl_bijection.1822197960 |
|
|
Jun 05 03:58:59 PM PDT 24 |
Jun 05 04:34:08 PM PDT 24 |
178653564687 ps |
| T57 |
/workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.3153910392 |
|
|
Jun 05 04:00:21 PM PDT 24 |
Jun 05 04:01:50 PM PDT 24 |
7462413633 ps |
| T112 |
/workspace/coverage/default/32.sram_ctrl_mem_walk.2596751716 |
|
|
Jun 05 04:00:20 PM PDT 24 |
Jun 05 04:02:23 PM PDT 24 |
4113925635 ps |
| T113 |
/workspace/coverage/default/36.sram_ctrl_mem_walk.247200930 |
|
|
Jun 05 04:00:43 PM PDT 24 |
Jun 05 04:03:20 PM PDT 24 |
5261311057 ps |
| T114 |
/workspace/coverage/default/24.sram_ctrl_bijection.4119084458 |
|
|
Jun 05 03:59:31 PM PDT 24 |
Jun 05 04:20:10 PM PDT 24 |
72443061312 ps |
| T115 |
/workspace/coverage/default/2.sram_ctrl_regwen.1793161831 |
|
|
Jun 05 03:58:23 PM PDT 24 |
Jun 05 04:13:50 PM PDT 24 |
22954131087 ps |
| T181 |
/workspace/coverage/default/15.sram_ctrl_mem_partial_access.4220032030 |
|
|
Jun 05 03:58:59 PM PDT 24 |
Jun 05 04:00:22 PM PDT 24 |
3000563307 ps |
| T182 |
/workspace/coverage/default/32.sram_ctrl_access_during_key_req.3535186479 |
|
|
Jun 05 04:00:13 PM PDT 24 |
Jun 05 04:13:15 PM PDT 24 |
25070394380 ps |
| T117 |
/workspace/coverage/default/36.sram_ctrl_stress_all.370877114 |
|
|
Jun 05 04:00:44 PM PDT 24 |
Jun 05 04:31:34 PM PDT 24 |
61303133203 ps |
| T183 |
/workspace/coverage/default/31.sram_ctrl_mem_walk.2394143398 |
|
|
Jun 05 04:00:12 PM PDT 24 |
Jun 05 04:02:41 PM PDT 24 |
10519178002 ps |
| T184 |
/workspace/coverage/default/19.sram_ctrl_multiple_keys.432491730 |
|
|
Jun 05 03:59:06 PM PDT 24 |
Jun 05 04:20:35 PM PDT 24 |
106377986224 ps |
| T133 |
/workspace/coverage/default/18.sram_ctrl_stress_all.218040845 |
|
|
Jun 05 03:59:05 PM PDT 24 |
Jun 05 04:52:08 PM PDT 24 |
34805387534 ps |
| T185 |
/workspace/coverage/default/35.sram_ctrl_smoke.2911982538 |
|
|
Jun 05 04:00:32 PM PDT 24 |
Jun 05 04:00:42 PM PDT 24 |
1425754956 ps |
| T186 |
/workspace/coverage/default/31.sram_ctrl_partial_access.607532343 |
|
|
Jun 05 04:00:14 PM PDT 24 |
Jun 05 04:00:21 PM PDT 24 |
881523685 ps |
| T187 |
/workspace/coverage/default/34.sram_ctrl_ram_cfg.2395226902 |
|
|
Jun 05 04:00:31 PM PDT 24 |
Jun 05 04:00:35 PM PDT 24 |
696086628 ps |
| T188 |
/workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.3262354099 |
|
|
Jun 05 03:58:21 PM PDT 24 |
Jun 05 03:59:12 PM PDT 24 |
2719942221 ps |
| T189 |
/workspace/coverage/default/21.sram_ctrl_mem_partial_access.3138622354 |
|
|
Jun 05 03:59:19 PM PDT 24 |
Jun 05 04:01:39 PM PDT 24 |
9706869099 ps |
| T190 |
/workspace/coverage/default/1.sram_ctrl_max_throughput.816919331 |
|
|
Jun 05 03:58:12 PM PDT 24 |
Jun 05 03:58:52 PM PDT 24 |
2866441873 ps |
| T191 |
/workspace/coverage/default/12.sram_ctrl_bijection.2167191126 |
|
|
Jun 05 03:58:50 PM PDT 24 |
Jun 05 04:44:14 PM PDT 24 |
317233532574 ps |
| T192 |
/workspace/coverage/default/3.sram_ctrl_partial_access_b2b.2311162723 |
|
|
Jun 05 03:58:21 PM PDT 24 |
Jun 05 04:06:03 PM PDT 24 |
18296531891 ps |
| T193 |
/workspace/coverage/default/15.sram_ctrl_stress_pipeline.2022191280 |
|
|
Jun 05 03:58:52 PM PDT 24 |
Jun 05 04:03:28 PM PDT 24 |
7384281744 ps |
| T194 |
/workspace/coverage/default/3.sram_ctrl_partial_access.1348270695 |
|
|
Jun 05 03:58:23 PM PDT 24 |
Jun 05 03:58:28 PM PDT 24 |
742658423 ps |
| T195 |
/workspace/coverage/default/24.sram_ctrl_smoke.1048894528 |
|
|
Jun 05 03:59:31 PM PDT 24 |
Jun 05 03:59:51 PM PDT 24 |
859900867 ps |
| T196 |
/workspace/coverage/default/14.sram_ctrl_alert_test.1801155725 |
|
|
Jun 05 03:58:55 PM PDT 24 |
Jun 05 03:58:57 PM PDT 24 |
15055820 ps |
| T197 |
/workspace/coverage/default/11.sram_ctrl_partial_access.2740554476 |
|
|
Jun 05 03:58:41 PM PDT 24 |
Jun 05 03:59:05 PM PDT 24 |
888262413 ps |
| T198 |
/workspace/coverage/default/24.sram_ctrl_partial_access.2377967465 |
|
|
Jun 05 03:59:30 PM PDT 24 |
Jun 05 03:59:51 PM PDT 24 |
641919696 ps |
| T199 |
/workspace/coverage/default/3.sram_ctrl_stress_pipeline.1913154896 |
|
|
Jun 05 03:58:18 PM PDT 24 |
Jun 05 04:05:23 PM PDT 24 |
5720627844 ps |
| T200 |
/workspace/coverage/default/25.sram_ctrl_mem_walk.592256918 |
|
|
Jun 05 03:59:42 PM PDT 24 |
Jun 05 04:05:21 PM PDT 24 |
28224033895 ps |
| T137 |
/workspace/coverage/default/2.sram_ctrl_partial_access_b2b.2807192957 |
|
|
Jun 05 03:58:22 PM PDT 24 |
Jun 05 04:05:52 PM PDT 24 |
20529016309 ps |
| T201 |
/workspace/coverage/default/4.sram_ctrl_alert_test.626621054 |
|
|
Jun 05 03:58:30 PM PDT 24 |
Jun 05 03:58:32 PM PDT 24 |
14234547 ps |
| T202 |
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.2693742988 |
|
|
Jun 05 03:58:50 PM PDT 24 |
Jun 05 03:59:17 PM PDT 24 |
3236726390 ps |
| T203 |
/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.2573168376 |
|
|
Jun 05 04:01:26 PM PDT 24 |
Jun 05 04:05:50 PM PDT 24 |
16312190625 ps |
| T204 |
/workspace/coverage/default/32.sram_ctrl_smoke.2997107884 |
|
|
Jun 05 04:00:10 PM PDT 24 |
Jun 05 04:00:21 PM PDT 24 |
2749631234 ps |
| T205 |
/workspace/coverage/default/20.sram_ctrl_regwen.2396856306 |
|
|
Jun 05 03:59:14 PM PDT 24 |
Jun 05 04:15:01 PM PDT 24 |
23487660401 ps |
| T118 |
/workspace/coverage/default/6.sram_ctrl_lc_escalation.949234567 |
|
|
Jun 05 03:58:28 PM PDT 24 |
Jun 05 03:59:20 PM PDT 24 |
8232397826 ps |
| T206 |
/workspace/coverage/default/3.sram_ctrl_lc_escalation.2163682995 |
|
|
Jun 05 03:58:21 PM PDT 24 |
Jun 05 03:59:33 PM PDT 24 |
10283462369 ps |
| T207 |
/workspace/coverage/default/43.sram_ctrl_mem_walk.3150959858 |
|
|
Jun 05 04:01:36 PM PDT 24 |
Jun 05 04:06:37 PM PDT 24 |
21003321351 ps |
| T208 |
/workspace/coverage/default/33.sram_ctrl_multiple_keys.3328639850 |
|
|
Jun 05 04:00:20 PM PDT 24 |
Jun 05 04:03:47 PM PDT 24 |
17530941322 ps |
| T209 |
/workspace/coverage/default/32.sram_ctrl_executable.2608089233 |
|
|
Jun 05 04:00:12 PM PDT 24 |
Jun 05 04:35:26 PM PDT 24 |
116371149245 ps |
| T210 |
/workspace/coverage/default/18.sram_ctrl_partial_access.2650857594 |
|
|
Jun 05 03:59:05 PM PDT 24 |
Jun 05 03:59:33 PM PDT 24 |
6719355982 ps |
| T211 |
/workspace/coverage/default/30.sram_ctrl_ram_cfg.2365128206 |
|
|
Jun 05 04:00:04 PM PDT 24 |
Jun 05 04:00:09 PM PDT 24 |
691660921 ps |
| T212 |
/workspace/coverage/default/12.sram_ctrl_multiple_keys.4218960571 |
|
|
Jun 05 03:58:50 PM PDT 24 |
Jun 05 04:16:48 PM PDT 24 |
10346258887 ps |
| T213 |
/workspace/coverage/default/37.sram_ctrl_partial_access.4184551036 |
|
|
Jun 05 04:00:50 PM PDT 24 |
Jun 05 04:01:15 PM PDT 24 |
5366505364 ps |
| T214 |
/workspace/coverage/default/17.sram_ctrl_regwen.642287758 |
|
|
Jun 05 03:59:00 PM PDT 24 |
Jun 05 04:11:56 PM PDT 24 |
57125349604 ps |
| T215 |
/workspace/coverage/default/27.sram_ctrl_smoke.1909488830 |
|
|
Jun 05 03:59:47 PM PDT 24 |
Jun 05 04:00:08 PM PDT 24 |
5193649957 ps |
| T216 |
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.4265722257 |
|
|
Jun 05 03:58:30 PM PDT 24 |
Jun 05 04:01:59 PM PDT 24 |
29630722982 ps |
| T217 |
/workspace/coverage/default/15.sram_ctrl_smoke.1542208921 |
|
|
Jun 05 03:58:51 PM PDT 24 |
Jun 05 03:59:53 PM PDT 24 |
770958997 ps |
| T218 |
/workspace/coverage/default/29.sram_ctrl_smoke.1198965580 |
|
|
Jun 05 03:59:56 PM PDT 24 |
Jun 05 04:00:04 PM PDT 24 |
731147641 ps |
| T219 |
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.2842909790 |
|
|
Jun 05 04:01:37 PM PDT 24 |
Jun 05 04:10:01 PM PDT 24 |
86898326925 ps |
| T220 |
/workspace/coverage/default/35.sram_ctrl_max_throughput.919750795 |
|
|
Jun 05 04:00:32 PM PDT 24 |
Jun 05 04:02:54 PM PDT 24 |
818366032 ps |
| T221 |
/workspace/coverage/default/42.sram_ctrl_mem_partial_access.556455412 |
|
|
Jun 05 04:01:30 PM PDT 24 |
Jun 05 04:03:41 PM PDT 24 |
1590526453 ps |
| T222 |
/workspace/coverage/default/13.sram_ctrl_access_during_key_req.4000008588 |
|
|
Jun 05 03:58:52 PM PDT 24 |
Jun 05 04:07:31 PM PDT 24 |
31436126573 ps |
| T223 |
/workspace/coverage/default/6.sram_ctrl_max_throughput.1909050017 |
|
|
Jun 05 03:58:30 PM PDT 24 |
Jun 05 03:59:05 PM PDT 24 |
8015012135 ps |
| T224 |
/workspace/coverage/default/36.sram_ctrl_alert_test.4069765604 |
|
|
Jun 05 04:00:41 PM PDT 24 |
Jun 05 04:00:43 PM PDT 24 |
27204644 ps |
| T225 |
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.518386169 |
|
|
Jun 05 03:58:30 PM PDT 24 |
Jun 05 04:06:59 PM PDT 24 |
397593794553 ps |
| T226 |
/workspace/coverage/default/21.sram_ctrl_ram_cfg.3094991115 |
|
|
Jun 05 03:59:26 PM PDT 24 |
Jun 05 03:59:30 PM PDT 24 |
2575315110 ps |
| T227 |
/workspace/coverage/default/21.sram_ctrl_partial_access_b2b.1740029692 |
|
|
Jun 05 03:59:16 PM PDT 24 |
Jun 05 04:01:39 PM PDT 24 |
11166564017 ps |
| T228 |
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.3037425706 |
|
|
Jun 05 04:01:56 PM PDT 24 |
Jun 05 04:06:17 PM PDT 24 |
8642080954 ps |
| T229 |
/workspace/coverage/default/39.sram_ctrl_regwen.1640367431 |
|
|
Jun 05 04:01:00 PM PDT 24 |
Jun 05 04:20:05 PM PDT 24 |
17953146197 ps |
| T230 |
/workspace/coverage/default/5.sram_ctrl_regwen.94558495 |
|
|
Jun 05 03:58:27 PM PDT 24 |
Jun 05 04:09:41 PM PDT 24 |
2468717946 ps |
| T231 |
/workspace/coverage/default/5.sram_ctrl_executable.3041018326 |
|
|
Jun 05 03:58:32 PM PDT 24 |
Jun 05 04:13:21 PM PDT 24 |
50792859503 ps |
| T232 |
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.2980092157 |
|
|
Jun 05 03:58:32 PM PDT 24 |
Jun 05 03:59:45 PM PDT 24 |
2924080255 ps |
| T233 |
/workspace/coverage/default/41.sram_ctrl_regwen.1565864661 |
|
|
Jun 05 04:01:18 PM PDT 24 |
Jun 05 04:16:54 PM PDT 24 |
13623506659 ps |
| T234 |
/workspace/coverage/default/18.sram_ctrl_regwen.1537314846 |
|
|
Jun 05 03:59:06 PM PDT 24 |
Jun 05 04:04:48 PM PDT 24 |
23381801373 ps |
| T235 |
/workspace/coverage/default/42.sram_ctrl_access_during_key_req.1091640646 |
|
|
Jun 05 04:01:30 PM PDT 24 |
Jun 05 04:15:03 PM PDT 24 |
229779651126 ps |
| T236 |
/workspace/coverage/default/46.sram_ctrl_mem_walk.215136475 |
|
|
Jun 05 04:01:54 PM PDT 24 |
Jun 05 04:04:31 PM PDT 24 |
43197844122 ps |
| T237 |
/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.2244618880 |
|
|
Jun 05 04:00:20 PM PDT 24 |
Jun 05 04:05:41 PM PDT 24 |
13900529565 ps |
| T70 |
/workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.2769855799 |
|
|
Jun 05 03:58:52 PM PDT 24 |
Jun 05 03:59:17 PM PDT 24 |
3760241813 ps |
| T238 |
/workspace/coverage/default/30.sram_ctrl_bijection.2710517504 |
|
|
Jun 05 04:00:06 PM PDT 24 |
Jun 05 04:30:03 PM PDT 24 |
252414172676 ps |
| T23 |
/workspace/coverage/default/2.sram_ctrl_sec_cm.472859339 |
|
|
Jun 05 03:58:18 PM PDT 24 |
Jun 05 03:58:23 PM PDT 24 |
235707403 ps |
| T239 |
/workspace/coverage/default/12.sram_ctrl_ram_cfg.2550746062 |
|
|
Jun 05 03:58:49 PM PDT 24 |
Jun 05 03:58:53 PM PDT 24 |
893464483 ps |
| T105 |
/workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.2592088912 |
|
|
Jun 05 03:59:07 PM PDT 24 |
Jun 05 03:59:32 PM PDT 24 |
10956125739 ps |
| T240 |
/workspace/coverage/default/3.sram_ctrl_mem_walk.1852614131 |
|
|
Jun 05 03:58:20 PM PDT 24 |
Jun 05 04:01:06 PM PDT 24 |
7228658092 ps |
| T241 |
/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.2763364634 |
|
|
Jun 05 03:59:42 PM PDT 24 |
Jun 05 04:05:30 PM PDT 24 |
13661882626 ps |
| T242 |
/workspace/coverage/default/28.sram_ctrl_mem_walk.86693399 |
|
|
Jun 05 03:59:56 PM PDT 24 |
Jun 05 04:03:06 PM PDT 24 |
41314325289 ps |
| T243 |
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.217652391 |
|
|
Jun 05 03:58:51 PM PDT 24 |
Jun 05 04:07:27 PM PDT 24 |
30944383969 ps |
| T244 |
/workspace/coverage/default/40.sram_ctrl_max_throughput.2296332735 |
|
|
Jun 05 04:01:09 PM PDT 24 |
Jun 05 04:02:09 PM PDT 24 |
738950126 ps |
| T245 |
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1614680859 |
|
|
Jun 05 04:01:54 PM PDT 24 |
Jun 05 04:02:37 PM PDT 24 |
2034614691 ps |
| T246 |
/workspace/coverage/default/22.sram_ctrl_executable.3589500387 |
|
|
Jun 05 03:59:23 PM PDT 24 |
Jun 05 04:01:07 PM PDT 24 |
11536541575 ps |
| T247 |
/workspace/coverage/default/25.sram_ctrl_bijection.2708490622 |
|
|
Jun 05 03:59:44 PM PDT 24 |
Jun 05 04:13:14 PM PDT 24 |
180365755255 ps |
| T248 |
/workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.2593240824 |
|
|
Jun 05 03:59:21 PM PDT 24 |
Jun 05 04:00:00 PM PDT 24 |
2944926727 ps |
| T249 |
/workspace/coverage/default/45.sram_ctrl_smoke.188726406 |
|
|
Jun 05 04:01:45 PM PDT 24 |
Jun 05 04:03:00 PM PDT 24 |
22904274506 ps |
| T250 |
/workspace/coverage/default/25.sram_ctrl_partial_access_b2b.3177429065 |
|
|
Jun 05 03:59:42 PM PDT 24 |
Jun 05 04:02:55 PM PDT 24 |
7675798304 ps |
| T251 |
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.1892149525 |
|
|
Jun 05 04:01:18 PM PDT 24 |
Jun 05 04:06:01 PM PDT 24 |
4350492371 ps |
| T252 |
/workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.3790827681 |
|
|
Jun 05 03:58:20 PM PDT 24 |
Jun 05 03:59:15 PM PDT 24 |
2956524071 ps |
| T253 |
/workspace/coverage/default/49.sram_ctrl_partial_access.2863818783 |
|
|
Jun 05 04:02:25 PM PDT 24 |
Jun 05 04:05:15 PM PDT 24 |
3354498189 ps |
| T254 |
/workspace/coverage/default/38.sram_ctrl_access_during_key_req.1822488327 |
|
|
Jun 05 04:00:51 PM PDT 24 |
Jun 05 04:31:52 PM PDT 24 |
420606896143 ps |
| T255 |
/workspace/coverage/default/32.sram_ctrl_bijection.2793769402 |
|
|
Jun 05 04:00:12 PM PDT 24 |
Jun 05 04:37:11 PM PDT 24 |
281891211318 ps |
| T256 |
/workspace/coverage/default/44.sram_ctrl_executable.11348865 |
|
|
Jun 05 04:01:46 PM PDT 24 |
Jun 05 04:14:52 PM PDT 24 |
17895561320 ps |
| T257 |
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.2700615048 |
|
|
Jun 05 03:58:31 PM PDT 24 |
Jun 05 04:02:10 PM PDT 24 |
6462826262 ps |
| T258 |
/workspace/coverage/default/13.sram_ctrl_stress_pipeline.3916059857 |
|
|
Jun 05 03:58:57 PM PDT 24 |
Jun 05 04:01:20 PM PDT 24 |
2339700399 ps |
| T259 |
/workspace/coverage/default/45.sram_ctrl_ram_cfg.1622313489 |
|
|
Jun 05 04:01:53 PM PDT 24 |
Jun 05 04:01:57 PM PDT 24 |
5615254230 ps |
| T260 |
/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.970717527 |
|
|
Jun 05 03:58:50 PM PDT 24 |
Jun 05 04:03:16 PM PDT 24 |
56323059311 ps |
| T261 |
/workspace/coverage/default/32.sram_ctrl_regwen.419358105 |
|
|
Jun 05 04:00:23 PM PDT 24 |
Jun 05 04:05:28 PM PDT 24 |
10437323928 ps |
| T262 |
/workspace/coverage/default/7.sram_ctrl_bijection.4124520130 |
|
|
Jun 05 03:58:31 PM PDT 24 |
Jun 05 04:34:28 PM PDT 24 |
267618167010 ps |
| T263 |
/workspace/coverage/default/3.sram_ctrl_regwen.751004451 |
|
|
Jun 05 03:58:19 PM PDT 24 |
Jun 05 04:01:57 PM PDT 24 |
5256814426 ps |
| T264 |
/workspace/coverage/default/35.sram_ctrl_partial_access.300467404 |
|
|
Jun 05 04:00:32 PM PDT 24 |
Jun 05 04:01:38 PM PDT 24 |
1602260061 ps |
| T265 |
/workspace/coverage/default/23.sram_ctrl_partial_access.1399404494 |
|
|
Jun 05 03:59:33 PM PDT 24 |
Jun 05 03:59:53 PM PDT 24 |
1272482326 ps |
| T266 |
/workspace/coverage/default/40.sram_ctrl_mem_partial_access.1746336538 |
|
|
Jun 05 04:01:12 PM PDT 24 |
Jun 05 04:03:40 PM PDT 24 |
19693883021 ps |
| T267 |
/workspace/coverage/default/19.sram_ctrl_alert_test.3731081145 |
|
|
Jun 05 03:59:07 PM PDT 24 |
Jun 05 03:59:08 PM PDT 24 |
82715914 ps |
| T268 |
/workspace/coverage/default/30.sram_ctrl_mem_partial_access.2289406339 |
|
|
Jun 05 04:00:13 PM PDT 24 |
Jun 05 04:02:17 PM PDT 24 |
10647661478 ps |
| T269 |
/workspace/coverage/default/13.sram_ctrl_partial_access.1535033460 |
|
|
Jun 05 03:58:51 PM PDT 24 |
Jun 05 03:59:09 PM PDT 24 |
568146070 ps |
| T270 |
/workspace/coverage/default/24.sram_ctrl_alert_test.3704021742 |
|
|
Jun 05 03:59:42 PM PDT 24 |
Jun 05 03:59:44 PM PDT 24 |
17233070 ps |
| T119 |
/workspace/coverage/default/16.sram_ctrl_lc_escalation.25072447 |
|
|
Jun 05 03:59:00 PM PDT 24 |
Jun 05 04:00:05 PM PDT 24 |
14977240703 ps |
| T271 |
/workspace/coverage/default/19.sram_ctrl_ram_cfg.4044292887 |
|
|
Jun 05 03:59:12 PM PDT 24 |
Jun 05 03:59:16 PM PDT 24 |
691215129 ps |
| T272 |
/workspace/coverage/default/8.sram_ctrl_max_throughput.3357551721 |
|
|
Jun 05 03:58:31 PM PDT 24 |
Jun 05 03:58:59 PM PDT 24 |
3378850394 ps |
| T273 |
/workspace/coverage/default/35.sram_ctrl_stress_pipeline.1421064077 |
|
|
Jun 05 04:00:32 PM PDT 24 |
Jun 05 04:03:38 PM PDT 24 |
18600101376 ps |
| T274 |
/workspace/coverage/default/8.sram_ctrl_alert_test.1247143409 |
|
|
Jun 05 03:58:41 PM PDT 24 |
Jun 05 03:58:42 PM PDT 24 |
111004722 ps |
| T275 |
/workspace/coverage/default/5.sram_ctrl_mem_walk.910405509 |
|
|
Jun 05 03:58:28 PM PDT 24 |
Jun 05 04:04:47 PM PDT 24 |
89794171875 ps |
| T276 |
/workspace/coverage/default/8.sram_ctrl_partial_access.943751560 |
|
|
Jun 05 03:58:29 PM PDT 24 |
Jun 05 03:58:53 PM PDT 24 |
3666370617 ps |
| T277 |
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1691746928 |
|
|
Jun 05 03:58:41 PM PDT 24 |
Jun 05 04:01:15 PM PDT 24 |
2547431701 ps |
| T278 |
/workspace/coverage/default/22.sram_ctrl_stress_pipeline.4174996523 |
|
|
Jun 05 03:59:21 PM PDT 24 |
Jun 05 04:03:15 PM PDT 24 |
3695904263 ps |
| T279 |
/workspace/coverage/default/41.sram_ctrl_partial_access_b2b.1776638723 |
|
|
Jun 05 04:01:11 PM PDT 24 |
Jun 05 04:07:09 PM PDT 24 |
6472565466 ps |
| T280 |
/workspace/coverage/default/13.sram_ctrl_alert_test.151496356 |
|
|
Jun 05 03:58:52 PM PDT 24 |
Jun 05 03:58:54 PM PDT 24 |
39587909 ps |
| T281 |
/workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.1832710946 |
|
|
Jun 05 03:59:04 PM PDT 24 |
Jun 05 03:59:21 PM PDT 24 |
724824270 ps |
| T282 |
/workspace/coverage/default/21.sram_ctrl_alert_test.3629913356 |
|
|
Jun 05 03:59:20 PM PDT 24 |
Jun 05 03:59:21 PM PDT 24 |
16985871 ps |
| T283 |
/workspace/coverage/default/23.sram_ctrl_multiple_keys.982561132 |
|
|
Jun 05 03:59:29 PM PDT 24 |
Jun 05 04:26:59 PM PDT 24 |
32735217478 ps |
| T284 |
/workspace/coverage/default/33.sram_ctrl_alert_test.3506333041 |
|
|
Jun 05 04:00:31 PM PDT 24 |
Jun 05 04:00:32 PM PDT 24 |
14785659 ps |
| T285 |
/workspace/coverage/default/44.sram_ctrl_multiple_keys.1828485551 |
|
|
Jun 05 04:01:48 PM PDT 24 |
Jun 05 04:18:43 PM PDT 24 |
37119775230 ps |
| T286 |
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.3746938327 |
|
|
Jun 05 04:01:29 PM PDT 24 |
Jun 05 04:01:47 PM PDT 24 |
468574507 ps |
| T287 |
/workspace/coverage/default/8.sram_ctrl_smoke.647248603 |
|
|
Jun 05 03:58:31 PM PDT 24 |
Jun 05 03:58:54 PM PDT 24 |
2661491591 ps |
| T288 |
/workspace/coverage/default/46.sram_ctrl_smoke.1016769642 |
|
|
Jun 05 04:01:54 PM PDT 24 |
Jun 05 04:02:04 PM PDT 24 |
9991020118 ps |
| T289 |
/workspace/coverage/default/25.sram_ctrl_mem_partial_access.3928207757 |
|
|
Jun 05 03:59:42 PM PDT 24 |
Jun 05 04:01:02 PM PDT 24 |
2749920712 ps |
| T290 |
/workspace/coverage/default/28.sram_ctrl_lc_escalation.3654374055 |
|
|
Jun 05 03:59:56 PM PDT 24 |
Jun 05 04:00:51 PM PDT 24 |
9113093257 ps |
| T291 |
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.2176672481 |
|
|
Jun 05 03:58:42 PM PDT 24 |
Jun 05 04:03:14 PM PDT 24 |
11528686680 ps |
| T292 |
/workspace/coverage/default/16.sram_ctrl_stress_pipeline.3461734913 |
|
|
Jun 05 03:58:59 PM PDT 24 |
Jun 05 04:03:13 PM PDT 24 |
7943399604 ps |
| T293 |
/workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.2919098395 |
|
|
Jun 05 03:59:21 PM PDT 24 |
Jun 05 03:59:28 PM PDT 24 |
734489746 ps |
| T294 |
/workspace/coverage/default/36.sram_ctrl_smoke.3081030291 |
|
|
Jun 05 04:00:45 PM PDT 24 |
Jun 05 04:01:05 PM PDT 24 |
17732647869 ps |
| T295 |
/workspace/coverage/default/19.sram_ctrl_smoke.3347209119 |
|
|
Jun 05 03:59:05 PM PDT 24 |
Jun 05 03:59:15 PM PDT 24 |
1518693664 ps |
| T296 |
/workspace/coverage/default/19.sram_ctrl_partial_access.2272084663 |
|
|
Jun 05 03:59:12 PM PDT 24 |
Jun 05 03:59:46 PM PDT 24 |
445895861 ps |
| T297 |
/workspace/coverage/default/45.sram_ctrl_alert_test.3111780633 |
|
|
Jun 05 04:01:54 PM PDT 24 |
Jun 05 04:01:55 PM PDT 24 |
52625200 ps |
| T298 |
/workspace/coverage/default/28.sram_ctrl_stress_all.3029271674 |
|
|
Jun 05 03:59:56 PM PDT 24 |
Jun 05 05:23:08 PM PDT 24 |
87234488069 ps |
| T299 |
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.1362137750 |
|
|
Jun 05 04:01:45 PM PDT 24 |
Jun 05 04:15:08 PM PDT 24 |
44906732115 ps |
| T300 |
/workspace/coverage/default/7.sram_ctrl_partial_access.3986608965 |
|
|
Jun 05 03:58:31 PM PDT 24 |
Jun 05 03:59:24 PM PDT 24 |
4840415507 ps |
| T301 |
/workspace/coverage/default/30.sram_ctrl_executable.3606828687 |
|
|
Jun 05 04:00:15 PM PDT 24 |
Jun 05 04:10:01 PM PDT 24 |
10069947528 ps |
| T302 |
/workspace/coverage/default/35.sram_ctrl_regwen.843582878 |
|
|
Jun 05 04:00:42 PM PDT 24 |
Jun 05 04:05:29 PM PDT 24 |
1211486648 ps |
| T303 |
/workspace/coverage/default/31.sram_ctrl_access_during_key_req.3336511973 |
|
|
Jun 05 04:00:10 PM PDT 24 |
Jun 05 04:21:19 PM PDT 24 |
15024208601 ps |
| T304 |
/workspace/coverage/default/17.sram_ctrl_smoke.2487172168 |
|
|
Jun 05 03:59:01 PM PDT 24 |
Jun 05 03:59:15 PM PDT 24 |
1110849462 ps |
| T305 |
/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.1745337682 |
|
|
Jun 05 04:01:18 PM PDT 24 |
Jun 05 04:01:48 PM PDT 24 |
2888013164 ps |