Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	145712130	1			T1	8637		T2	480		T3	1497
triple_byte_access	2854542	1			T1	156		T2	405		T3	3419
halfword_access	4375547	1			T1	262		T2	615		T3	6335
byte_access	6129273	1			T1	331		T2	795		T3	12108
zero_access	1859288	1			T1	95		T2	215		T3	7147

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

80267429

1

T1

4787

T2

1254

T3

15188

auto[1]

80663351

1

T1

4694

T2

1256

T3

15318

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	72512629	1			T1	4356		T2	251		T3	114
auto[0]	triple_byte_access	1360919	1			T1	83		T2	189		T3	630
auto[0]	halfword_access	2140098	1			T1	138		T2	313		T3	2214
auto[0]	byte_access	3142278	1			T1	162		T2	391		T3	6505
auto[0]	zero_access	1111505	1			T1	48		T2	110		T3	5725
auto[1]	word_access	73199501	1			T1	4281		T2	229		T3	1383
auto[1]	triple_byte_access	1493623	1			T1	73		T2	216		T3	2789
auto[1]	halfword_access	2235449	1			T1	124		T2	302		T3	4121
auto[1]	byte_access	2986995	1			T1	169		T2	404		T3	5603
auto[1]	zero_access	747783	1			T1	47		T2	105		T3	1422