| T798 |
/workspace/coverage/default/12.sram_ctrl_lc_escalation.2763472990 |
|
|
Jun 05 03:58:51 PM PDT 24 |
Jun 05 04:00:45 PM PDT 24 |
98112042859 ps |
| T799 |
/workspace/coverage/default/4.sram_ctrl_partial_access_b2b.3408358383 |
|
|
Jun 05 03:58:24 PM PDT 24 |
Jun 05 04:05:07 PM PDT 24 |
14349825385 ps |
| T800 |
/workspace/coverage/default/14.sram_ctrl_lc_escalation.1444793949 |
|
|
Jun 05 03:58:52 PM PDT 24 |
Jun 05 03:59:55 PM PDT 24 |
10764025297 ps |
| T801 |
/workspace/coverage/default/37.sram_ctrl_mem_partial_access.2971358406 |
|
|
Jun 05 04:00:52 PM PDT 24 |
Jun 05 04:03:28 PM PDT 24 |
4357927522 ps |
| T802 |
/workspace/coverage/default/31.sram_ctrl_partial_access_b2b.1938886389 |
|
|
Jun 05 04:00:15 PM PDT 24 |
Jun 05 04:08:32 PM PDT 24 |
77747042986 ps |
| T803 |
/workspace/coverage/default/42.sram_ctrl_smoke.3339698266 |
|
|
Jun 05 04:01:20 PM PDT 24 |
Jun 05 04:01:29 PM PDT 24 |
3373288204 ps |
| T804 |
/workspace/coverage/default/34.sram_ctrl_max_throughput.3933713012 |
|
|
Jun 05 04:00:34 PM PDT 24 |
Jun 05 04:01:42 PM PDT 24 |
1533837353 ps |
| T805 |
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.1537642978 |
|
|
Jun 05 03:58:50 PM PDT 24 |
Jun 05 03:59:56 PM PDT 24 |
785593126 ps |
| T806 |
/workspace/coverage/default/37.sram_ctrl_stress_pipeline.1417468573 |
|
|
Jun 05 04:00:54 PM PDT 24 |
Jun 05 04:05:15 PM PDT 24 |
4353239086 ps |
| T807 |
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.641127595 |
|
|
Jun 05 03:58:45 PM PDT 24 |
Jun 05 04:02:12 PM PDT 24 |
15855762342 ps |
| T808 |
/workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.2724727455 |
|
|
Jun 05 03:59:49 PM PDT 24 |
Jun 05 04:00:00 PM PDT 24 |
725357734 ps |
| T809 |
/workspace/coverage/default/24.sram_ctrl_executable.1896492167 |
|
|
Jun 05 03:59:41 PM PDT 24 |
Jun 05 04:30:52 PM PDT 24 |
329832088944 ps |
| T810 |
/workspace/coverage/default/47.sram_ctrl_stress_all.1192100467 |
|
|
Jun 05 04:02:10 PM PDT 24 |
Jun 05 05:52:57 PM PDT 24 |
66172558000 ps |
| T811 |
/workspace/coverage/default/38.sram_ctrl_smoke.3148837223 |
|
|
Jun 05 04:00:51 PM PDT 24 |
Jun 05 04:01:10 PM PDT 24 |
1185314545 ps |
| T812 |
/workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.3975852176 |
|
|
Jun 05 04:00:03 PM PDT 24 |
Jun 05 04:00:33 PM PDT 24 |
2918465255 ps |
| T813 |
/workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.1756679457 |
|
|
Jun 05 04:00:14 PM PDT 24 |
Jun 05 04:03:13 PM PDT 24 |
4690650423 ps |
| T814 |
/workspace/coverage/default/39.sram_ctrl_mem_walk.3626825495 |
|
|
Jun 05 04:01:00 PM PDT 24 |
Jun 05 04:05:31 PM PDT 24 |
32842537473 ps |
| T815 |
/workspace/coverage/default/32.sram_ctrl_alert_test.2870847433 |
|
|
Jun 05 04:00:21 PM PDT 24 |
Jun 05 04:00:22 PM PDT 24 |
35653023 ps |
| T816 |
/workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.1360182265 |
|
|
Jun 05 04:00:44 PM PDT 24 |
Jun 05 04:01:14 PM PDT 24 |
968987167 ps |
| T817 |
/workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.1509498615 |
|
|
Jun 05 04:00:33 PM PDT 24 |
Jun 05 04:01:30 PM PDT 24 |
2107274141 ps |
| T818 |
/workspace/coverage/default/18.sram_ctrl_mem_partial_access.4164624408 |
|
|
Jun 05 03:59:03 PM PDT 24 |
Jun 05 04:01:27 PM PDT 24 |
10161866706 ps |
| T819 |
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.1867186018 |
|
|
Jun 05 03:58:44 PM PDT 24 |
Jun 05 04:03:43 PM PDT 24 |
5750433861 ps |
| T820 |
/workspace/coverage/default/9.sram_ctrl_lc_escalation.2603926539 |
|
|
Jun 05 03:58:39 PM PDT 24 |
Jun 05 03:59:45 PM PDT 24 |
40847232109 ps |
| T821 |
/workspace/coverage/default/43.sram_ctrl_lc_escalation.2393852158 |
|
|
Jun 05 04:01:37 PM PDT 24 |
Jun 05 04:01:55 PM PDT 24 |
8346411334 ps |
| T822 |
/workspace/coverage/default/6.sram_ctrl_ram_cfg.2232189547 |
|
|
Jun 05 03:58:33 PM PDT 24 |
Jun 05 03:58:37 PM PDT 24 |
434581034 ps |
| T823 |
/workspace/coverage/default/28.sram_ctrl_smoke.2518890264 |
|
|
Jun 05 03:59:54 PM PDT 24 |
Jun 05 04:01:24 PM PDT 24 |
810791643 ps |
| T824 |
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.986928794 |
|
|
Jun 05 03:58:41 PM PDT 24 |
Jun 05 04:01:17 PM PDT 24 |
10144265465 ps |
| T825 |
/workspace/coverage/default/4.sram_ctrl_stress_pipeline.3735969848 |
|
|
Jun 05 03:58:23 PM PDT 24 |
Jun 05 04:02:43 PM PDT 24 |
8590998298 ps |
| T826 |
/workspace/coverage/default/11.sram_ctrl_max_throughput.2864162109 |
|
|
Jun 05 03:58:42 PM PDT 24 |
Jun 05 03:58:49 PM PDT 24 |
1419296333 ps |
| T827 |
/workspace/coverage/default/7.sram_ctrl_multiple_keys.3415520370 |
|
|
Jun 05 03:58:30 PM PDT 24 |
Jun 05 04:19:42 PM PDT 24 |
18863816365 ps |
| T828 |
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.50635652 |
|
|
Jun 05 03:58:13 PM PDT 24 |
Jun 05 04:01:25 PM PDT 24 |
3192346053 ps |
| T829 |
/workspace/coverage/default/33.sram_ctrl_ram_cfg.1453020143 |
|
|
Jun 05 04:00:31 PM PDT 24 |
Jun 05 04:00:36 PM PDT 24 |
1346254180 ps |
| T830 |
/workspace/coverage/default/49.sram_ctrl_mem_walk.3976763946 |
|
|
Jun 05 04:02:21 PM PDT 24 |
Jun 05 04:05:04 PM PDT 24 |
9093131976 ps |
| T831 |
/workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.3621310212 |
|
|
Jun 05 04:00:51 PM PDT 24 |
Jun 05 04:01:57 PM PDT 24 |
3116703912 ps |
| T832 |
/workspace/coverage/default/0.sram_ctrl_lc_escalation.3796703702 |
|
|
Jun 05 03:58:10 PM PDT 24 |
Jun 05 03:58:42 PM PDT 24 |
24641760686 ps |
| T833 |
/workspace/coverage/default/38.sram_ctrl_alert_test.2598642107 |
|
|
Jun 05 04:00:57 PM PDT 24 |
Jun 05 04:00:59 PM PDT 24 |
15435477 ps |
| T834 |
/workspace/coverage/default/2.sram_ctrl_mem_walk.1299474347 |
|
|
Jun 05 03:58:19 PM PDT 24 |
Jun 05 04:00:26 PM PDT 24 |
3662022934 ps |
| T835 |
/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.589131462 |
|
|
Jun 05 03:59:14 PM PDT 24 |
Jun 05 03:59:46 PM PDT 24 |
764316081 ps |
| T836 |
/workspace/coverage/default/47.sram_ctrl_mem_walk.1701150119 |
|
|
Jun 05 04:02:10 PM PDT 24 |
Jun 05 04:04:21 PM PDT 24 |
2325460405 ps |
| T837 |
/workspace/coverage/default/10.sram_ctrl_max_throughput.2402018067 |
|
|
Jun 05 03:58:40 PM PDT 24 |
Jun 05 03:58:57 PM PDT 24 |
1477657389 ps |
| T838 |
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.4129200205 |
|
|
Jun 05 04:01:26 PM PDT 24 |
Jun 05 04:07:24 PM PDT 24 |
16205555547 ps |
| T839 |
/workspace/coverage/default/26.sram_ctrl_alert_test.3967670609 |
|
|
Jun 05 03:59:47 PM PDT 24 |
Jun 05 03:59:48 PM PDT 24 |
35568562 ps |
| T840 |
/workspace/coverage/default/26.sram_ctrl_lc_escalation.1449968584 |
|
|
Jun 05 03:59:40 PM PDT 24 |
Jun 05 04:00:18 PM PDT 24 |
11903909898 ps |
| T841 |
/workspace/coverage/default/41.sram_ctrl_executable.3221524359 |
|
|
Jun 05 04:01:16 PM PDT 24 |
Jun 05 04:16:37 PM PDT 24 |
8099756859 ps |
| T842 |
/workspace/coverage/default/15.sram_ctrl_executable.3680184902 |
|
|
Jun 05 03:58:56 PM PDT 24 |
Jun 05 04:07:38 PM PDT 24 |
16679888548 ps |
| T843 |
/workspace/coverage/default/30.sram_ctrl_access_during_key_req.4113189067 |
|
|
Jun 05 04:00:05 PM PDT 24 |
Jun 05 04:09:16 PM PDT 24 |
111024333921 ps |
| T844 |
/workspace/coverage/default/28.sram_ctrl_ram_cfg.575415776 |
|
|
Jun 05 03:59:55 PM PDT 24 |
Jun 05 03:59:59 PM PDT 24 |
671363474 ps |
| T845 |
/workspace/coverage/default/9.sram_ctrl_multiple_keys.3884879943 |
|
|
Jun 05 03:58:44 PM PDT 24 |
Jun 05 04:01:11 PM PDT 24 |
31340054996 ps |
| T846 |
/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.3121943666 |
|
|
Jun 05 03:59:20 PM PDT 24 |
Jun 05 04:03:06 PM PDT 24 |
4653416149 ps |
| T847 |
/workspace/coverage/default/42.sram_ctrl_ram_cfg.3955790829 |
|
|
Jun 05 04:01:32 PM PDT 24 |
Jun 05 04:01:36 PM PDT 24 |
347406378 ps |
| T848 |
/workspace/coverage/default/27.sram_ctrl_access_during_key_req.146571769 |
|
|
Jun 05 03:59:47 PM PDT 24 |
Jun 05 04:15:33 PM PDT 24 |
13585847528 ps |
| T849 |
/workspace/coverage/default/22.sram_ctrl_multiple_keys.1553557578 |
|
|
Jun 05 03:59:21 PM PDT 24 |
Jun 05 04:21:43 PM PDT 24 |
39862972198 ps |
| T850 |
/workspace/coverage/default/33.sram_ctrl_partial_access.969274520 |
|
|
Jun 05 04:00:26 PM PDT 24 |
Jun 05 04:00:50 PM PDT 24 |
6511766729 ps |
| T851 |
/workspace/coverage/default/4.sram_ctrl_mem_walk.627239608 |
|
|
Jun 05 03:58:21 PM PDT 24 |
Jun 05 04:03:18 PM PDT 24 |
52510890083 ps |
| T852 |
/workspace/coverage/default/37.sram_ctrl_alert_test.1129926519 |
|
|
Jun 05 04:00:51 PM PDT 24 |
Jun 05 04:00:53 PM PDT 24 |
34995826 ps |
| T853 |
/workspace/coverage/default/29.sram_ctrl_mem_walk.2854495357 |
|
|
Jun 05 04:00:05 PM PDT 24 |
Jun 05 04:05:12 PM PDT 24 |
14279787200 ps |
| T854 |
/workspace/coverage/default/31.sram_ctrl_smoke.3517872496 |
|
|
Jun 05 04:00:05 PM PDT 24 |
Jun 05 04:00:21 PM PDT 24 |
527441558 ps |
| T855 |
/workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.854452147 |
|
|
Jun 05 04:00:32 PM PDT 24 |
Jun 05 04:02:41 PM PDT 24 |
5143464110 ps |
| T856 |
/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.2458565489 |
|
|
Jun 05 03:58:53 PM PDT 24 |
Jun 05 03:59:50 PM PDT 24 |
4382568646 ps |
| T857 |
/workspace/coverage/default/2.sram_ctrl_stress_all.222707284 |
|
|
Jun 05 03:58:21 PM PDT 24 |
Jun 05 05:30:42 PM PDT 24 |
262796022156 ps |
| T858 |
/workspace/coverage/default/4.sram_ctrl_regwen.2597807848 |
|
|
Jun 05 03:58:23 PM PDT 24 |
Jun 05 04:13:17 PM PDT 24 |
6494390065 ps |
| T859 |
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.526211591 |
|
|
Jun 05 03:58:11 PM PDT 24 |
Jun 05 04:04:18 PM PDT 24 |
6273932703 ps |
| T860 |
/workspace/coverage/default/38.sram_ctrl_partial_access_b2b.2167797520 |
|
|
Jun 05 04:00:52 PM PDT 24 |
Jun 05 04:05:54 PM PDT 24 |
23548798504 ps |
| T861 |
/workspace/coverage/default/24.sram_ctrl_mem_walk.2031965502 |
|
|
Jun 05 03:59:42 PM PDT 24 |
Jun 05 04:02:17 PM PDT 24 |
10953838517 ps |
| T862 |
/workspace/coverage/default/27.sram_ctrl_max_throughput.3628203277 |
|
|
Jun 05 03:59:49 PM PDT 24 |
Jun 05 04:00:07 PM PDT 24 |
737979159 ps |
| T863 |
/workspace/coverage/default/30.sram_ctrl_partial_access_b2b.2625548033 |
|
|
Jun 05 04:00:06 PM PDT 24 |
Jun 05 04:04:04 PM PDT 24 |
18089077810 ps |
| T864 |
/workspace/coverage/default/17.sram_ctrl_mem_walk.1894282386 |
|
|
Jun 05 03:59:07 PM PDT 24 |
Jun 05 04:03:52 PM PDT 24 |
21871861599 ps |
| T865 |
/workspace/coverage/default/41.sram_ctrl_stress_all.3642458758 |
|
|
Jun 05 04:01:16 PM PDT 24 |
Jun 05 05:25:06 PM PDT 24 |
263579858389 ps |
| T866 |
/workspace/coverage/default/34.sram_ctrl_stress_all.3133960963 |
|
|
Jun 05 04:00:32 PM PDT 24 |
Jun 05 04:38:56 PM PDT 24 |
43003829444 ps |
| T867 |
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.2942207321 |
|
|
Jun 05 04:02:05 PM PDT 24 |
Jun 05 04:08:08 PM PDT 24 |
21496058227 ps |
| T868 |
/workspace/coverage/default/43.sram_ctrl_smoke.268949664 |
|
|
Jun 05 04:01:30 PM PDT 24 |
Jun 05 04:01:52 PM PDT 24 |
4676278288 ps |
| T869 |
/workspace/coverage/default/13.sram_ctrl_lc_escalation.1189764308 |
|
|
Jun 05 03:58:52 PM PDT 24 |
Jun 05 04:00:04 PM PDT 24 |
43704335659 ps |
| T870 |
/workspace/coverage/default/43.sram_ctrl_stress_all.2852245813 |
|
|
Jun 05 04:01:35 PM PDT 24 |
Jun 05 04:55:49 PM PDT 24 |
38389840020 ps |
| T871 |
/workspace/coverage/default/28.sram_ctrl_mem_partial_access.3197988895 |
|
|
Jun 05 03:59:56 PM PDT 24 |
Jun 05 04:01:16 PM PDT 24 |
2657351881 ps |
| T872 |
/workspace/coverage/default/11.sram_ctrl_lc_escalation.1849036347 |
|
|
Jun 05 03:58:40 PM PDT 24 |
Jun 05 03:58:53 PM PDT 24 |
3755443016 ps |
| T873 |
/workspace/coverage/default/45.sram_ctrl_multiple_keys.202509823 |
|
|
Jun 05 04:01:46 PM PDT 24 |
Jun 05 04:16:51 PM PDT 24 |
31367504829 ps |
| T874 |
/workspace/coverage/default/33.sram_ctrl_smoke.1190625159 |
|
|
Jun 05 04:00:20 PM PDT 24 |
Jun 05 04:00:29 PM PDT 24 |
782963523 ps |
| T108 |
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3913479133 |
|
|
Jun 05 03:58:33 PM PDT 24 |
Jun 05 03:58:58 PM PDT 24 |
1734845102 ps |
| T875 |
/workspace/coverage/default/48.sram_ctrl_alert_test.639440340 |
|
|
Jun 05 04:02:11 PM PDT 24 |
Jun 05 04:02:12 PM PDT 24 |
12609248 ps |
| T876 |
/workspace/coverage/default/26.sram_ctrl_stress_pipeline.3862346714 |
|
|
Jun 05 03:59:39 PM PDT 24 |
Jun 05 04:06:24 PM PDT 24 |
27574670763 ps |
| T877 |
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.4077547852 |
|
|
Jun 05 04:02:18 PM PDT 24 |
Jun 05 04:08:15 PM PDT 24 |
59401099937 ps |
| T878 |
/workspace/coverage/default/29.sram_ctrl_lc_escalation.706960745 |
|
|
Jun 05 04:00:15 PM PDT 24 |
Jun 05 04:01:28 PM PDT 24 |
45568590090 ps |
| T879 |
/workspace/coverage/default/14.sram_ctrl_stress_all.3250480872 |
|
|
Jun 05 03:58:50 PM PDT 24 |
Jun 05 05:19:51 PM PDT 24 |
62356292857 ps |
| T880 |
/workspace/coverage/default/15.sram_ctrl_alert_test.1898478232 |
|
|
Jun 05 03:59:05 PM PDT 24 |
Jun 05 03:59:07 PM PDT 24 |
29126109 ps |
| T881 |
/workspace/coverage/default/35.sram_ctrl_access_during_key_req.2715952803 |
|
|
Jun 05 04:00:42 PM PDT 24 |
Jun 05 04:19:54 PM PDT 24 |
63880031929 ps |
| T882 |
/workspace/coverage/default/35.sram_ctrl_mem_partial_access.115929407 |
|
|
Jun 05 04:00:42 PM PDT 24 |
Jun 05 04:02:43 PM PDT 24 |
6549693483 ps |
| T883 |
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.3989282882 |
|
|
Jun 05 04:02:12 PM PDT 24 |
Jun 05 04:02:31 PM PDT 24 |
383226735 ps |
| T884 |
/workspace/coverage/default/42.sram_ctrl_alert_test.1098903977 |
|
|
Jun 05 04:01:30 PM PDT 24 |
Jun 05 04:01:31 PM PDT 24 |
20493097 ps |
| T885 |
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.2566190805 |
|
|
Jun 05 03:58:40 PM PDT 24 |
Jun 05 03:59:58 PM PDT 24 |
1453382680 ps |
| T886 |
/workspace/coverage/default/45.sram_ctrl_executable.261173770 |
|
|
Jun 05 04:01:54 PM PDT 24 |
Jun 05 04:17:30 PM PDT 24 |
18325058291 ps |
| T887 |
/workspace/coverage/default/11.sram_ctrl_bijection.2694546509 |
|
|
Jun 05 03:58:44 PM PDT 24 |
Jun 05 04:39:26 PM PDT 24 |
66251536344 ps |
| T888 |
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.3810546008 |
|
|
Jun 05 03:58:27 PM PDT 24 |
Jun 05 03:58:55 PM PDT 24 |
2998276446 ps |
| T889 |
/workspace/coverage/default/33.sram_ctrl_stress_all.67548303 |
|
|
Jun 05 04:00:31 PM PDT 24 |
Jun 05 06:07:11 PM PDT 24 |
159902205379 ps |
| T890 |
/workspace/coverage/default/48.sram_ctrl_stress_all.3480131634 |
|
|
Jun 05 04:02:12 PM PDT 24 |
Jun 05 04:55:59 PM PDT 24 |
353320998757 ps |
| T891 |
/workspace/coverage/default/33.sram_ctrl_executable.141254150 |
|
|
Jun 05 04:00:31 PM PDT 24 |
Jun 05 04:10:46 PM PDT 24 |
38104052527 ps |
| T892 |
/workspace/coverage/default/47.sram_ctrl_ram_cfg.3730641055 |
|
|
Jun 05 04:02:10 PM PDT 24 |
Jun 05 04:02:14 PM PDT 24 |
414813386 ps |
| T893 |
/workspace/coverage/default/41.sram_ctrl_lc_escalation.4278523641 |
|
|
Jun 05 04:01:17 PM PDT 24 |
Jun 05 04:02:41 PM PDT 24 |
27826555209 ps |
| T894 |
/workspace/coverage/default/33.sram_ctrl_lc_escalation.3715681075 |
|
|
Jun 05 04:00:23 PM PDT 24 |
Jun 05 04:01:15 PM PDT 24 |
23208869367 ps |
| T895 |
/workspace/coverage/default/9.sram_ctrl_smoke.4109121759 |
|
|
Jun 05 03:58:41 PM PDT 24 |
Jun 05 03:59:00 PM PDT 24 |
1064072896 ps |
| T896 |
/workspace/coverage/default/11.sram_ctrl_multiple_keys.2494291962 |
|
|
Jun 05 03:58:42 PM PDT 24 |
Jun 05 04:22:15 PM PDT 24 |
108366402103 ps |
| T897 |
/workspace/coverage/default/13.sram_ctrl_mem_partial_access.3099305062 |
|
|
Jun 05 03:58:50 PM PDT 24 |
Jun 05 04:01:28 PM PDT 24 |
5038337264 ps |
| T898 |
/workspace/coverage/default/22.sram_ctrl_ram_cfg.3188950208 |
|
|
Jun 05 03:59:22 PM PDT 24 |
Jun 05 03:59:26 PM PDT 24 |
681198010 ps |
| T899 |
/workspace/coverage/default/18.sram_ctrl_stress_pipeline.3591861167 |
|
|
Jun 05 03:59:03 PM PDT 24 |
Jun 05 04:02:44 PM PDT 24 |
6847061805 ps |
| T900 |
/workspace/coverage/default/35.sram_ctrl_alert_test.2640272182 |
|
|
Jun 05 04:00:40 PM PDT 24 |
Jun 05 04:00:41 PM PDT 24 |
33354307 ps |
| T901 |
/workspace/coverage/default/21.sram_ctrl_stress_all.1194104924 |
|
|
Jun 05 03:59:23 PM PDT 24 |
Jun 05 04:47:59 PM PDT 24 |
107182963275 ps |
| T902 |
/workspace/coverage/default/5.sram_ctrl_bijection.2917431824 |
|
|
Jun 05 03:58:31 PM PDT 24 |
Jun 05 04:10:43 PM PDT 24 |
33828275310 ps |
| T903 |
/workspace/coverage/default/19.sram_ctrl_stress_all.2570363150 |
|
|
Jun 05 03:59:05 PM PDT 24 |
Jun 05 05:01:52 PM PDT 24 |
57011474487 ps |
| T904 |
/workspace/coverage/default/5.sram_ctrl_lc_escalation.2574798641 |
|
|
Jun 05 03:58:31 PM PDT 24 |
Jun 05 03:59:53 PM PDT 24 |
13619903304 ps |
| T905 |
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.3523935724 |
|
|
Jun 05 04:02:25 PM PDT 24 |
Jun 05 04:05:58 PM PDT 24 |
11591442772 ps |
| T906 |
/workspace/coverage/default/49.sram_ctrl_stress_all.1756211546 |
|
|
Jun 05 04:02:26 PM PDT 24 |
Jun 05 05:26:54 PM PDT 24 |
260226311638 ps |
| T907 |
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2178679784 |
|
|
Jun 05 03:58:41 PM PDT 24 |
Jun 05 03:59:53 PM PDT 24 |
4718027027 ps |
| T34 |
/workspace/coverage/default/1.sram_ctrl_sec_cm.3336346628 |
|
|
Jun 05 03:58:19 PM PDT 24 |
Jun 05 03:58:23 PM PDT 24 |
276124582 ps |
| T908 |
/workspace/coverage/default/24.sram_ctrl_lc_escalation.2873443573 |
|
|
Jun 05 03:59:41 PM PDT 24 |
Jun 05 04:00:15 PM PDT 24 |
38276662985 ps |
| T909 |
/workspace/coverage/default/38.sram_ctrl_mem_partial_access.2753335784 |
|
|
Jun 05 04:00:51 PM PDT 24 |
Jun 05 04:03:27 PM PDT 24 |
5813438028 ps |
| T910 |
/workspace/coverage/default/26.sram_ctrl_multiple_keys.1385414917 |
|
|
Jun 05 03:59:41 PM PDT 24 |
Jun 05 04:03:45 PM PDT 24 |
3211042770 ps |
| T911 |
/workspace/coverage/default/7.sram_ctrl_max_throughput.2064447425 |
|
|
Jun 05 03:58:31 PM PDT 24 |
Jun 05 03:58:55 PM PDT 24 |
1378234549 ps |
| T912 |
/workspace/coverage/default/4.sram_ctrl_stress_all.807641409 |
|
|
Jun 05 03:58:23 PM PDT 24 |
Jun 05 04:36:33 PM PDT 24 |
24505471705 ps |
| T913 |
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.3040570759 |
|
|
Jun 05 03:58:53 PM PDT 24 |
Jun 05 04:04:13 PM PDT 24 |
13402122668 ps |
| T914 |
/workspace/coverage/default/24.sram_ctrl_access_during_key_req.3831827743 |
|
|
Jun 05 03:59:42 PM PDT 24 |
Jun 05 04:00:16 PM PDT 24 |
26784720608 ps |
| T915 |
/workspace/coverage/default/33.sram_ctrl_regwen.64857718 |
|
|
Jun 05 04:00:30 PM PDT 24 |
Jun 05 04:17:56 PM PDT 24 |
9567918947 ps |
| T916 |
/workspace/coverage/default/32.sram_ctrl_stress_pipeline.2021778282 |
|
|
Jun 05 04:00:16 PM PDT 24 |
Jun 05 04:04:59 PM PDT 24 |
70937813974 ps |
| T917 |
/workspace/coverage/default/36.sram_ctrl_regwen.1463668252 |
|
|
Jun 05 04:00:45 PM PDT 24 |
Jun 05 04:17:50 PM PDT 24 |
28596671593 ps |
| T918 |
/workspace/coverage/default/8.sram_ctrl_bijection.2211863826 |
|
|
Jun 05 03:58:33 PM PDT 24 |
Jun 05 04:41:02 PM PDT 24 |
221023854195 ps |
| T919 |
/workspace/coverage/default/42.sram_ctrl_stress_all.17660627 |
|
|
Jun 05 04:01:31 PM PDT 24 |
Jun 05 05:31:39 PM PDT 24 |
76505679875 ps |
| T920 |
/workspace/coverage/default/42.sram_ctrl_max_throughput.677812894 |
|
|
Jun 05 04:01:16 PM PDT 24 |
Jun 05 04:01:52 PM PDT 24 |
1498137057 ps |
| T921 |
/workspace/coverage/default/6.sram_ctrl_multiple_keys.1320840530 |
|
|
Jun 05 03:58:34 PM PDT 24 |
Jun 05 04:13:00 PM PDT 24 |
24534483677 ps |
| T922 |
/workspace/coverage/default/5.sram_ctrl_stress_all.284357749 |
|
|
Jun 05 03:58:32 PM PDT 24 |
Jun 05 05:04:17 PM PDT 24 |
1068101483645 ps |
| T923 |
/workspace/coverage/default/17.sram_ctrl_bijection.1113300479 |
|
|
Jun 05 03:59:04 PM PDT 24 |
Jun 05 04:28:32 PM PDT 24 |
294948710078 ps |
| T924 |
/workspace/coverage/default/3.sram_ctrl_access_during_key_req.2827496007 |
|
|
Jun 05 03:58:21 PM PDT 24 |
Jun 05 04:22:10 PM PDT 24 |
20329487544 ps |
| T925 |
/workspace/coverage/default/17.sram_ctrl_multiple_keys.2838128724 |
|
|
Jun 05 03:59:04 PM PDT 24 |
Jun 05 04:04:59 PM PDT 24 |
28115785759 ps |
| T926 |
/workspace/coverage/default/39.sram_ctrl_executable.2687641620 |
|
|
Jun 05 04:00:58 PM PDT 24 |
Jun 05 04:17:12 PM PDT 24 |
34091372266 ps |
| T927 |
/workspace/coverage/default/0.sram_ctrl_multiple_keys.4000486858 |
|
|
Jun 05 03:58:16 PM PDT 24 |
Jun 05 04:05:51 PM PDT 24 |
11871221993 ps |
| T928 |
/workspace/coverage/default/35.sram_ctrl_ram_cfg.23266545 |
|
|
Jun 05 04:00:42 PM PDT 24 |
Jun 05 04:00:48 PM PDT 24 |
3344572706 ps |
| T929 |
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.3055886212 |
|
|
Jun 05 03:58:32 PM PDT 24 |
Jun 05 03:59:24 PM PDT 24 |
756602224 ps |
| T930 |
/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.307933949 |
|
|
Jun 05 04:00:41 PM PDT 24 |
Jun 05 04:05:25 PM PDT 24 |
14379746215 ps |
| T931 |
/workspace/coverage/default/20.sram_ctrl_ram_cfg.1027913939 |
|
|
Jun 05 03:59:14 PM PDT 24 |
Jun 05 03:59:18 PM PDT 24 |
346067752 ps |
| T932 |
/workspace/coverage/default/16.sram_ctrl_regwen.1776469968 |
|
|
Jun 05 03:58:59 PM PDT 24 |
Jun 05 04:16:10 PM PDT 24 |
85929087028 ps |
| T933 |
/workspace/coverage/default/39.sram_ctrl_access_during_key_req.3991844730 |
|
|
Jun 05 04:01:03 PM PDT 24 |
Jun 05 04:01:32 PM PDT 24 |
3008792381 ps |
| T934 |
/workspace/coverage/default/31.sram_ctrl_bijection.2754366698 |
|
|
Jun 05 04:00:04 PM PDT 24 |
Jun 05 04:27:40 PM PDT 24 |
93816368619 ps |
| T935 |
/workspace/coverage/default/1.sram_ctrl_alert_test.1623113359 |
|
|
Jun 05 03:58:20 PM PDT 24 |
Jun 05 03:58:21 PM PDT 24 |
14399317 ps |
| T936 |
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.3169428328 |
|
|
Jun 05 04:01:46 PM PDT 24 |
Jun 05 04:04:39 PM PDT 24 |
7533478001 ps |
| T937 |
/workspace/coverage/default/37.sram_ctrl_bijection.3309772893 |
|
|
Jun 05 04:00:52 PM PDT 24 |
Jun 05 04:31:32 PM PDT 24 |
27411214507 ps |
| T938 |
/workspace/coverage/default/45.sram_ctrl_lc_escalation.714764480 |
|
|
Jun 05 04:01:43 PM PDT 24 |
Jun 05 04:02:45 PM PDT 24 |
49901569887 ps |
| T939 |
/workspace/coverage/default/31.sram_ctrl_lc_escalation.2367156698 |
|
|
Jun 05 04:00:05 PM PDT 24 |
Jun 05 04:00:49 PM PDT 24 |
12102022355 ps |
| T940 |
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.3931910314 |
|
|
Jun 05 03:58:11 PM PDT 24 |
Jun 05 04:00:46 PM PDT 24 |
7070118748 ps |
| T941 |
/workspace/coverage/default/38.sram_ctrl_max_throughput.1640730207 |
|
|
Jun 05 04:00:52 PM PDT 24 |
Jun 05 04:01:34 PM PDT 24 |
1468071444 ps |
| T942 |
/workspace/coverage/default/30.sram_ctrl_max_throughput.557857861 |
|
|
Jun 05 04:00:04 PM PDT 24 |
Jun 05 04:00:13 PM PDT 24 |
4230798303 ps |
| T943 |
/workspace/coverage/default/26.sram_ctrl_bijection.3993199759 |
|
|
Jun 05 03:59:41 PM PDT 24 |
Jun 05 04:13:34 PM PDT 24 |
324628376649 ps |
| T63 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3475563122 |
|
|
Jun 05 03:55:36 PM PDT 24 |
Jun 05 03:55:39 PM PDT 24 |
71955228 ps |
| T64 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.4136153495 |
|
|
Jun 05 03:55:34 PM PDT 24 |
Jun 05 03:56:38 PM PDT 24 |
32109380479 ps |
| T65 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.762870160 |
|
|
Jun 05 03:55:42 PM PDT 24 |
Jun 05 03:56:34 PM PDT 24 |
7105594909 ps |
| T59 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3921227727 |
|
|
Jun 05 03:55:35 PM PDT 24 |
Jun 05 03:55:38 PM PDT 24 |
1339987276 ps |
| T72 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.622715812 |
|
|
Jun 05 03:55:45 PM PDT 24 |
Jun 05 03:55:46 PM PDT 24 |
26959106 ps |
| T116 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.4099579160 |
|
|
Jun 05 03:55:38 PM PDT 24 |
Jun 05 03:55:42 PM PDT 24 |
324180178 ps |
| T60 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.471906123 |
|
|
Jun 05 03:55:47 PM PDT 24 |
Jun 05 03:55:50 PM PDT 24 |
159616158 ps |
| T94 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2445472148 |
|
|
Jun 05 03:55:46 PM PDT 24 |
Jun 05 03:55:47 PM PDT 24 |
17457291 ps |
| T103 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.851611071 |
|
|
Jun 05 03:55:25 PM PDT 24 |
Jun 05 03:55:26 PM PDT 24 |
24588684 ps |
| T73 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.479346448 |
|
|
Jun 05 03:55:42 PM PDT 24 |
Jun 05 03:55:44 PM PDT 24 |
15050558 ps |
| T74 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.828827087 |
|
|
Jun 05 03:55:26 PM PDT 24 |
Jun 05 03:55:30 PM PDT 24 |
1190965486 ps |
| T95 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2792367615 |
|
|
Jun 05 03:55:47 PM PDT 24 |
Jun 05 03:55:48 PM PDT 24 |
20142958 ps |
| T944 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2909843874 |
|
|
Jun 05 03:55:39 PM PDT 24 |
Jun 05 03:55:44 PM PDT 24 |
380130845 ps |
| T75 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.679476830 |
|
|
Jun 05 03:55:42 PM PDT 24 |
Jun 05 03:55:44 PM PDT 24 |
13704219 ps |
| T76 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2049057086 |
|
|
Jun 05 03:55:35 PM PDT 24 |
Jun 05 03:55:36 PM PDT 24 |
15333180 ps |
| T945 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1190880867 |
|
|
Jun 05 03:55:28 PM PDT 24 |
Jun 05 03:55:32 PM PDT 24 |
365444600 ps |
| T96 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.4232771256 |
|
|
Jun 05 03:55:47 PM PDT 24 |
Jun 05 03:56:20 PM PDT 24 |
15384560254 ps |
| T77 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2559434724 |
|
|
Jun 05 03:55:44 PM PDT 24 |
Jun 05 03:55:46 PM PDT 24 |
20699067 ps |
| T61 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.4006918621 |
|
|
Jun 05 03:55:40 PM PDT 24 |
Jun 05 03:55:43 PM PDT 24 |
1932537781 ps |
| T78 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1379153151 |
|
|
Jun 05 03:55:27 PM PDT 24 |
Jun 05 03:56:20 PM PDT 24 |
7123986505 ps |
| T946 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3819838851 |
|
|
Jun 05 03:55:25 PM PDT 24 |
Jun 05 03:55:30 PM PDT 24 |
497635159 ps |
| T97 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.780234096 |
|
|
Jun 05 03:55:43 PM PDT 24 |
Jun 05 03:56:40 PM PDT 24 |
29397140980 ps |
| T947 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.4255778698 |
|
|
Jun 05 03:55:40 PM PDT 24 |
Jun 05 03:55:45 PM PDT 24 |
139096089 ps |
| T948 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1594058265 |
|
|
Jun 05 03:55:46 PM PDT 24 |
Jun 05 03:55:50 PM PDT 24 |
756034032 ps |
| T949 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.386743987 |
|
|
Jun 05 03:55:40 PM PDT 24 |
Jun 05 03:55:45 PM PDT 24 |
368342143 ps |
| T121 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1105631562 |
|
|
Jun 05 03:55:43 PM PDT 24 |
Jun 05 03:55:46 PM PDT 24 |
606686559 ps |
| T950 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2941727140 |
|
|
Jun 05 03:55:40 PM PDT 24 |
Jun 05 03:55:44 PM PDT 24 |
77642977 ps |
| T951 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.987758586 |
|
|
Jun 05 03:55:39 PM PDT 24 |
Jun 05 03:55:42 PM PDT 24 |
48961290 ps |
| T122 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.422664177 |
|
|
Jun 05 03:55:29 PM PDT 24 |
Jun 05 03:55:31 PM PDT 24 |
341427966 ps |
| T952 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1316140914 |
|
|
Jun 05 03:55:35 PM PDT 24 |
Jun 05 03:55:36 PM PDT 24 |
25230283 ps |
| T120 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.4039445058 |
|
|
Jun 05 03:55:41 PM PDT 24 |
Jun 05 03:55:44 PM PDT 24 |
111483495 ps |
| T79 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1034504651 |
|
|
Jun 05 03:55:35 PM PDT 24 |
Jun 05 03:56:04 PM PDT 24 |
3814428615 ps |
| T953 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3017999128 |
|
|
Jun 05 03:55:26 PM PDT 24 |
Jun 05 03:55:30 PM PDT 24 |
58084788 ps |
| T98 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1912858825 |
|
|
Jun 05 03:55:39 PM PDT 24 |
Jun 05 03:55:41 PM PDT 24 |
17773626 ps |
| T954 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1460374387 |
|
|
Jun 05 03:55:47 PM PDT 24 |
Jun 05 03:55:52 PM PDT 24 |
357231383 ps |
| T955 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.548364080 |
|
|
Jun 05 03:55:24 PM PDT 24 |
Jun 05 03:55:27 PM PDT 24 |
47700518 ps |
| T956 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3783615282 |
|
|
Jun 05 03:55:49 PM PDT 24 |
Jun 05 03:55:51 PM PDT 24 |
37604607 ps |
| T124 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3012185645 |
|
|
Jun 05 03:55:27 PM PDT 24 |
Jun 05 03:55:30 PM PDT 24 |
277071782 ps |
| T957 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3294954461 |
|
|
Jun 05 03:55:43 PM PDT 24 |
Jun 05 03:56:40 PM PDT 24 |
7400627957 ps |
| T81 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1655666118 |
|
|
Jun 05 03:55:37 PM PDT 24 |
Jun 05 03:56:46 PM PDT 24 |
47008375674 ps |
| T958 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.530355743 |
|
|
Jun 05 03:55:23 PM PDT 24 |
Jun 05 03:55:28 PM PDT 24 |
120429374 ps |
| T959 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3216324407 |
|
|
Jun 05 03:55:25 PM PDT 24 |
Jun 05 03:55:27 PM PDT 24 |
67477084 ps |
| T960 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1339494932 |
|
|
Jun 05 03:55:42 PM PDT 24 |
Jun 05 03:55:44 PM PDT 24 |
43190285 ps |
| T123 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2445649875 |
|
|
Jun 05 03:55:28 PM PDT 24 |
Jun 05 03:55:30 PM PDT 24 |
139964023 ps |
| T82 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2572661053 |
|
|
Jun 05 03:55:37 PM PDT 24 |
Jun 05 03:55:39 PM PDT 24 |
11057072 ps |
| T83 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3293459224 |
|
|
Jun 05 03:55:39 PM PDT 24 |
Jun 05 03:55:41 PM PDT 24 |
17571730 ps |
| T961 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1876514719 |
|
|
Jun 05 03:55:39 PM PDT 24 |
Jun 05 03:55:41 PM PDT 24 |
17856667 ps |
| T84 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.4089820508 |
|
|
Jun 05 03:55:45 PM PDT 24 |
Jun 05 03:56:38 PM PDT 24 |
29333627861 ps |
| T962 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1841843813 |
|
|
Jun 05 03:55:39 PM PDT 24 |
Jun 05 03:55:42 PM PDT 24 |
1618292089 ps |
| T963 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2887825326 |
|
|
Jun 05 03:55:33 PM PDT 24 |
Jun 05 03:55:34 PM PDT 24 |
17098056 ps |
| T964 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.112128569 |
|
|
Jun 05 03:55:33 PM PDT 24 |
Jun 05 03:55:37 PM PDT 24 |
363953314 ps |
| T965 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3492487348 |
|
|
Jun 05 03:55:38 PM PDT 24 |
Jun 05 03:55:40 PM PDT 24 |
33673440 ps |
| T966 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1277255422 |
|
|
Jun 05 03:55:42 PM PDT 24 |
Jun 05 03:55:46 PM PDT 24 |
1719746640 ps |
| T86 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2840180150 |
|
|
Jun 05 03:55:25 PM PDT 24 |
Jun 05 03:56:29 PM PDT 24 |
50281435099 ps |
| T967 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2677087092 |
|
|
Jun 05 03:55:46 PM PDT 24 |
Jun 05 03:55:50 PM PDT 24 |
1155441769 ps |
| T968 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1427001019 |
|
|
Jun 05 03:55:34 PM PDT 24 |
Jun 05 03:55:36 PM PDT 24 |
35131027 ps |
| T969 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.4172291557 |
|
|
Jun 05 03:55:42 PM PDT 24 |
Jun 05 03:55:45 PM PDT 24 |
340150817 ps |
| T87 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.4154140435 |
|
|
Jun 05 03:55:38 PM PDT 24 |
Jun 05 03:56:04 PM PDT 24 |
15450693661 ps |
| T970 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2778084792 |
|
|
Jun 05 03:55:35 PM PDT 24 |
Jun 05 03:55:37 PM PDT 24 |
20977419 ps |
| T971 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1150636376 |
|
|
Jun 05 03:55:35 PM PDT 24 |
Jun 05 03:55:40 PM PDT 24 |
6995365101 ps |
| T972 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2052201702 |
|
|
Jun 05 03:55:40 PM PDT 24 |
Jun 05 03:55:44 PM PDT 24 |
1386466288 ps |
| T973 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1984192243 |
|
|
Jun 05 03:55:46 PM PDT 24 |
Jun 05 03:55:48 PM PDT 24 |
19887683 ps |
| T974 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1291142141 |
|
|
Jun 05 03:55:40 PM PDT 24 |
Jun 05 03:55:42 PM PDT 24 |
21913320 ps |
| T975 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.782619765 |
|
|
Jun 05 03:55:36 PM PDT 24 |
Jun 05 03:55:41 PM PDT 24 |
1476934883 ps |
| T976 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2941754319 |
|
|
Jun 05 03:55:50 PM PDT 24 |
Jun 05 03:55:55 PM PDT 24 |
1384856119 ps |
| T977 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.4057499863 |
|
|
Jun 05 03:55:47 PM PDT 24 |
Jun 05 03:55:49 PM PDT 24 |
51088396 ps |
| T978 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.683710957 |
|
|
Jun 05 03:55:46 PM PDT 24 |
Jun 05 03:55:47 PM PDT 24 |
34776751 ps |
| T979 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3152090954 |
|
|
Jun 05 03:55:35 PM PDT 24 |
Jun 05 03:55:39 PM PDT 24 |
260763514 ps |
| T88 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.892481895 |
|
|
Jun 05 03:55:50 PM PDT 24 |
Jun 05 03:56:18 PM PDT 24 |
3880604753 ps |
| T980 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3581672348 |
|
|
Jun 05 03:55:42 PM PDT 24 |
Jun 05 03:55:45 PM PDT 24 |
43314960 ps |
| T125 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3308212718 |
|
|
Jun 05 03:55:35 PM PDT 24 |
Jun 05 03:55:38 PM PDT 24 |
173411785 ps |
| T981 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3207861050 |
|
|
Jun 05 03:55:47 PM PDT 24 |
Jun 05 03:55:52 PM PDT 24 |
356877148 ps |
| T90 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1002098268 |
|
|
Jun 05 03:55:24 PM PDT 24 |
Jun 05 03:55:26 PM PDT 24 |
50977909 ps |
| T982 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.781026636 |
|
|
Jun 05 03:55:36 PM PDT 24 |
Jun 05 03:55:40 PM PDT 24 |
1418916985 ps |
| T91 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1910718884 |
|
|
Jun 05 03:55:37 PM PDT 24 |
Jun 05 03:56:34 PM PDT 24 |
28202115069 ps |
| T983 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.877542615 |
|
|
Jun 05 03:55:40 PM PDT 24 |
Jun 05 03:55:42 PM PDT 24 |
51679097 ps |
| T984 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.403201610 |
|
|
Jun 05 03:55:54 PM PDT 24 |
Jun 05 03:55:57 PM PDT 24 |
50060086 ps |
| T985 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1326794815 |
|
|
Jun 05 03:55:32 PM PDT 24 |
Jun 05 03:55:35 PM PDT 24 |
124125524 ps |
| T986 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.964175781 |
|
|
Jun 05 03:55:35 PM PDT 24 |
Jun 05 03:55:40 PM PDT 24 |
44524529 ps |
| T987 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2680270222 |
|
|
Jun 05 03:55:34 PM PDT 24 |
Jun 05 03:55:37 PM PDT 24 |
235248617 ps |
| T988 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3722781994 |
|
|
Jun 05 03:55:51 PM PDT 24 |
Jun 05 03:55:55 PM PDT 24 |
129304572 ps |
| T989 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.269820729 |
|
|
Jun 05 03:55:46 PM PDT 24 |
Jun 05 03:55:48 PM PDT 24 |
33021070 ps |
| T990 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.521618846 |
|
|
Jun 05 03:55:44 PM PDT 24 |
Jun 05 03:55:46 PM PDT 24 |
43046576 ps |
| T89 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3692456079 |
|
|
Jun 05 03:55:24 PM PDT 24 |
Jun 05 03:56:12 PM PDT 24 |
7180576991 ps |
| T991 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.792079428 |
|
|
Jun 05 03:55:26 PM PDT 24 |
Jun 05 03:55:28 PM PDT 24 |
43032140 ps |
| T992 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3180673361 |
|
|
Jun 05 03:55:25 PM PDT 24 |
Jun 05 03:55:29 PM PDT 24 |
363429578 ps |
| T993 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2215418253 |
|
|
Jun 05 03:55:34 PM PDT 24 |
Jun 05 03:55:35 PM PDT 24 |
18676112 ps |
| T126 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3761138489 |
|
|
Jun 05 03:55:51 PM PDT 24 |
Jun 05 03:55:55 PM PDT 24 |
1535306203 ps |
| T994 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2897302525 |
|
|
Jun 05 03:55:49 PM PDT 24 |
Jun 05 03:55:52 PM PDT 24 |
265676271 ps |
| T995 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.175454409 |
|
|
Jun 05 03:55:42 PM PDT 24 |
Jun 05 03:56:48 PM PDT 24 |
35275658870 ps |
| T92 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.911224708 |
|
|
Jun 05 03:55:32 PM PDT 24 |
Jun 05 03:55:33 PM PDT 24 |
29326503 ps |
| T996 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1664693609 |
|
|
Jun 05 03:55:34 PM PDT 24 |
Jun 05 03:55:36 PM PDT 24 |
49283628 ps |
| T127 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1894484118 |
|
|
Jun 05 03:55:37 PM PDT 24 |
Jun 05 03:55:40 PM PDT 24 |
592420816 ps |
| T997 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3890321183 |
|
|
Jun 05 03:55:43 PM PDT 24 |
Jun 05 03:55:47 PM PDT 24 |
345572910 ps |
| T998 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.818685562 |
|
|
Jun 05 03:55:34 PM PDT 24 |
Jun 05 03:56:02 PM PDT 24 |
3812298961 ps |
| T131 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3478653940 |
|
|
Jun 05 03:55:47 PM PDT 24 |
Jun 05 03:55:49 PM PDT 24 |
385540105 ps |
| T999 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1170032484 |
|
|
Jun 05 03:55:37 PM PDT 24 |
Jun 05 03:55:38 PM PDT 24 |
24161080 ps |
| T1000 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.142690582 |
|
|
Jun 05 03:55:24 PM PDT 24 |
Jun 05 03:55:26 PM PDT 24 |
55510937 ps |
| T1001 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.912080131 |
|
|
Jun 05 03:55:44 PM PDT 24 |
Jun 05 03:55:45 PM PDT 24 |
30001841 ps |
| T1002 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1471964513 |
|
|
Jun 05 03:55:46 PM PDT 24 |
Jun 05 03:55:47 PM PDT 24 |
93535211 ps |
| T128 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1265446543 |
|
|
Jun 05 03:55:39 PM PDT 24 |
Jun 05 03:55:42 PM PDT 24 |
604821551 ps |
| T1003 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.861239471 |
|
|
Jun 05 03:55:35 PM PDT 24 |
Jun 05 03:55:36 PM PDT 24 |
17882322 ps |