Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	332537854	1			T1	395906		T2	23476		T3	7168
instr_valid_dis	287858701	1			T1	336790		T2	23476		T3	7168
instr_en	30617339	1			T1	554570		T4	282580		T15	258284

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	16482800	1			T1	56040		T4	256854		T11	75460
sram_ifetch_valid_disable	287451224	1			T1	370720		T2	23476		T3	7168
sram_ifetch_enable	28603830	1			T1	195816		T4	296368		T11	139696

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	332537854	1			T1	395906		T2	23476		T3	7168
hw_debug_en_valid_off	293767507	1			T1	325493		T2	23476		T3	7168
hw_debug_en_on	22447045	1			T1	630244		T4	362230		T11	85192

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	287451224	1			T1	370720		T2	23476		T3	7168
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	271924123	1			T1	319213		T2	23476		T3	7168
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9245787	1			T1	515074		T4	191498		T15	159706
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	9328454	1			T1	32546		T4	12046		T15	11232
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	4348666	1			T1	32546		T4	6318		T38	2900
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	3639382	1			T15	11232		T16	18144		T42	74556
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4849100	1			T1	23494		T4	10750		T11	63428
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1843772	1			T1	13190		T11	63428		T38	28168
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1754220	1			T1	10304		T4	10750		T15	38632
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8677647	1			T1	515074		T4	163530		T11	14446
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3045846	1			T4	34158		T11	14446		T38	28250
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4345837	1			T1	515074		T4	82046		T15	80810

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	15078648	1			T1	29192		T4	80332		T15	48714
lc_exec_en	8920298	1			T1	91676		T4	187950		T11	7318
valid_exec_dis	283784961	1			T1	332216		T2	23476		T3	7168
invalid_exec_dis	45086630	1			T1	251856		T4	553222		T11	215156