Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	135555968	1			T1	187595		T2	38		T6	155670
triple_byte_access	2892295	1			T1	6055		T2	1		T6	3153
halfword_access	4426217	1			T1	9067		T2	2		T6	4653
byte_access	6166924	1			T1	12058		T2	1		T6	6318
zero_access	1834889	1			T1	2934		T2	1		T6	1611

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

75263099

1

T1

956621

T2

22

T6

85487

auto[1]

75613194

1

T1

949446

T2

21

T6

85918

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	67460753	1			T1	941254		T2	17		T6	77658
auto[0]	triple_byte_access	1388312	1			T1	3141		T2	1		T6	1614
auto[0]	halfword_access	2171629	1			T1	4560		T2	2		T6	2262
auto[0]	byte_access	3157457	1			T1	6170		T2	1		T6	3170
auto[0]	zero_access	1084948	1			T1	1496		T2	1		T6	783
auto[1]	word_access	68095215	1			T1	934699		T2	21		T6	78012
auto[1]	triple_byte_access	1503983	1			T1	2914		T6	1539		T4	1885
auto[1]	halfword_access	2254588	1			T1	4507		T6	2391		T4	2784
auto[1]	byte_access	3009467	1			T1	5888		T6	3148		T4	3753
auto[1]	zero_access	749941	1			T1	1438		T6	828		T4	940