| T797 |
/workspace/coverage/default/37.sram_ctrl_executable.262170795 |
|
|
Jun 06 01:41:48 PM PDT 24 |
Jun 06 01:46:41 PM PDT 24 |
11658763868 ps |
| T798 |
/workspace/coverage/default/2.sram_ctrl_smoke.894036513 |
|
|
Jun 06 01:38:08 PM PDT 24 |
Jun 06 01:41:06 PM PDT 24 |
1336862935 ps |
| T799 |
/workspace/coverage/default/37.sram_ctrl_alert_test.3565830758 |
|
|
Jun 06 01:41:46 PM PDT 24 |
Jun 06 01:41:48 PM PDT 24 |
32518662 ps |
| T800 |
/workspace/coverage/default/5.sram_ctrl_alert_test.2412407747 |
|
|
Jun 06 01:38:16 PM PDT 24 |
Jun 06 01:38:17 PM PDT 24 |
11715479 ps |
| T801 |
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.3276106469 |
|
|
Jun 06 01:38:49 PM PDT 24 |
Jun 06 01:42:35 PM PDT 24 |
37214102802 ps |
| T802 |
/workspace/coverage/default/28.sram_ctrl_stress_pipeline.935708650 |
|
|
Jun 06 01:40:19 PM PDT 24 |
Jun 06 01:44:06 PM PDT 24 |
3445864545 ps |
| T803 |
/workspace/coverage/default/15.sram_ctrl_regwen.1912853455 |
|
|
Jun 06 01:39:06 PM PDT 24 |
Jun 06 02:05:05 PM PDT 24 |
22007448499 ps |
| T804 |
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.1013929671 |
|
|
Jun 06 01:43:47 PM PDT 24 |
Jun 06 01:44:53 PM PDT 24 |
3973336907 ps |
| T805 |
/workspace/coverage/default/15.sram_ctrl_stress_pipeline.1617498812 |
|
|
Jun 06 01:38:56 PM PDT 24 |
Jun 06 01:43:09 PM PDT 24 |
19204817012 ps |
| T806 |
/workspace/coverage/default/19.sram_ctrl_multiple_keys.1202703270 |
|
|
Jun 06 01:39:41 PM PDT 24 |
Jun 06 01:59:54 PM PDT 24 |
6187995805 ps |
| T807 |
/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.319088836 |
|
|
Jun 06 01:40:58 PM PDT 24 |
Jun 06 01:47:23 PM PDT 24 |
6077214194 ps |
| T808 |
/workspace/coverage/default/43.sram_ctrl_max_throughput.406909657 |
|
|
Jun 06 01:42:34 PM PDT 24 |
Jun 06 01:43:15 PM PDT 24 |
2660969957 ps |
| T809 |
/workspace/coverage/default/42.sram_ctrl_smoke.467564144 |
|
|
Jun 06 01:42:22 PM PDT 24 |
Jun 06 01:42:29 PM PDT 24 |
1332387209 ps |
| T810 |
/workspace/coverage/default/6.sram_ctrl_multiple_keys.2754666365 |
|
|
Jun 06 01:38:14 PM PDT 24 |
Jun 06 01:43:00 PM PDT 24 |
13480379617 ps |
| T811 |
/workspace/coverage/default/6.sram_ctrl_smoke.3989284749 |
|
|
Jun 06 01:38:27 PM PDT 24 |
Jun 06 01:39:33 PM PDT 24 |
746497736 ps |
| T812 |
/workspace/coverage/default/4.sram_ctrl_max_throughput.1141823504 |
|
|
Jun 06 01:38:13 PM PDT 24 |
Jun 06 01:39:19 PM PDT 24 |
1440421479 ps |
| T813 |
/workspace/coverage/default/38.sram_ctrl_max_throughput.1452816070 |
|
|
Jun 06 01:41:46 PM PDT 24 |
Jun 06 01:42:12 PM PDT 24 |
736758285 ps |
| T814 |
/workspace/coverage/default/9.sram_ctrl_lc_escalation.406172544 |
|
|
Jun 06 01:38:37 PM PDT 24 |
Jun 06 01:39:55 PM PDT 24 |
12526697594 ps |
| T815 |
/workspace/coverage/default/8.sram_ctrl_ram_cfg.2631973376 |
|
|
Jun 06 01:38:39 PM PDT 24 |
Jun 06 01:38:44 PM PDT 24 |
689770228 ps |
| T816 |
/workspace/coverage/default/25.sram_ctrl_partial_access.2951781523 |
|
|
Jun 06 01:39:58 PM PDT 24 |
Jun 06 01:40:19 PM PDT 24 |
3616109038 ps |
| T817 |
/workspace/coverage/default/34.sram_ctrl_ram_cfg.3215793326 |
|
|
Jun 06 01:41:04 PM PDT 24 |
Jun 06 01:41:08 PM PDT 24 |
768097394 ps |
| T818 |
/workspace/coverage/default/28.sram_ctrl_mem_partial_access.581653228 |
|
|
Jun 06 01:40:20 PM PDT 24 |
Jun 06 01:41:36 PM PDT 24 |
16074750562 ps |
| T819 |
/workspace/coverage/default/48.sram_ctrl_mem_walk.370205352 |
|
|
Jun 06 01:43:34 PM PDT 24 |
Jun 06 01:49:55 PM PDT 24 |
207012066687 ps |
| T820 |
/workspace/coverage/default/2.sram_ctrl_mem_walk.206954540 |
|
|
Jun 06 01:38:11 PM PDT 24 |
Jun 06 01:43:52 PM PDT 24 |
55336971487 ps |
| T821 |
/workspace/coverage/default/19.sram_ctrl_alert_test.1324433255 |
|
|
Jun 06 01:39:29 PM PDT 24 |
Jun 06 01:39:30 PM PDT 24 |
45294567 ps |
| T822 |
/workspace/coverage/default/27.sram_ctrl_max_throughput.2236091107 |
|
|
Jun 06 01:40:07 PM PDT 24 |
Jun 06 01:41:17 PM PDT 24 |
2959929272 ps |
| T823 |
/workspace/coverage/default/40.sram_ctrl_regwen.211330621 |
|
|
Jun 06 01:42:07 PM PDT 24 |
Jun 06 01:59:16 PM PDT 24 |
2123547378 ps |
| T824 |
/workspace/coverage/default/16.sram_ctrl_multiple_keys.1406532936 |
|
|
Jun 06 01:39:11 PM PDT 24 |
Jun 06 01:53:57 PM PDT 24 |
18236844078 ps |
| T825 |
/workspace/coverage/default/31.sram_ctrl_access_during_key_req.3505960391 |
|
|
Jun 06 01:40:48 PM PDT 24 |
Jun 06 01:48:00 PM PDT 24 |
33654500928 ps |
| T826 |
/workspace/coverage/default/32.sram_ctrl_stress_pipeline.255231263 |
|
|
Jun 06 01:40:48 PM PDT 24 |
Jun 06 01:47:18 PM PDT 24 |
4999756580 ps |
| T827 |
/workspace/coverage/default/34.sram_ctrl_partial_access.1931022566 |
|
|
Jun 06 01:41:08 PM PDT 24 |
Jun 06 01:41:13 PM PDT 24 |
708524667 ps |
| T828 |
/workspace/coverage/default/23.sram_ctrl_stress_pipeline.4169307328 |
|
|
Jun 06 01:39:51 PM PDT 24 |
Jun 06 01:46:33 PM PDT 24 |
6099893674 ps |
| T829 |
/workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.640316669 |
|
|
Jun 06 01:39:28 PM PDT 24 |
Jun 06 01:39:49 PM PDT 24 |
857604203 ps |
| T830 |
/workspace/coverage/default/18.sram_ctrl_partial_access_b2b.2662444306 |
|
|
Jun 06 01:39:15 PM PDT 24 |
Jun 06 01:48:11 PM PDT 24 |
46624444928 ps |
| T831 |
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.2669817771 |
|
|
Jun 06 01:38:48 PM PDT 24 |
Jun 06 01:56:07 PM PDT 24 |
22452001546 ps |
| T832 |
/workspace/coverage/default/22.sram_ctrl_bijection.237309314 |
|
|
Jun 06 01:39:42 PM PDT 24 |
Jun 06 01:50:46 PM PDT 24 |
38164848506 ps |
| T833 |
/workspace/coverage/default/3.sram_ctrl_max_throughput.1324356333 |
|
|
Jun 06 01:38:16 PM PDT 24 |
Jun 06 01:39:09 PM PDT 24 |
749827906 ps |
| T834 |
/workspace/coverage/default/13.sram_ctrl_ram_cfg.2148756238 |
|
|
Jun 06 01:38:56 PM PDT 24 |
Jun 06 01:39:00 PM PDT 24 |
1412476883 ps |
| T835 |
/workspace/coverage/default/21.sram_ctrl_regwen.1126073827 |
|
|
Jun 06 01:39:39 PM PDT 24 |
Jun 06 01:51:05 PM PDT 24 |
2366631111 ps |
| T836 |
/workspace/coverage/default/34.sram_ctrl_stress_all.225786870 |
|
|
Jun 06 01:41:16 PM PDT 24 |
Jun 06 02:38:56 PM PDT 24 |
42332136314 ps |
| T837 |
/workspace/coverage/default/19.sram_ctrl_smoke.1130980115 |
|
|
Jun 06 01:39:29 PM PDT 24 |
Jun 06 01:39:48 PM PDT 24 |
667289644 ps |
| T838 |
/workspace/coverage/default/42.sram_ctrl_access_during_key_req.408037113 |
|
|
Jun 06 01:42:27 PM PDT 24 |
Jun 06 02:00:19 PM PDT 24 |
43959196864 ps |
| T839 |
/workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.2528212271 |
|
|
Jun 06 01:38:11 PM PDT 24 |
Jun 06 01:41:06 PM PDT 24 |
7615347522 ps |
| T840 |
/workspace/coverage/default/26.sram_ctrl_stress_pipeline.2625836452 |
|
|
Jun 06 01:39:58 PM PDT 24 |
Jun 06 01:43:00 PM PDT 24 |
10643091948 ps |
| T841 |
/workspace/coverage/default/15.sram_ctrl_multiple_keys.3586193062 |
|
|
Jun 06 01:39:00 PM PDT 24 |
Jun 06 02:00:33 PM PDT 24 |
25820105643 ps |
| T842 |
/workspace/coverage/default/7.sram_ctrl_multiple_keys.4034419569 |
|
|
Jun 06 01:38:28 PM PDT 24 |
Jun 06 02:19:48 PM PDT 24 |
198542922974 ps |
| T843 |
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.2855356234 |
|
|
Jun 06 01:43:37 PM PDT 24 |
Jun 06 02:06:40 PM PDT 24 |
47488487132 ps |
| T844 |
/workspace/coverage/default/30.sram_ctrl_mem_walk.1115856086 |
|
|
Jun 06 01:40:37 PM PDT 24 |
Jun 06 01:43:16 PM PDT 24 |
6935054832 ps |
| T845 |
/workspace/coverage/default/28.sram_ctrl_multiple_keys.2878949295 |
|
|
Jun 06 01:40:17 PM PDT 24 |
Jun 06 02:00:31 PM PDT 24 |
48238758611 ps |
| T846 |
/workspace/coverage/default/14.sram_ctrl_partial_access.735323138 |
|
|
Jun 06 01:39:00 PM PDT 24 |
Jun 06 01:39:47 PM PDT 24 |
4556674769 ps |
| T847 |
/workspace/coverage/default/34.sram_ctrl_alert_test.3067309398 |
|
|
Jun 06 01:41:16 PM PDT 24 |
Jun 06 01:41:17 PM PDT 24 |
19717842 ps |
| T848 |
/workspace/coverage/default/7.sram_ctrl_stress_all.2990084139 |
|
|
Jun 06 01:38:40 PM PDT 24 |
Jun 06 02:41:00 PM PDT 24 |
61675881525 ps |
| T849 |
/workspace/coverage/default/20.sram_ctrl_mem_partial_access.625260976 |
|
|
Jun 06 01:39:40 PM PDT 24 |
Jun 06 01:41:09 PM PDT 24 |
3192695541 ps |
| T850 |
/workspace/coverage/default/8.sram_ctrl_executable.3360610177 |
|
|
Jun 06 01:38:36 PM PDT 24 |
Jun 06 01:52:45 PM PDT 24 |
21807299023 ps |
| T851 |
/workspace/coverage/default/39.sram_ctrl_regwen.4014645670 |
|
|
Jun 06 01:41:57 PM PDT 24 |
Jun 06 02:05:18 PM PDT 24 |
4929994894 ps |
| T852 |
/workspace/coverage/default/29.sram_ctrl_regwen.2363136818 |
|
|
Jun 06 01:40:28 PM PDT 24 |
Jun 06 01:53:54 PM PDT 24 |
11876096307 ps |
| T853 |
/workspace/coverage/default/0.sram_ctrl_bijection.469782544 |
|
|
Jun 06 01:38:04 PM PDT 24 |
Jun 06 01:53:06 PM PDT 24 |
12386838598 ps |
| T854 |
/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.62698914 |
|
|
Jun 06 01:38:56 PM PDT 24 |
Jun 06 01:44:56 PM PDT 24 |
36421606489 ps |
| T855 |
/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.3485215361 |
|
|
Jun 06 01:38:56 PM PDT 24 |
Jun 06 01:39:03 PM PDT 24 |
705861226 ps |
| T856 |
/workspace/coverage/default/12.sram_ctrl_regwen.3521198105 |
|
|
Jun 06 01:38:48 PM PDT 24 |
Jun 06 01:42:09 PM PDT 24 |
3029578847 ps |
| T857 |
/workspace/coverage/default/25.sram_ctrl_smoke.302810893 |
|
|
Jun 06 01:40:00 PM PDT 24 |
Jun 06 01:40:17 PM PDT 24 |
4997410435 ps |
| T858 |
/workspace/coverage/default/5.sram_ctrl_partial_access.4149751179 |
|
|
Jun 06 01:38:20 PM PDT 24 |
Jun 06 01:39:16 PM PDT 24 |
1573106853 ps |
| T859 |
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.3635936687 |
|
|
Jun 06 01:38:15 PM PDT 24 |
Jun 06 01:38:25 PM PDT 24 |
713442748 ps |
| T860 |
/workspace/coverage/default/6.sram_ctrl_alert_test.332430977 |
|
|
Jun 06 01:38:30 PM PDT 24 |
Jun 06 01:38:32 PM PDT 24 |
187257966 ps |
| T861 |
/workspace/coverage/default/37.sram_ctrl_smoke.1539611529 |
|
|
Jun 06 01:41:34 PM PDT 24 |
Jun 06 01:41:53 PM PDT 24 |
2263182114 ps |
| T862 |
/workspace/coverage/default/21.sram_ctrl_stress_pipeline.1670752576 |
|
|
Jun 06 01:39:39 PM PDT 24 |
Jun 06 01:43:31 PM PDT 24 |
3458019134 ps |
| T863 |
/workspace/coverage/default/8.sram_ctrl_mem_walk.337189041 |
|
|
Jun 06 01:38:37 PM PDT 24 |
Jun 06 01:44:03 PM PDT 24 |
21011311322 ps |
| T864 |
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2657219730 |
|
|
Jun 06 01:38:38 PM PDT 24 |
Jun 06 01:38:55 PM PDT 24 |
736971478 ps |
| T865 |
/workspace/coverage/default/39.sram_ctrl_max_throughput.1809255128 |
|
|
Jun 06 01:41:56 PM PDT 24 |
Jun 06 01:44:44 PM PDT 24 |
3048462158 ps |
| T866 |
/workspace/coverage/default/25.sram_ctrl_ram_cfg.3497914543 |
|
|
Jun 06 01:40:00 PM PDT 24 |
Jun 06 01:40:04 PM PDT 24 |
695748538 ps |
| T867 |
/workspace/coverage/default/23.sram_ctrl_alert_test.3175036167 |
|
|
Jun 06 01:39:50 PM PDT 24 |
Jun 06 01:39:52 PM PDT 24 |
25356538 ps |
| T868 |
/workspace/coverage/default/43.sram_ctrl_smoke.1219923500 |
|
|
Jun 06 01:42:31 PM PDT 24 |
Jun 06 01:42:56 PM PDT 24 |
750958064 ps |
| T869 |
/workspace/coverage/default/4.sram_ctrl_ram_cfg.358298191 |
|
|
Jun 06 01:38:08 PM PDT 24 |
Jun 06 01:38:12 PM PDT 24 |
1362107418 ps |
| T870 |
/workspace/coverage/default/21.sram_ctrl_mem_walk.3541608204 |
|
|
Jun 06 01:39:40 PM PDT 24 |
Jun 06 01:44:49 PM PDT 24 |
5311451287 ps |
| T871 |
/workspace/coverage/default/41.sram_ctrl_access_during_key_req.1052788427 |
|
|
Jun 06 01:42:11 PM PDT 24 |
Jun 06 01:50:38 PM PDT 24 |
25960551697 ps |
| T872 |
/workspace/coverage/default/47.sram_ctrl_max_throughput.1192467874 |
|
|
Jun 06 01:43:16 PM PDT 24 |
Jun 06 01:43:38 PM PDT 24 |
711865866 ps |
| T873 |
/workspace/coverage/default/15.sram_ctrl_partial_access.2567574247 |
|
|
Jun 06 01:38:57 PM PDT 24 |
Jun 06 01:41:10 PM PDT 24 |
5538616058 ps |
| T874 |
/workspace/coverage/default/20.sram_ctrl_ram_cfg.3560315334 |
|
|
Jun 06 01:39:38 PM PDT 24 |
Jun 06 01:39:42 PM PDT 24 |
1607306935 ps |
| T875 |
/workspace/coverage/default/40.sram_ctrl_partial_access_b2b.2391432019 |
|
|
Jun 06 01:42:05 PM PDT 24 |
Jun 06 01:48:08 PM PDT 24 |
17944585111 ps |
| T876 |
/workspace/coverage/default/46.sram_ctrl_bijection.4202939718 |
|
|
Jun 06 01:43:10 PM PDT 24 |
Jun 06 02:12:44 PM PDT 24 |
24769572977 ps |
| T877 |
/workspace/coverage/default/0.sram_ctrl_ram_cfg.2461675423 |
|
|
Jun 06 01:38:03 PM PDT 24 |
Jun 06 01:38:09 PM PDT 24 |
1405558977 ps |
| T878 |
/workspace/coverage/default/0.sram_ctrl_regwen.2531089957 |
|
|
Jun 06 01:37:58 PM PDT 24 |
Jun 06 01:57:13 PM PDT 24 |
83965372418 ps |
| T879 |
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.1651153972 |
|
|
Jun 06 01:43:09 PM PDT 24 |
Jun 06 01:48:57 PM PDT 24 |
14399478359 ps |
| T880 |
/workspace/coverage/default/39.sram_ctrl_stress_pipeline.3939682906 |
|
|
Jun 06 01:42:03 PM PDT 24 |
Jun 06 01:48:11 PM PDT 24 |
44227934665 ps |
| T881 |
/workspace/coverage/default/46.sram_ctrl_ram_cfg.3278895033 |
|
|
Jun 06 01:43:09 PM PDT 24 |
Jun 06 01:43:13 PM PDT 24 |
594830764 ps |
| T882 |
/workspace/coverage/default/10.sram_ctrl_executable.3872000307 |
|
|
Jun 06 01:38:52 PM PDT 24 |
Jun 06 01:55:28 PM PDT 24 |
22361577878 ps |
| T883 |
/workspace/coverage/default/27.sram_ctrl_partial_access.177182470 |
|
|
Jun 06 01:40:08 PM PDT 24 |
Jun 06 01:42:48 PM PDT 24 |
2559956540 ps |
| T884 |
/workspace/coverage/default/24.sram_ctrl_executable.3763926316 |
|
|
Jun 06 01:40:01 PM PDT 24 |
Jun 06 01:43:53 PM PDT 24 |
13490038627 ps |
| T885 |
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.153120353 |
|
|
Jun 06 01:43:29 PM PDT 24 |
Jun 06 01:47:47 PM PDT 24 |
4482711806 ps |
| T886 |
/workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.4114567210 |
|
|
Jun 06 01:40:56 PM PDT 24 |
Jun 06 01:43:11 PM PDT 24 |
1626219640 ps |
| T887 |
/workspace/coverage/default/42.sram_ctrl_regwen.4126866757 |
|
|
Jun 06 01:42:21 PM PDT 24 |
Jun 06 01:48:53 PM PDT 24 |
92488348219 ps |
| T888 |
/workspace/coverage/default/36.sram_ctrl_bijection.3185569335 |
|
|
Jun 06 01:41:28 PM PDT 24 |
Jun 06 02:01:38 PM PDT 24 |
240009183506 ps |
| T889 |
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.1151212005 |
|
|
Jun 06 01:38:37 PM PDT 24 |
Jun 06 01:40:10 PM PDT 24 |
11672366812 ps |
| T890 |
/workspace/coverage/default/6.sram_ctrl_bijection.4055137630 |
|
|
Jun 06 01:38:21 PM PDT 24 |
Jun 06 02:18:00 PM PDT 24 |
68190108923 ps |
| T891 |
/workspace/coverage/default/37.sram_ctrl_partial_access_b2b.2125484919 |
|
|
Jun 06 01:41:37 PM PDT 24 |
Jun 06 01:45:40 PM PDT 24 |
38110921571 ps |
| T892 |
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.67352835 |
|
|
Jun 06 01:42:42 PM PDT 24 |
Jun 06 01:44:05 PM PDT 24 |
22727600016 ps |
| T893 |
/workspace/coverage/default/4.sram_ctrl_partial_access_b2b.3409715859 |
|
|
Jun 06 01:38:19 PM PDT 24 |
Jun 06 01:45:26 PM PDT 24 |
36589232025 ps |
| T894 |
/workspace/coverage/default/26.sram_ctrl_mem_partial_access.2616897056 |
|
|
Jun 06 01:40:09 PM PDT 24 |
Jun 06 01:43:01 PM PDT 24 |
6750059478 ps |
| T895 |
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.3252160423 |
|
|
Jun 06 01:43:02 PM PDT 24 |
Jun 06 01:45:36 PM PDT 24 |
9740736222 ps |
| T896 |
/workspace/coverage/default/44.sram_ctrl_ram_cfg.1224172191 |
|
|
Jun 06 01:42:38 PM PDT 24 |
Jun 06 01:42:43 PM PDT 24 |
472422186 ps |
| T897 |
/workspace/coverage/default/27.sram_ctrl_regwen.2905642118 |
|
|
Jun 06 01:40:08 PM PDT 24 |
Jun 06 01:43:48 PM PDT 24 |
10359266634 ps |
| T898 |
/workspace/coverage/default/33.sram_ctrl_mem_partial_access.1665185547 |
|
|
Jun 06 01:41:05 PM PDT 24 |
Jun 06 01:42:36 PM PDT 24 |
2763445254 ps |
| T899 |
/workspace/coverage/default/1.sram_ctrl_partial_access.3597119262 |
|
|
Jun 06 01:38:08 PM PDT 24 |
Jun 06 01:38:13 PM PDT 24 |
363612611 ps |
| T900 |
/workspace/coverage/default/13.sram_ctrl_executable.2948822104 |
|
|
Jun 06 01:38:50 PM PDT 24 |
Jun 06 01:39:14 PM PDT 24 |
631906621 ps |
| T901 |
/workspace/coverage/default/28.sram_ctrl_ram_cfg.1473456004 |
|
|
Jun 06 01:40:17 PM PDT 24 |
Jun 06 01:40:23 PM PDT 24 |
3727927185 ps |
| T902 |
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.737739419 |
|
|
Jun 06 01:37:59 PM PDT 24 |
Jun 06 01:42:07 PM PDT 24 |
3950888223 ps |
| T903 |
/workspace/coverage/default/48.sram_ctrl_stress_all.2973041940 |
|
|
Jun 06 01:43:36 PM PDT 24 |
Jun 06 02:22:03 PM PDT 24 |
26162129922 ps |
| T904 |
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.690693574 |
|
|
Jun 06 01:42:31 PM PDT 24 |
Jun 06 01:45:26 PM PDT 24 |
11261740200 ps |
| T905 |
/workspace/coverage/default/41.sram_ctrl_ram_cfg.3661879696 |
|
|
Jun 06 01:42:13 PM PDT 24 |
Jun 06 01:42:18 PM PDT 24 |
1523238677 ps |
| T906 |
/workspace/coverage/default/21.sram_ctrl_alert_test.1954726003 |
|
|
Jun 06 01:39:39 PM PDT 24 |
Jun 06 01:39:41 PM PDT 24 |
15858771 ps |
| T907 |
/workspace/coverage/default/49.sram_ctrl_stress_all.100851619 |
|
|
Jun 06 01:43:48 PM PDT 24 |
Jun 06 02:43:08 PM PDT 24 |
467616613333 ps |
| T908 |
/workspace/coverage/default/13.sram_ctrl_regwen.4136296478 |
|
|
Jun 06 01:38:51 PM PDT 24 |
Jun 06 01:57:12 PM PDT 24 |
3055942963 ps |
| T909 |
/workspace/coverage/default/13.sram_ctrl_access_during_key_req.3543227632 |
|
|
Jun 06 01:38:50 PM PDT 24 |
Jun 06 01:44:20 PM PDT 24 |
14193648277 ps |
| T910 |
/workspace/coverage/default/46.sram_ctrl_partial_access.4277429125 |
|
|
Jun 06 01:43:09 PM PDT 24 |
Jun 06 01:43:19 PM PDT 24 |
813017967 ps |
| T911 |
/workspace/coverage/default/43.sram_ctrl_alert_test.1769824094 |
|
|
Jun 06 01:42:39 PM PDT 24 |
Jun 06 01:42:41 PM PDT 24 |
46862851 ps |
| T912 |
/workspace/coverage/default/28.sram_ctrl_access_during_key_req.830275220 |
|
|
Jun 06 01:40:18 PM PDT 24 |
Jun 06 01:42:55 PM PDT 24 |
6094384574 ps |
| T913 |
/workspace/coverage/default/8.sram_ctrl_bijection.86149264 |
|
|
Jun 06 01:38:37 PM PDT 24 |
Jun 06 02:22:08 PM PDT 24 |
460168159297 ps |
| T914 |
/workspace/coverage/default/24.sram_ctrl_access_during_key_req.476674674 |
|
|
Jun 06 01:39:50 PM PDT 24 |
Jun 06 01:45:07 PM PDT 24 |
8808013745 ps |
| T915 |
/workspace/coverage/default/44.sram_ctrl_multiple_keys.1900160726 |
|
|
Jun 06 01:42:44 PM PDT 24 |
Jun 06 01:59:24 PM PDT 24 |
21989854133 ps |
| T916 |
/workspace/coverage/default/4.sram_ctrl_partial_access.3709318333 |
|
|
Jun 06 01:38:20 PM PDT 24 |
Jun 06 01:40:07 PM PDT 24 |
1239301796 ps |
| T917 |
/workspace/coverage/default/3.sram_ctrl_stress_all.3064836558 |
|
|
Jun 06 01:38:12 PM PDT 24 |
Jun 06 02:36:15 PM PDT 24 |
98417396648 ps |
| T918 |
/workspace/coverage/default/41.sram_ctrl_mem_partial_access.3497626408 |
|
|
Jun 06 01:42:26 PM PDT 24 |
Jun 06 01:45:30 PM PDT 24 |
23188566489 ps |
| T919 |
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.1510196257 |
|
|
Jun 06 01:38:07 PM PDT 24 |
Jun 06 01:47:02 PM PDT 24 |
43246986289 ps |
| T920 |
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.878646086 |
|
|
Jun 06 01:38:38 PM PDT 24 |
Jun 06 01:51:00 PM PDT 24 |
24859391341 ps |
| T921 |
/workspace/coverage/default/46.sram_ctrl_alert_test.3737856921 |
|
|
Jun 06 01:43:11 PM PDT 24 |
Jun 06 01:43:12 PM PDT 24 |
14458360 ps |
| T922 |
/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.2513976981 |
|
|
Jun 06 01:39:51 PM PDT 24 |
Jun 06 01:45:01 PM PDT 24 |
48885814947 ps |
| T923 |
/workspace/coverage/default/12.sram_ctrl_multiple_keys.3577604864 |
|
|
Jun 06 01:38:50 PM PDT 24 |
Jun 06 01:51:36 PM PDT 24 |
52002514131 ps |
| T924 |
/workspace/coverage/default/39.sram_ctrl_partial_access.2033144763 |
|
|
Jun 06 01:41:56 PM PDT 24 |
Jun 06 01:42:02 PM PDT 24 |
407340487 ps |
| T925 |
/workspace/coverage/default/10.sram_ctrl_stress_all.1139693153 |
|
|
Jun 06 01:38:46 PM PDT 24 |
Jun 06 03:14:06 PM PDT 24 |
348494964213 ps |
| T926 |
/workspace/coverage/default/48.sram_ctrl_ram_cfg.3965454304 |
|
|
Jun 06 01:43:34 PM PDT 24 |
Jun 06 01:43:39 PM PDT 24 |
4198206151 ps |
| T927 |
/workspace/coverage/default/26.sram_ctrl_stress_all.154396642 |
|
|
Jun 06 01:40:10 PM PDT 24 |
Jun 06 04:24:18 PM PDT 24 |
395573852757 ps |
| T928 |
/workspace/coverage/default/3.sram_ctrl_mem_partial_access.2831597929 |
|
|
Jun 06 01:38:09 PM PDT 24 |
Jun 06 01:39:44 PM PDT 24 |
5224322212 ps |
| T929 |
/workspace/coverage/default/16.sram_ctrl_access_during_key_req.1461008597 |
|
|
Jun 06 01:39:06 PM PDT 24 |
Jun 06 01:45:21 PM PDT 24 |
3343178476 ps |
| T930 |
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.2010450816 |
|
|
Jun 06 01:38:36 PM PDT 24 |
Jun 06 01:42:55 PM PDT 24 |
17740656451 ps |
| T931 |
/workspace/coverage/default/36.sram_ctrl_mem_partial_access.374643385 |
|
|
Jun 06 01:41:37 PM PDT 24 |
Jun 06 01:42:54 PM PDT 24 |
5773315216 ps |
| T932 |
/workspace/coverage/default/34.sram_ctrl_smoke.701294414 |
|
|
Jun 06 01:41:07 PM PDT 24 |
Jun 06 01:41:14 PM PDT 24 |
368114665 ps |
| T933 |
/workspace/coverage/default/33.sram_ctrl_access_during_key_req.3573012955 |
|
|
Jun 06 01:41:04 PM PDT 24 |
Jun 06 01:59:25 PM PDT 24 |
15371280571 ps |
| T934 |
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.2779405538 |
|
|
Jun 06 01:43:36 PM PDT 24 |
Jun 06 01:46:15 PM PDT 24 |
3492965045 ps |
| T935 |
/workspace/coverage/default/41.sram_ctrl_lc_escalation.2625539067 |
|
|
Jun 06 01:42:12 PM PDT 24 |
Jun 06 01:43:07 PM PDT 24 |
16586077988 ps |
| T936 |
/workspace/coverage/default/45.sram_ctrl_regwen.2619194243 |
|
|
Jun 06 01:43:00 PM PDT 24 |
Jun 06 01:49:54 PM PDT 24 |
3149315478 ps |
| T937 |
/workspace/coverage/default/20.sram_ctrl_smoke.2390606551 |
|
|
Jun 06 01:39:26 PM PDT 24 |
Jun 06 01:39:37 PM PDT 24 |
2723521651 ps |
| T938 |
/workspace/coverage/default/46.sram_ctrl_lc_escalation.478215796 |
|
|
Jun 06 01:43:09 PM PDT 24 |
Jun 06 01:45:03 PM PDT 24 |
140498517848 ps |
| T939 |
/workspace/coverage/default/24.sram_ctrl_regwen.2694187587 |
|
|
Jun 06 01:39:58 PM PDT 24 |
Jun 06 01:44:14 PM PDT 24 |
9172568324 ps |
| T940 |
/workspace/coverage/default/28.sram_ctrl_lc_escalation.3830243197 |
|
|
Jun 06 01:40:18 PM PDT 24 |
Jun 06 01:40:43 PM PDT 24 |
16270934457 ps |
| T941 |
/workspace/coverage/default/0.sram_ctrl_mem_walk.3453031474 |
|
|
Jun 06 01:38:03 PM PDT 24 |
Jun 06 01:40:12 PM PDT 24 |
4113974627 ps |
| T942 |
/workspace/coverage/default/43.sram_ctrl_lc_escalation.2281275404 |
|
|
Jun 06 01:42:32 PM PDT 24 |
Jun 06 01:44:11 PM PDT 24 |
51483615274 ps |
| T943 |
/workspace/coverage/default/9.sram_ctrl_bijection.580775051 |
|
|
Jun 06 01:38:40 PM PDT 24 |
Jun 06 01:54:13 PM PDT 24 |
28048726214 ps |
| T944 |
/workspace/coverage/default/19.sram_ctrl_mem_partial_access.2479116907 |
|
|
Jun 06 01:39:28 PM PDT 24 |
Jun 06 01:40:53 PM PDT 24 |
5310735174 ps |
| T945 |
/workspace/coverage/default/37.sram_ctrl_partial_access.2696846676 |
|
|
Jun 06 01:41:37 PM PDT 24 |
Jun 06 01:41:57 PM PDT 24 |
4300945458 ps |
| T946 |
/workspace/coverage/default/15.sram_ctrl_executable.1372400840 |
|
|
Jun 06 01:39:05 PM PDT 24 |
Jun 06 01:45:09 PM PDT 24 |
21216315452 ps |
| T58 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1460153821 |
|
|
Jun 06 01:31:36 PM PDT 24 |
Jun 06 01:31:37 PM PDT 24 |
41925678 ps |
| T59 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1580358193 |
|
|
Jun 06 01:31:36 PM PDT 24 |
Jun 06 01:31:38 PM PDT 24 |
18909022 ps |
| T60 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3923998289 |
|
|
Jun 06 01:31:28 PM PDT 24 |
Jun 06 01:31:30 PM PDT 24 |
44479180 ps |
| T93 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3833246881 |
|
|
Jun 06 01:31:30 PM PDT 24 |
Jun 06 01:31:32 PM PDT 24 |
19655216 ps |
| T64 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2783406047 |
|
|
Jun 06 01:31:25 PM PDT 24 |
Jun 06 01:31:30 PM PDT 24 |
180958438 ps |
| T947 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.102768613 |
|
|
Jun 06 01:31:26 PM PDT 24 |
Jun 06 01:31:30 PM PDT 24 |
202392655 ps |
| T55 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2987968732 |
|
|
Jun 06 01:31:22 PM PDT 24 |
Jun 06 01:31:27 PM PDT 24 |
265977687 ps |
| T948 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3561837972 |
|
|
Jun 06 01:31:21 PM PDT 24 |
Jun 06 01:31:24 PM PDT 24 |
58524922 ps |
| T65 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2699108590 |
|
|
Jun 06 01:31:37 PM PDT 24 |
Jun 06 01:32:29 PM PDT 24 |
7436791728 ps |
| T66 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1680943350 |
|
|
Jun 06 01:31:26 PM PDT 24 |
Jun 06 01:31:29 PM PDT 24 |
25417442 ps |
| T67 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1757986865 |
|
|
Jun 06 01:31:25 PM PDT 24 |
Jun 06 01:32:00 PM PDT 24 |
28370647568 ps |
| T949 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3276533259 |
|
|
Jun 06 01:31:23 PM PDT 24 |
Jun 06 01:31:29 PM PDT 24 |
376625320 ps |
| T950 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3066155638 |
|
|
Jun 06 01:31:26 PM PDT 24 |
Jun 06 01:31:34 PM PDT 24 |
217483134 ps |
| T68 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.476096201 |
|
|
Jun 06 01:31:27 PM PDT 24 |
Jun 06 01:31:58 PM PDT 24 |
3704707063 ps |
| T102 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.886248696 |
|
|
Jun 06 01:31:37 PM PDT 24 |
Jun 06 01:31:39 PM PDT 24 |
21113176 ps |
| T56 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3060763483 |
|
|
Jun 06 01:31:26 PM PDT 24 |
Jun 06 01:31:30 PM PDT 24 |
257559650 ps |
| T951 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3875411331 |
|
|
Jun 06 01:31:37 PM PDT 24 |
Jun 06 01:31:43 PM PDT 24 |
126863186 ps |
| T94 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.543243494 |
|
|
Jun 06 01:31:26 PM PDT 24 |
Jun 06 01:32:01 PM PDT 24 |
21780013105 ps |
| T69 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2905835252 |
|
|
Jun 06 01:31:23 PM PDT 24 |
Jun 06 01:31:26 PM PDT 24 |
18429289 ps |
| T952 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.170377521 |
|
|
Jun 06 01:31:23 PM PDT 24 |
Jun 06 01:31:29 PM PDT 24 |
710568866 ps |
| T57 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2823373533 |
|
|
Jun 06 01:31:36 PM PDT 24 |
Jun 06 01:31:39 PM PDT 24 |
553031470 ps |
| T70 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2112617436 |
|
|
Jun 06 01:31:24 PM PDT 24 |
Jun 06 01:31:28 PM PDT 24 |
30989923 ps |
| T110 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1882903541 |
|
|
Jun 06 01:31:27 PM PDT 24 |
Jun 06 01:31:31 PM PDT 24 |
262000083 ps |
| T95 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.77231572 |
|
|
Jun 06 01:31:18 PM PDT 24 |
Jun 06 01:31:21 PM PDT 24 |
25345302 ps |
| T71 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1577289484 |
|
|
Jun 06 01:31:18 PM PDT 24 |
Jun 06 01:31:49 PM PDT 24 |
21748865777 ps |
| T119 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3631260525 |
|
|
Jun 06 01:31:21 PM PDT 24 |
Jun 06 01:31:25 PM PDT 24 |
326332163 ps |
| T953 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.623234746 |
|
|
Jun 06 01:31:18 PM PDT 24 |
Jun 06 01:31:20 PM PDT 24 |
16390811 ps |
| T954 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3104067748 |
|
|
Jun 06 01:31:21 PM PDT 24 |
Jun 06 01:32:17 PM PDT 24 |
32095558081 ps |
| T955 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.4094822367 |
|
|
Jun 06 01:31:28 PM PDT 24 |
Jun 06 01:31:34 PM PDT 24 |
892749698 ps |
| T72 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2318651002 |
|
|
Jun 06 01:31:37 PM PDT 24 |
Jun 06 01:31:39 PM PDT 24 |
39544296 ps |
| T112 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2900996473 |
|
|
Jun 06 01:31:36 PM PDT 24 |
Jun 06 01:31:40 PM PDT 24 |
266051275 ps |
| T956 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3779232296 |
|
|
Jun 06 01:31:21 PM PDT 24 |
Jun 06 01:31:28 PM PDT 24 |
696876831 ps |
| T957 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.36334398 |
|
|
Jun 06 01:31:17 PM PDT 24 |
Jun 06 01:31:21 PM PDT 24 |
375132004 ps |
| T958 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1926953796 |
|
|
Jun 06 01:31:22 PM PDT 24 |
Jun 06 01:31:26 PM PDT 24 |
19580031 ps |
| T959 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.4116055520 |
|
|
Jun 06 01:31:20 PM PDT 24 |
Jun 06 01:31:22 PM PDT 24 |
133456945 ps |
| T960 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3827899479 |
|
|
Jun 06 01:31:21 PM PDT 24 |
Jun 06 01:31:23 PM PDT 24 |
24398627 ps |
| T961 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1343034803 |
|
|
Jun 06 01:31:25 PM PDT 24 |
Jun 06 01:31:29 PM PDT 24 |
24363910 ps |
| T962 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1222877547 |
|
|
Jun 06 01:31:26 PM PDT 24 |
Jun 06 01:31:29 PM PDT 24 |
55051764 ps |
| T963 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.4198034008 |
|
|
Jun 06 01:31:20 PM PDT 24 |
Jun 06 01:31:26 PM PDT 24 |
1446623882 ps |
| T964 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2626939124 |
|
|
Jun 06 01:31:37 PM PDT 24 |
Jun 06 01:31:39 PM PDT 24 |
11365471 ps |
| T114 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.4267057221 |
|
|
Jun 06 01:31:24 PM PDT 24 |
Jun 06 01:31:28 PM PDT 24 |
354427536 ps |
| T116 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.809741128 |
|
|
Jun 06 01:31:38 PM PDT 24 |
Jun 06 01:31:42 PM PDT 24 |
1336391535 ps |
| T965 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.4122531339 |
|
|
Jun 06 01:31:19 PM PDT 24 |
Jun 06 01:31:23 PM PDT 24 |
82349741 ps |
| T966 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.695935206 |
|
|
Jun 06 01:31:32 PM PDT 24 |
Jun 06 01:31:34 PM PDT 24 |
15581544 ps |
| T967 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.215879890 |
|
|
Jun 06 01:31:27 PM PDT 24 |
Jun 06 01:31:32 PM PDT 24 |
220910824 ps |
| T968 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1702140556 |
|
|
Jun 06 01:31:22 PM PDT 24 |
Jun 06 01:31:56 PM PDT 24 |
14778096596 ps |
| T75 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2499796018 |
|
|
Jun 06 01:31:26 PM PDT 24 |
Jun 06 01:31:29 PM PDT 24 |
29788401 ps |
| T969 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.4293280003 |
|
|
Jun 06 01:31:25 PM PDT 24 |
Jun 06 01:31:31 PM PDT 24 |
1468549609 ps |
| T76 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1635505982 |
|
|
Jun 06 01:31:37 PM PDT 24 |
Jun 06 01:32:33 PM PDT 24 |
14196407804 ps |
| T970 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3778864545 |
|
|
Jun 06 01:31:23 PM PDT 24 |
Jun 06 01:31:28 PM PDT 24 |
246090474 ps |
| T971 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2996846805 |
|
|
Jun 06 01:31:28 PM PDT 24 |
Jun 06 01:31:33 PM PDT 24 |
379018444 ps |
| T972 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.4012328562 |
|
|
Jun 06 01:31:36 PM PDT 24 |
Jun 06 01:31:42 PM PDT 24 |
360028248 ps |
| T973 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.301659724 |
|
|
Jun 06 01:31:18 PM PDT 24 |
Jun 06 01:31:22 PM PDT 24 |
351319978 ps |
| T974 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2368371183 |
|
|
Jun 06 01:31:37 PM PDT 24 |
Jun 06 01:31:43 PM PDT 24 |
2007483630 ps |
| T77 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2437840195 |
|
|
Jun 06 01:31:26 PM PDT 24 |
Jun 06 01:32:21 PM PDT 24 |
26535491960 ps |
| T975 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3355759025 |
|
|
Jun 06 01:31:19 PM PDT 24 |
Jun 06 01:31:21 PM PDT 24 |
160653418 ps |
| T78 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1326321356 |
|
|
Jun 06 01:31:38 PM PDT 24 |
Jun 06 01:31:40 PM PDT 24 |
75097379 ps |
| T79 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1372483058 |
|
|
Jun 06 01:31:20 PM PDT 24 |
Jun 06 01:31:22 PM PDT 24 |
68420525 ps |
| T80 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.396564 |
|
|
Jun 06 01:31:22 PM PDT 24 |
Jun 06 01:31:53 PM PDT 24 |
7451235577 ps |
| T976 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1730781019 |
|
|
Jun 06 01:31:25 PM PDT 24 |
Jun 06 01:31:31 PM PDT 24 |
410758342 ps |
| T977 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1091732870 |
|
|
Jun 06 01:31:17 PM PDT 24 |
Jun 06 01:31:19 PM PDT 24 |
163708011 ps |
| T978 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.654692038 |
|
|
Jun 06 01:31:26 PM PDT 24 |
Jun 06 01:31:29 PM PDT 24 |
47437658 ps |
| T121 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.4180884116 |
|
|
Jun 06 01:31:26 PM PDT 24 |
Jun 06 01:31:30 PM PDT 24 |
103727108 ps |
| T81 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2652892912 |
|
|
Jun 06 01:31:22 PM PDT 24 |
Jun 06 01:32:16 PM PDT 24 |
7224529606 ps |
| T979 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2428225901 |
|
|
Jun 06 01:31:38 PM PDT 24 |
Jun 06 01:31:43 PM PDT 24 |
366512386 ps |
| T980 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2371518415 |
|
|
Jun 06 01:31:19 PM PDT 24 |
Jun 06 01:31:21 PM PDT 24 |
35086315 ps |
| T981 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.5574524 |
|
|
Jun 06 01:31:16 PM PDT 24 |
Jun 06 01:31:19 PM PDT 24 |
163774665 ps |
| T82 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2520869048 |
|
|
Jun 06 01:31:22 PM PDT 24 |
Jun 06 01:31:26 PM PDT 24 |
21568586 ps |
| T87 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.964911440 |
|
|
Jun 06 01:31:38 PM PDT 24 |
Jun 06 01:32:46 PM PDT 24 |
78437301054 ps |
| T982 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1087854306 |
|
|
Jun 06 01:31:25 PM PDT 24 |
Jun 06 01:32:00 PM PDT 24 |
15352806388 ps |
| T983 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1045325665 |
|
|
Jun 06 01:31:23 PM PDT 24 |
Jun 06 01:31:26 PM PDT 24 |
23854643 ps |
| T984 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.226497801 |
|
|
Jun 06 01:31:23 PM PDT 24 |
Jun 06 01:31:26 PM PDT 24 |
21638334 ps |
| T985 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.776053279 |
|
|
Jun 06 01:31:21 PM PDT 24 |
Jun 06 01:31:24 PM PDT 24 |
18305791 ps |
| T986 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3276212954 |
|
|
Jun 06 01:31:22 PM PDT 24 |
Jun 06 01:31:25 PM PDT 24 |
32013813 ps |
| T987 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3825493110 |
|
|
Jun 06 01:31:24 PM PDT 24 |
Jun 06 01:31:28 PM PDT 24 |
1103265021 ps |
| T988 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3643285649 |
|
|
Jun 06 01:31:35 PM PDT 24 |
Jun 06 01:31:36 PM PDT 24 |
18110169 ps |
| T989 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2561064992 |
|
|
Jun 06 01:31:37 PM PDT 24 |
Jun 06 01:31:38 PM PDT 24 |
48832330 ps |
| T88 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3670263250 |
|
|
Jun 06 01:31:37 PM PDT 24 |
Jun 06 01:32:31 PM PDT 24 |
29381728367 ps |
| T990 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.195091781 |
|
|
Jun 06 01:31:18 PM PDT 24 |
Jun 06 01:31:24 PM PDT 24 |
511762582 ps |
| T991 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2779768553 |
|
|
Jun 06 01:31:36 PM PDT 24 |
Jun 06 01:31:38 PM PDT 24 |
19367541 ps |
| T992 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1898659788 |
|
|
Jun 06 01:31:35 PM PDT 24 |
Jun 06 01:31:39 PM PDT 24 |
367391517 ps |
| T111 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.500851013 |
|
|
Jun 06 01:31:26 PM PDT 24 |
Jun 06 01:31:30 PM PDT 24 |
111857765 ps |
| T993 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1678282744 |
|
|
Jun 06 01:31:20 PM PDT 24 |
Jun 06 01:31:25 PM PDT 24 |
35936508 ps |
| T994 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1768911172 |
|
|
Jun 06 01:31:36 PM PDT 24 |
Jun 06 01:31:38 PM PDT 24 |
86290411 ps |
| T995 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2586547663 |
|
|
Jun 06 01:31:27 PM PDT 24 |
Jun 06 01:31:30 PM PDT 24 |
94415553 ps |
| T89 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.955340571 |
|
|
Jun 06 01:31:40 PM PDT 24 |
Jun 06 01:31:41 PM PDT 24 |
27577074 ps |
| T996 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2530780624 |
|
|
Jun 06 01:31:25 PM PDT 24 |
Jun 06 01:31:32 PM PDT 24 |
228925171 ps |
| T120 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.4179855318 |
|
|
Jun 06 01:31:28 PM PDT 24 |
Jun 06 01:31:32 PM PDT 24 |
229374158 ps |
| T997 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.953112784 |
|
|
Jun 06 01:31:35 PM PDT 24 |
Jun 06 01:31:40 PM PDT 24 |
138544009 ps |
| T998 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2962849622 |
|
|
Jun 06 01:31:27 PM PDT 24 |
Jun 06 01:31:31 PM PDT 24 |
121574416 ps |
| T999 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1858904957 |
|
|
Jun 06 01:31:22 PM PDT 24 |
Jun 06 01:31:25 PM PDT 24 |
48334678 ps |
| T117 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1013311843 |
|
|
Jun 06 01:31:41 PM PDT 24 |
Jun 06 01:31:44 PM PDT 24 |
309714058 ps |
| T86 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3217025408 |
|
|
Jun 06 01:31:18 PM PDT 24 |
Jun 06 01:31:20 PM PDT 24 |
27450615 ps |
| T1000 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.4057864879 |
|
|
Jun 06 01:31:25 PM PDT 24 |
Jun 06 01:31:32 PM PDT 24 |
713049039 ps |
| T1001 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.262540750 |
|
|
Jun 06 01:31:55 PM PDT 24 |
Jun 06 01:32:01 PM PDT 24 |
1417701326 ps |
| T1002 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2345833242 |
|
|
Jun 06 01:31:24 PM PDT 24 |
Jun 06 01:31:30 PM PDT 24 |
144617859 ps |
| T118 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1530237439 |
|
|
Jun 06 01:31:22 PM PDT 24 |
Jun 06 01:31:26 PM PDT 24 |
362122038 ps |
| T1003 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.85369286 |
|
|
Jun 06 01:31:28 PM PDT 24 |
Jun 06 01:31:32 PM PDT 24 |
139540262 ps |
| T1004 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1962183888 |
|
|
Jun 06 01:31:27 PM PDT 24 |
Jun 06 01:31:32 PM PDT 24 |
96753353 ps |
| T1005 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.517388746 |
|
|
Jun 06 01:31:20 PM PDT 24 |
Jun 06 01:31:22 PM PDT 24 |
111213417 ps |