Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16918913	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

160374667

1

T1

5164

T2

142553

T3

196606

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	87300375	1			T1	2833		T2	78611		T3	65536
values[0x0]	43316445	1			T1	1321		T2	37778		T3	65391
values[0x1]	46676760	1			T1	1530		T2	40278		T3	65679

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8608474	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

168685106

1

T1

5434

T2

149609

T3

196606

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	641853	1			T1	28		T2	818		T3	768
valid_sources[0x01]	582438	1			T1	28		T2	570		T3	682
valid_sources[0x02]	952729	1			T1	18		T2	540		T3	654
valid_sources[0x03]	579981	1			T1	16		T2	433		T3	768
valid_sources[0x04]	630908	1			T1	31		T2	602		T3	758
valid_sources[0x05]	581974	1			T1	32		T2	588		T3	743
valid_sources[0x06]	580254	1			T1	38		T2	605		T3	831
valid_sources[0x07]	610656	1			T1	35		T2	446		T3	767
valid_sources[0x08]	596555	1			T1	18		T2	544		T3	696
valid_sources[0x09]	578359	1			T1	22		T2	539		T3	752
valid_sources[0x0a]	577506	1			T1	30		T2	973		T3	691
valid_sources[0x0b]	564655	1			T1	15		T2	799		T3	752
valid_sources[0x0c]	662691	1			T1	10		T2	757		T3	758
valid_sources[0x0d]	674498	1			T1	23		T2	600		T3	755
valid_sources[0x0e]	639838	1			T1	18		T2	519		T3	677
valid_sources[0x0f]	581415	1			T1	20		T2	501		T3	765
valid_sources[0x10]	573724	1			T1	23		T2	661		T3	699
valid_sources[0x11]	606385	1			T1	30		T2	582		T3	760
valid_sources[0x12]	660610	1			T1	22		T2	626		T3	888
valid_sources[0x13]	1761565	1			T1	26		T2	707		T3	737
valid_sources[0x14]	654174	1			T1	21		T2	693		T3	757
valid_sources[0x15]	615388	1			T1	26		T2	522		T3	689
valid_sources[0x16]	593871	1			T1	24		T2	760		T3	828
valid_sources[0x17]	647561	1			T1	19		T2	499		T3	761
valid_sources[0x18]	1007335	1			T1	22		T2	680		T3	821
valid_sources[0x19]	654037	1			T1	21		T2	698		T3	744
valid_sources[0x1a]	592003	1			T1	22		T2	810		T3	708
valid_sources[0x1b]	593626	1			T1	20		T2	691		T3	749
valid_sources[0x1c]	569031	1			T1	17		T2	547		T3	756
valid_sources[0x1d]	576592	1			T1	19		T2	559		T3	746
valid_sources[0x1e]	2469207	1			T1	31		T2	458		T3	719
valid_sources[0x1f]	578439	1			T1	24		T2	565		T3	866
valid_sources[0x20]	618270	1			T1	28		T2	542		T3	744
valid_sources[0x21]	592965	1			T1	23		T2	395		T3	775
valid_sources[0x22]	591110	1			T1	20		T2	634		T3	674
valid_sources[0x23]	610969	1			T1	21		T2	666		T3	756
valid_sources[0x24]	1373827	1			T1	22		T2	770		T3	818
valid_sources[0x25]	751010	1			T1	22		T2	646		T3	781
valid_sources[0x26]	575786	1			T1	24		T2	626		T3	745
valid_sources[0x27]	2136721	1			T1	22		T2	671		T3	756
valid_sources[0x28]	597875	1			T1	30		T2	850		T3	760
valid_sources[0x29]	592412	1			T1	21		T2	661		T3	751
valid_sources[0x2a]	616247	1			T1	34		T2	755		T3	748
valid_sources[0x2b]	578497	1			T1	21		T2	571		T3	745
valid_sources[0x2c]	572828	1			T1	25		T2	571		T3	773
valid_sources[0x2d]	639722	1			T1	31		T2	739		T3	769
valid_sources[0x2e]	571376	1			T1	25		T2	777		T3	772
valid_sources[0x2f]	581740	1			T1	10		T2	751		T3	768
valid_sources[0x30]	581534	1			T1	19		T2	697		T3	732
valid_sources[0x31]	598973	1			T1	20		T2	631		T3	812
valid_sources[0x32]	583031	1			T1	23		T2	739		T3	844
valid_sources[0x33]	577347	1			T1	20		T2	406		T3	777
valid_sources[0x34]	565358	1			T1	19		T2	452		T3	746
valid_sources[0x35]	1586237	1			T1	29		T2	558		T3	764
valid_sources[0x36]	576887	1			T1	16		T2	460		T3	790
valid_sources[0x37]	573536	1			T1	22		T2	840		T3	728
valid_sources[0x38]	2244919	1			T1	17		T2	660		T3	859
valid_sources[0x39]	671656	1			T1	30		T2	646		T3	788
valid_sources[0x3a]	593255	1			T1	22		T2	680		T3	717
valid_sources[0x3b]	567429	1			T1	30		T2	610		T3	762
valid_sources[0x3c]	1839704	1			T1	27		T2	562		T3	764
valid_sources[0x3d]	614911	1			T1	23		T2	550		T3	757
valid_sources[0x3e]	619470	1			T1	21		T2	932		T3	771
valid_sources[0x3f]	583759	1			T1	13		T2	656		T3	682
valid_sources[0x40]	586124	1			T1	28		T2	684		T3	687
valid_sources[0x41]	570258	1			T1	16		T2	504		T3	810
valid_sources[0x42]	610291	1			T1	34		T2	623		T3	805
valid_sources[0x43]	1582834	1			T1	25		T2	588		T3	794
valid_sources[0x44]	597355	1			T1	21		T2	539		T3	788
valid_sources[0x45]	594110	1			T1	24		T2	741		T3	826
valid_sources[0x46]	625757	1			T1	18		T2	593		T3	716
valid_sources[0x47]	605047	1			T1	20		T2	621		T3	771
valid_sources[0x48]	577763	1			T1	24		T2	565		T3	757
valid_sources[0x49]	586323	1			T1	21		T2	625		T3	835
valid_sources[0x4a]	596318	1			T1	23		T2	666		T3	853
valid_sources[0x4b]	579134	1			T1	29		T2	565		T3	774
valid_sources[0x4c]	695260	1			T1	22		T2	684		T3	779
valid_sources[0x4d]	636120	1			T1	15		T2	473		T3	762
valid_sources[0x4e]	579047	1			T1	25		T2	407		T3	808
valid_sources[0x4f]	590954	1			T1	21		T2	698		T3	818
valid_sources[0x50]	625813	1			T1	17		T2	662		T3	734
valid_sources[0x51]	597468	1			T1	33		T2	628		T3	702
valid_sources[0x52]	650883	1			T1	19		T2	503		T3	795
valid_sources[0x53]	685240	1			T1	16		T2	822		T3	803
valid_sources[0x54]	608924	1			T1	12		T2	618		T3	791
valid_sources[0x55]	594064	1			T1	18		T2	655		T3	804
valid_sources[0x56]	599112	1			T1	28		T2	923		T3	855
valid_sources[0x57]	602063	1			T1	24		T2	616		T3	792
valid_sources[0x58]	591474	1			T1	20		T2	699		T3	790
valid_sources[0x59]	632021	1			T1	18		T2	667		T3	729
valid_sources[0x5a]	615257	1			T1	24		T2	623		T3	752
valid_sources[0x5b]	598157	1			T1	13		T2	648		T3	646
valid_sources[0x5c]	2210873	1			T1	13		T2	708		T3	801
valid_sources[0x5d]	647047	1			T1	29		T2	479		T3	784
valid_sources[0x5e]	599573	1			T1	17		T2	514		T3	803
valid_sources[0x5f]	609443	1			T1	30		T2	662		T3	770
valid_sources[0x60]	604236	1			T1	23		T2	643		T3	776
valid_sources[0x61]	592513	1			T1	21		T2	628		T3	778
valid_sources[0x62]	605645	1			T1	23		T2	539		T3	837
valid_sources[0x63]	587872	1			T1	13		T2	665		T3	821
valid_sources[0x64]	599332	1			T1	31		T2	491		T3	793
valid_sources[0x65]	2010073	1			T1	30		T2	633		T3	702
valid_sources[0x66]	584862	1			T1	22		T2	641		T3	822
valid_sources[0x67]	633791	1			T1	13		T2	555		T3	814
valid_sources[0x68]	593856	1			T1	14		T2	634		T3	782
valid_sources[0x69]	579656	1			T1	20		T2	470		T3	714
valid_sources[0x6a]	619762	1			T1	22		T2	591		T3	717
valid_sources[0x6b]	645587	1			T1	21		T2	462		T3	647
valid_sources[0x6c]	676730	1			T1	27		T2	466		T3	763
valid_sources[0x6d]	622987	1			T1	16		T2	612		T3	828
valid_sources[0x6e]	582590	1			T1	19		T2	620		T3	750
valid_sources[0x6f]	606052	1			T1	21		T2	428		T3	802
valid_sources[0x70]	650755	1			T1	32		T2	784		T3	696
valid_sources[0x71]	649237	1			T1	19		T2	703		T3	814
valid_sources[0x72]	573019	1			T1	26		T2	450		T3	759
valid_sources[0x73]	627381	1			T1	22		T2	488		T3	717
valid_sources[0x74]	614690	1			T1	35		T2	385		T3	743
valid_sources[0x75]	1067937	1			T1	11		T2	717		T3	736
valid_sources[0x76]	585855	1			T1	16		T2	368		T3	797
valid_sources[0x77]	613060	1			T1	34		T2	540		T3	799
valid_sources[0x78]	656434	1			T1	36		T2	678		T3	743
valid_sources[0x79]	774338	1			T1	16		T2	678		T3	679
valid_sources[0x7a]	595636	1			T1	20		T2	406		T3	796
valid_sources[0x7b]	576652	1			T1	26		T2	697		T3	747
valid_sources[0x7c]	620464	1			T1	14		T2	399		T3	768
valid_sources[0x7d]	1909480	1			T1	16		T2	791		T3	775
valid_sources[0x7e]	1715902	1			T1	19		T2	415		T3	744
valid_sources[0x7f]	645726	1			T1	19		T2	417		T3	785
valid_sources[0x80]	573324	1			T1	32		T2	526		T3	800

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

78793512

1

T1

2574

T2

71467

T3

65536

values[0x0]

all_enables

biggest_size

40791147

1

T1

1256

T2

35665

T3

65391

values[0x1]

all_enables

biggest_size

40790008

1

T1

1334

T2

35421

T3

65679

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	45116	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

153232

1

T2

11

T3

63

T5

16

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	53401	1			T2	1		T5	32		T13	13
values[0x0]	69904	1			T1	1		T2	12		T3	124
values[0x1]	75043	1			T1	1		T2	12		T3	151

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34902	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

163446

1

T2

11

T3

91

T5

21

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	805	1			T25	1		T22	3		T16	1
valid_sources[0x01]	1089	1			T20	1		T13	126		T22	26
valid_sources[0x02]	602	1			T3	2		T22	16		T16	1
valid_sources[0x03]	750	1			T34	1		T22	8		T16	2
valid_sources[0x04]	862	1			T3	2		T34	1		T22	11
valid_sources[0x05]	653	1			T3	2		T34	1		T22	5
valid_sources[0x06]	773	1			T2	4		T34	1		T22	20
valid_sources[0x07]	815	1			T3	2		T22	10		T16	2
valid_sources[0x08]	853	1			T5	1		T22	29		T16	3
valid_sources[0x09]	873	1			T3	1		T5	4		T34	2
valid_sources[0x0a]	570	1			T34	3		T49	1		T22	15
valid_sources[0x0b]	799	1			T3	2		T126	1		T22	19
valid_sources[0x0c]	617	1			T30	1		T22	6		T24	17
valid_sources[0x0d]	688	1			T22	6		T24	5		T33	11
valid_sources[0x0e]	720	1			T3	3		T25	1		T34	1
valid_sources[0x0f]	798	1			T3	3		T49	1		T22	8
valid_sources[0x10]	1188	1			T3	2		T34	1		T30	1
valid_sources[0x11]	714	1			T3	7		T20	2		T49	1
valid_sources[0x12]	911	1			T3	6		T34	3		T22	22
valid_sources[0x13]	658	1			T5	2		T25	1		T22	10
valid_sources[0x14]	670	1			T3	4		T5	1		T34	2
valid_sources[0x15]	709	1			T1	1		T34	4		T22	8
valid_sources[0x16]	706	1			T1	1		T22	17		T16	1
valid_sources[0x17]	861	1			T3	1		T11	1		T34	1
valid_sources[0x18]	925	1			T3	4		T34	1		T29	1
valid_sources[0x19]	606	1			T119	1		T22	34		T40	1
valid_sources[0x1a]	871	1			T3	2		T22	21		T16	1
valid_sources[0x1b]	823	1			T3	1		T5	1		T8	2
valid_sources[0x1c]	1349	1			T3	1		T22	3		T23	6
valid_sources[0x1d]	802	1			T3	1		T5	1		T15	1
valid_sources[0x1e]	657	1			T49	2		T16	3		T33	11
valid_sources[0x1f]	720	1			T3	3		T34	1		T127	1
valid_sources[0x20]	767	1			T15	1		T22	2		T24	14
valid_sources[0x21]	946	1			T5	4		T40	2		T23	192
valid_sources[0x22]	1022	1			T3	1		T34	1		T22	4
valid_sources[0x23]	941	1			T3	3		T34	4		T22	19
valid_sources[0x24]	710	1			T3	1		T34	1		T29	1
valid_sources[0x25]	690	1			T3	2		T5	2		T34	5
valid_sources[0x26]	632	1			T3	2		T22	6		T40	1
valid_sources[0x27]	724	1			T34	1		T30	1		T22	1
valid_sources[0x28]	731	1			T22	12		T24	25		T33	17
valid_sources[0x29]	730	1			T3	2		T22	27		T24	20
valid_sources[0x2a]	723	1			T3	1		T119	1		T22	20
valid_sources[0x2b]	684	1			T3	1		T34	1		T22	20
valid_sources[0x2c]	592	1			T3	3		T34	1		T22	12
valid_sources[0x2d]	728	1			T2	1		T8	1		T25	1
valid_sources[0x2e]	703	1			T34	1		T119	1		T22	10
valid_sources[0x2f]	619	1			T34	1		T22	6		T40	1
valid_sources[0x30]	746	1			T3	2		T34	1		T22	16
valid_sources[0x31]	608	1			T34	2		T22	8		T24	11
valid_sources[0x32]	738	1			T3	1		T22	9		T59	2
valid_sources[0x33]	788	1			T34	1		T22	3		T16	2
valid_sources[0x34]	611	1			T3	2		T25	1		T22	17
valid_sources[0x35]	702	1			T3	1		T30	1		T22	3
valid_sources[0x36]	660	1			T3	5		T34	1		T22	2
valid_sources[0x37]	643	1			T3	1		T34	2		T22	18
valid_sources[0x38]	707	1			T3	2		T34	1		T37	3
valid_sources[0x39]	898	1			T3	3		T30	1		T22	11
valid_sources[0x3a]	782	1			T34	1		T22	13		T40	1
valid_sources[0x3b]	786	1			T3	1		T34	2		T22	6
valid_sources[0x3c]	746	1			T8	1		T22	4		T128	1
valid_sources[0x3d]	1223	1			T22	6		T24	28		T33	20
valid_sources[0x3e]	686	1			T3	3		T8	1		T34	2
valid_sources[0x3f]	892	1			T20	1		T34	3		T127	2
valid_sources[0x40]	890	1			T3	1		T34	3		T127	2
valid_sources[0x41]	764	1			T34	1		T22	10		T16	2
valid_sources[0x42]	834	1			T3	1		T15	2		T22	12
valid_sources[0x43]	884	1			T3	2		T34	2		T22	9
valid_sources[0x44]	1055	1			T22	17		T16	1		T40	2
valid_sources[0x45]	583	1			T3	4		T34	1		T30	1
valid_sources[0x46]	721	1			T3	1		T25	1		T22	8
valid_sources[0x47]	653	1			T34	1		T22	12		T24	12
valid_sources[0x48]	795	1			T2	2		T3	3		T21	1
valid_sources[0x49]	759	1			T5	3		T126	1		T40	1
valid_sources[0x4a]	623	1			T3	2		T15	3		T49	1
valid_sources[0x4b]	732	1			T22	12		T40	1		T24	24
valid_sources[0x4c]	1261	1			T3	2		T22	17		T16	2
valid_sources[0x4d]	1046	1			T30	1		T22	14		T16	1
valid_sources[0x4e]	644	1			T3	3		T49	1		T30	1
valid_sources[0x4f]	777	1			T3	8		T34	2		T30	1
valid_sources[0x50]	750	1			T22	3		T16	3		T24	7
valid_sources[0x51]	931	1			T3	2		T5	1		T34	2
valid_sources[0x52]	628	1			T3	1		T20	1		T22	2
valid_sources[0x53]	730	1			T3	1		T5	4		T12	20
valid_sources[0x54]	665	1			T3	1		T5	7		T30	1
valid_sources[0x55]	703	1			T3	4		T8	1		T10	3
valid_sources[0x56]	755	1			T30	1		T22	4		T40	1
valid_sources[0x57]	685	1			T8	1		T34	4		T22	2
valid_sources[0x58]	858	1			T3	1		T49	1		T22	8
valid_sources[0x59]	675	1			T34	2		T127	1		T22	6
valid_sources[0x5a]	946	1			T3	1		T22	27		T40	2
valid_sources[0x5b]	910	1			T2	1		T9	1		T34	1
valid_sources[0x5c]	742	1			T26	1		T34	1		T22	8
valid_sources[0x5d]	784	1			T5	2		T34	2		T22	8
valid_sources[0x5e]	945	1			T22	15		T24	4		T33	11
valid_sources[0x5f]	733	1			T34	5		T22	3		T16	1
valid_sources[0x60]	869	1			T22	7		T16	3		T24	6
valid_sources[0x61]	805	1			T2	4		T25	1		T34	2
valid_sources[0x62]	644	1			T34	1		T22	5		T16	2
valid_sources[0x63]	855	1			T3	1		T34	2		T49	1
valid_sources[0x64]	978	1			T3	5		T25	2		T34	1
valid_sources[0x65]	941	1			T3	1		T22	24		T16	1
valid_sources[0x66]	648	1			T3	1		T5	6		T30	1
valid_sources[0x67]	723	1			T30	1		T22	8		T16	2
valid_sources[0x68]	728	1			T3	1		T34	2		T22	2
valid_sources[0x69]	741	1			T3	1		T34	1		T22	33
valid_sources[0x6a]	751	1			T30	2		T22	12		T16	1
valid_sources[0x6b]	743	1			T34	1		T51	3		T127	1
valid_sources[0x6c]	903	1			T30	2		T22	16		T16	1
valid_sources[0x6d]	633	1			T3	2		T22	15		T16	1
valid_sources[0x6e]	596	1			T3	1		T34	3		T22	14
valid_sources[0x6f]	740	1			T29	1		T22	10		T17	12
valid_sources[0x70]	602	1			T34	2		T22	7		T24	17
valid_sources[0x71]	759	1			T3	2		T34	1		T22	10
valid_sources[0x72]	526	1			T34	1		T22	12		T16	1
valid_sources[0x73]	722	1			T25	1		T34	2		T22	16
valid_sources[0x74]	698	1			T34	3		T129	2		T24	54
valid_sources[0x75]	837	1			T3	4		T34	1		T22	21
valid_sources[0x76]	720	1			T3	2		T34	2		T16	6
valid_sources[0x77]	649	1			T3	3		T15	3		T30	1
valid_sources[0x78]	750	1			T2	2		T22	5		T16	3
valid_sources[0x79]	1028	1			T3	1		T34	2		T22	5
valid_sources[0x7a]	600	1			T29	3		T22	5		T16	2
valid_sources[0x7b]	917	1			T20	1		T34	3		T22	6
valid_sources[0x7c]	845	1			T34	2		T22	5		T23	111
valid_sources[0x7d]	686	1			T11	1		T34	2		T30	1
valid_sources[0x7e]	770	1			T16	2		T40	1		T17	1
valid_sources[0x7f]	704	1			T34	1		T22	2		T16	5
valid_sources[0x80]	852	1			T34	3		T96	1		T22	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

40867

1

T5

15

T13

7

T22

564

values[0x0]

all_enables

biggest_size

57647

1

T2

9

T3

39

T5

1

values[0x1]

all_enables

biggest_size

54718

1

T2

2

T3

24

T8

1