Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16797118

1

T1

520

T2

12857

T5

119

full_word

157019877

1

T1

5164

T2

130231

T3

196606

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	173816675	1			T1	5684		T2	143088		T3	196606
auto[TlIntgErrCmd]	100	1			T45	5		T46	1		T47	5
auto[TlIntgErrData]	114	1			T45	1		T46	6		T47	8
auto[TlIntgErrBoth]	106	1			T45	4		T46	3		T47	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

83721660

1

T1

2833

T2

65032

T3

65536

auto[1]

90095335

1

T1

2851

T2

78056

T3

131070

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	8220450	1			T1	259		T2	5887		T5	59
auto[TlIntgErrNone]	partial	auto[1]	8576370	1			T1	261		T2	6970		T5	60
auto[TlIntgErrNone]	full_word	auto[0]	75501062	1			T1	2574		T2	59145		T3	65536
auto[TlIntgErrNone]	full_word	auto[1]	81518793	1			T1	2590		T2	71086		T3	131070
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T45	2		T47	2		T107	3
auto[TlIntgErrCmd]	partial	auto[1]	56	1			T45	3		T46	1		T47	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T47	1		T109	2		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T115	1		T116	1		T111	1
auto[TlIntgErrData]	partial	auto[0]	58	1			T46	4		T47	3		T107	2
auto[TlIntgErrData]	partial	auto[1]	50	1			T45	1		T46	2		T47	5
auto[TlIntgErrData]	full_word	auto[0]	5	1			T107	1		T115	1		T114	2
auto[TlIntgErrData]	full_word	auto[1]	1	1			T117	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T45	1		T46	1		T47	3
auto[TlIntgErrBoth]	partial	auto[1]	58	1			T45	3		T46	2		T47	3
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T108	2		T115	1		T118	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T47	1		T115	1		T114	1