Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	651005	1			T28	1341		T25	3077		T29	11442
auto[1]	11492405	1			T1	2807		T2	27903		T5	581
auto[2]	500395	1			T28	897		T25	2114		T29	10565
auto[3]	11238391	1			T1	2814		T2	26667		T5	533

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	15013734	1			T1	4684		T2	45288		T5	924
auto[1]	2247910	1			T1	454		T2	4409		T5	89
auto[2]	2263492	1			T1	450		T2	4436		T5	92
auto[3]	4357060	1			T1	33		T2	437		T5	9

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10394722

1

T1

5621

T2

54569

T5

1114

auto[1]

13487474

1

T2

1

T11

214196

T48

32532

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	259648	1			T28	39		T25	2561		T29	9464
auto[0]	auto[0]	auto[1]	26885	1			T28	186		T25	244		T29	931
auto[0]	auto[0]	auto[2]	26855	1			T28	182		T25	246		T29	969
auto[0]	auto[0]	auto[3]	48084	1			T28	934		T25	26		T29	78
auto[0]	auto[1]	auto[0]	3776807	1			T1	2339		T2	23106		T5	490
auto[0]	auto[1]	auto[1]	393099	1			T1	211		T2	2262		T5	37
auto[0]	auto[1]	auto[2]	411071	1			T1	240		T2	2313		T5	49
auto[0]	auto[1]	auto[3]	402417	1			T1	17		T2	221		T5	5
auto[0]	auto[2]	auto[0]	187819	1			T28	40		T25	1758		T29	8920
auto[0]	auto[2]	auto[1]	22266	1			T28	172		T25	184		T29	920
auto[0]	auto[2]	auto[2]	17520	1			T28	136		T25	157		T29	655
auto[0]	auto[2]	auto[3]	37132	1			T28	549		T25	15		T29	69
auto[0]	auto[3]	auto[0]	3618774	1			T1	2345		T2	22182		T5	434
auto[0]	auto[3]	auto[1]	393242	1			T1	243		T2	2146		T5	52
auto[0]	auto[3]	auto[2]	401368	1			T1	210		T2	2123		T5	43
auto[0]	auto[3]	auto[3]	371735	1			T1	16		T2	216		T5	4
auto[1]	auto[0]	auto[0]	9473	1			T95	688		T124	703		T125	355
auto[1]	auto[0]	auto[1]	43165	1			T95	3071		T124	3478		T125	1641
auto[1]	auto[0]	auto[2]	43048	1			T95	3125		T124	3461		T125	1625
auto[1]	auto[0]	auto[3]	193847	1			T95	14025		T79	1		T124	15353
auto[1]	auto[1]	auto[0]	3576997	1			T11	88448		T48	205		T29	1
auto[1]	auto[1]	auto[1]	679861	1			T2	1		T11	8075		T48	2774
auto[1]	auto[1]	auto[2]	658748	1			T11	9000		T48	890		T13	1
auto[1]	auto[1]	auto[3]	1593405	1			T11	779		T48	12482		T95	13904
auto[1]	auto[2]	auto[0]	8186	1			T29	1		T95	645		T124	444
auto[1]	auto[2]	auto[1]	37098	1			T95	2832		T124	1979		T125	1467
auto[1]	auto[2]	auto[2]	34851	1			T95	2616		T124	3718		T125	1072
auto[1]	auto[2]	auto[3]	155523	1			T95	11781		T124	16537		T125	4999
auto[1]	auto[3]	auto[0]	3576030	1			T11	90097		T48	197		T13	2
auto[1]	auto[3]	auto[1]	652294	1			T11	8903		T48	931		T95	261
auto[1]	auto[3]	auto[2]	670031	1			T11	8066		T48	2712		T13	1
auto[1]	auto[3]	auto[3]	1554917	1			T11	828		T48	12341		T95	12108