Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
85.25	100.00	81.82	100.00		100.00	44.44	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1139492846	227226	0	0
ctrl_regwen_rd_A	1139492846	6540	0	0
exec_rd_A	1139492846	6156	0	0
exec_regwen_rd_A	1139492846	6662	0	0
readback_rd_A	1139492846	4997	0	0
readback_regwen_rd_A	1139492846	4506	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1139492846	227226	0	0
T16	564570	0	0	0
T22	119137	3809	0	0
T23	0	2927	0	0
T24	0	4949	0	0
T27	33838	0	0	0
T31	100111	0	0	0
T32	467126	0	0	0
T33	0	4634	0	0
T39	0	6418	0	0
T40	525581	0	0	0
T41	0	4401	0	0
T43	0	11894	0	0
T56	0	1904	0	0
T57	0	866	0	0
T58	0	3425	0	0
T59	68989	0	0	0
T60	71235	0	0	0
T61	158992	0	0	0
T62	500485	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1139492846	6540	0	0
T16	564570	0	0	0
T22	119137	299	0	0
T23	0	275	0	0
T27	33838	0	0	0
T31	100111	0	0	0
T32	467126	0	0	0
T33	0	191	0	0
T35	0	239	0	0
T36	0	233	0	0
T40	525581	0	0	0
T41	0	313	0	0
T58	0	130	0	0
T59	68989	0	0	0
T60	71235	0	0	0
T61	158992	0	0	0
T62	500485	0	0	0
T101	0	470	0	0
T102	0	126	0	0
T103	0	136	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1139492846	6156	0	0
T16	564570	0	0	0
T22	119137	270	0	0
T23	0	176	0	0
T27	33838	0	0	0
T31	100111	0	0	0
T32	467126	0	0	0
T33	0	172	0	0
T35	0	233	0	0
T36	0	255	0	0
T40	525581	0	0	0
T41	0	341	0	0
T58	0	125	0	0
T59	68989	0	0	0
T60	71235	0	0	0
T61	158992	0	0	0
T62	500485	0	0	0
T101	0	405	0	0
T102	0	99	0	0
T103	0	132	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1139492846	6662	0	0
T16	564570	0	0	0
T22	119137	225	0	0
T23	0	244	0	0
T27	33838	0	0	0
T31	100111	0	0	0
T32	467126	0	0	0
T33	0	167	0	0
T35	0	223	0	0
T36	0	285	0	0
T40	525581	0	0	0
T41	0	473	0	0
T58	0	122	0	0
T59	68989	0	0	0
T60	71235	0	0	0
T61	158992	0	0	0
T62	500485	0	0	0
T101	0	536	0	0
T102	0	73	0	0
T103	0	79	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1139492846	4997	0	0
T16	564570	0	0	0
T22	119137	246	0	0
T23	0	238	0	0
T27	33838	0	0	0
T31	100111	0	0	0
T32	467126	0	0	0
T33	0	157	0	0
T35	0	243	0	0
T36	0	241	0	0
T40	525581	0	0	0
T41	0	340	0	0
T58	0	134	0	0
T59	68989	0	0	0
T60	71235	0	0	0
T61	158992	0	0	0
T62	500485	0	0	0
T101	0	334	0	0
T102	0	122	0	0
T103	0	126	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1139492846	4506	0	0
T16	564570	0	0	0
T22	119137	180	0	0
T23	0	173	0	0
T27	33838	0	0	0
T31	100111	0	0	0
T32	467126	0	0	0
T33	0	109	0	0
T35	0	273	0	0
T36	0	152	0	0
T40	525581	0	0	0
T41	0	262	0	0
T58	0	127	0	0
T59	68989	0	0	0
T60	71235	0	0	0
T61	158992	0	0	0
T62	500485	0	0	0
T101	0	458	0	0
T102	0	65	0	0
T103	0	126	0	0