Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

---

Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	336707582	1			T1	11786		T2	12990		T3	73532
instr_valid_dis	300858026	1			T1	11786		T2	12990		T3	73532
instr_en	27380035	1			T28	191518		T29	144894		T22	1648

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	18256358	1			T28	50936		T29	32892		T30	47674
sram_ifetch_valid_disable	296823266	1			T1	11786		T2	12990		T3	73532
sram_ifetch_enable	21627958	1			T28	277692		T29	115894		T30	38762

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	336707582	1			T1	11786		T2	12990		T3	73532
hw_debug_en_valid_off	298109021	1			T1	11786		T2	12990		T9	393212
hw_debug_en_on	27204835	1			T3	73532		T14	331725		T15	2566

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	296823266	1			T1	11786		T2	12990		T3	73532
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	284327270	1			T1	11786		T2	12990		T3	73532
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9110803	1			T28	79372		T29	112818		T22	1648
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	7934572	1			T29	19600		T30	45132		T20	105998
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1973804	1			T30	29776		T20	105998		T6	22640
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	5110452	1			T29	19600		T30	15356		T8	17650
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	7832014	1			T29	13292		T30	2542		T20	19074
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	5074322	1			T29	13292		T20	19074		T6	105560
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	2032148	1			T118	112692		T62	8836		T128	31752
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	11663205	1			T3	73532		T14	331725		T15	2566
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	6096456	1			T3	73532		T14	331725		T28	14494
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4193009	1			T28	9136		T29	73454		T30	35248

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	9753992	1			T28	61210		T29	12476		T30	17504
lc_exec_en	7709616	1			T28	194506		T29	47886		T30	18762
valid_exec_dis	289466695	1			T1	11786		T2	12990		T9	393212
invalid_exec_dis	39884316	1			T28	328628		T29	148786		T30	86436