Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	139014833	1			T1	4844		T2	1206		T3	20105
triple_byte_access	2733286	1			T1	211		T2	1083		T3	399
halfword_access	4195223	1			T1	319		T2	1571		T3	609
byte_access	5854007	1			T1	415		T2	2127		T3	794
zero_access	1761088	1			T1	104		T2	508		T3	191

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

76546823

1

T1

2915

T2

3243

T3

14721

auto[1]

77011614

1

T1

2978

T2

3252

T3

7377

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	69143093	1			T1	2405		T2	617		T3	13364
auto[0]	triple_byte_access	1307578	1			T1	103		T2	551		T3	265
auto[0]	halfword_access	2051847	1			T1	155		T2	784		T3	417
auto[0]	byte_access	2997095	1			T1	198		T2	1027		T3	557
auto[0]	zero_access	1047210	1			T1	54		T2	264		T3	118
auto[1]	word_access	69871740	1			T1	2439		T2	589		T3	6741
auto[1]	triple_byte_access	1425708	1			T1	108		T2	532		T3	134
auto[1]	halfword_access	2143376	1			T1	164		T2	787		T3	192
auto[1]	byte_access	2856912	1			T1	217		T2	1100		T3	237
auto[1]	zero_access	713878	1			T1	50		T2	244		T3	73