| T788 |
/workspace/coverage/default/46.sram_ctrl_smoke.3857564194 |
|
|
Jun 09 01:03:49 PM PDT 24 |
Jun 09 01:04:03 PM PDT 24 |
2587210793 ps |
| T789 |
/workspace/coverage/default/47.sram_ctrl_regwen.1359354178 |
|
|
Jun 09 01:04:06 PM PDT 24 |
Jun 09 01:04:50 PM PDT 24 |
5871649947 ps |
| T790 |
/workspace/coverage/default/34.sram_ctrl_stress_all.3921773290 |
|
|
Jun 09 01:01:27 PM PDT 24 |
Jun 09 03:22:45 PM PDT 24 |
93915080612 ps |
| T791 |
/workspace/coverage/default/16.sram_ctrl_partial_access_b2b.3081283498 |
|
|
Jun 09 12:58:09 PM PDT 24 |
Jun 09 01:02:54 PM PDT 24 |
77498945685 ps |
| T792 |
/workspace/coverage/default/42.sram_ctrl_multiple_keys.2154347958 |
|
|
Jun 09 01:02:58 PM PDT 24 |
Jun 09 01:19:50 PM PDT 24 |
45198652316 ps |
| T793 |
/workspace/coverage/default/46.sram_ctrl_mem_walk.116568828 |
|
|
Jun 09 01:03:54 PM PDT 24 |
Jun 09 01:06:08 PM PDT 24 |
2058555476 ps |
| T794 |
/workspace/coverage/default/9.sram_ctrl_executable.2810721978 |
|
|
Jun 09 12:57:19 PM PDT 24 |
Jun 09 01:09:08 PM PDT 24 |
11832288987 ps |
| T795 |
/workspace/coverage/default/30.sram_ctrl_bijection.1042736718 |
|
|
Jun 09 01:00:34 PM PDT 24 |
Jun 09 01:18:22 PM PDT 24 |
64896218717 ps |
| T796 |
/workspace/coverage/default/28.sram_ctrl_multiple_keys.155617191 |
|
|
Jun 09 01:00:19 PM PDT 24 |
Jun 09 01:02:15 PM PDT 24 |
12937919923 ps |
| T797 |
/workspace/coverage/default/37.sram_ctrl_regwen.2913336587 |
|
|
Jun 09 01:02:03 PM PDT 24 |
Jun 09 01:21:24 PM PDT 24 |
30179491576 ps |
| T798 |
/workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.992281342 |
|
|
Jun 09 12:56:59 PM PDT 24 |
Jun 09 12:57:20 PM PDT 24 |
2949798660 ps |
| T799 |
/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.1750085783 |
|
|
Jun 09 01:00:33 PM PDT 24 |
Jun 09 01:01:44 PM PDT 24 |
3009130243 ps |
| T800 |
/workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.4143799405 |
|
|
Jun 09 12:58:15 PM PDT 24 |
Jun 09 12:59:26 PM PDT 24 |
23970125501 ps |
| T801 |
/workspace/coverage/default/47.sram_ctrl_partial_access.1032276048 |
|
|
Jun 09 01:04:01 PM PDT 24 |
Jun 09 01:04:18 PM PDT 24 |
2080911689 ps |
| T802 |
/workspace/coverage/default/21.sram_ctrl_regwen.3048235625 |
|
|
Jun 09 12:59:12 PM PDT 24 |
Jun 09 01:04:30 PM PDT 24 |
9065842513 ps |
| T803 |
/workspace/coverage/default/37.sram_ctrl_lc_escalation.2188512727 |
|
|
Jun 09 01:02:02 PM PDT 24 |
Jun 09 01:02:29 PM PDT 24 |
7317761355 ps |
| T804 |
/workspace/coverage/default/13.sram_ctrl_bijection.2583473045 |
|
|
Jun 09 12:57:46 PM PDT 24 |
Jun 09 01:36:28 PM PDT 24 |
122002570248 ps |
| T805 |
/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.2893301630 |
|
|
Jun 09 01:02:58 PM PDT 24 |
Jun 09 01:09:25 PM PDT 24 |
26216613398 ps |
| T806 |
/workspace/coverage/default/8.sram_ctrl_smoke.1962769914 |
|
|
Jun 09 12:57:08 PM PDT 24 |
Jun 09 12:57:28 PM PDT 24 |
5450601383 ps |
| T807 |
/workspace/coverage/default/21.sram_ctrl_max_throughput.2839494324 |
|
|
Jun 09 12:59:09 PM PDT 24 |
Jun 09 01:01:15 PM PDT 24 |
784475630 ps |
| T808 |
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.2851217109 |
|
|
Jun 09 12:57:29 PM PDT 24 |
Jun 09 01:00:24 PM PDT 24 |
5468467496 ps |
| T809 |
/workspace/coverage/default/26.sram_ctrl_ram_cfg.666984169 |
|
|
Jun 09 12:59:58 PM PDT 24 |
Jun 09 01:00:02 PM PDT 24 |
3350864119 ps |
| T810 |
/workspace/coverage/default/24.sram_ctrl_mem_walk.3074090358 |
|
|
Jun 09 12:59:42 PM PDT 24 |
Jun 09 01:05:07 PM PDT 24 |
14273116907 ps |
| T811 |
/workspace/coverage/default/6.sram_ctrl_regwen.2840556617 |
|
|
Jun 09 12:57:08 PM PDT 24 |
Jun 09 01:06:08 PM PDT 24 |
16885890078 ps |
| T812 |
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.3560744791 |
|
|
Jun 09 12:57:09 PM PDT 24 |
Jun 09 12:58:36 PM PDT 24 |
6163835938 ps |
| T813 |
/workspace/coverage/default/47.sram_ctrl_ram_cfg.1105085285 |
|
|
Jun 09 01:04:07 PM PDT 24 |
Jun 09 01:04:11 PM PDT 24 |
1342517585 ps |
| T814 |
/workspace/coverage/default/0.sram_ctrl_regwen.2244493745 |
|
|
Jun 09 12:56:40 PM PDT 24 |
Jun 09 12:57:35 PM PDT 24 |
62752517327 ps |
| T815 |
/workspace/coverage/default/13.sram_ctrl_executable.1574057017 |
|
|
Jun 09 12:57:48 PM PDT 24 |
Jun 09 01:13:26 PM PDT 24 |
63588845232 ps |
| T816 |
/workspace/coverage/default/36.sram_ctrl_bijection.610309712 |
|
|
Jun 09 01:01:45 PM PDT 24 |
Jun 09 01:10:57 PM PDT 24 |
8560856468 ps |
| T817 |
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.2931934593 |
|
|
Jun 09 12:57:07 PM PDT 24 |
Jun 09 12:59:38 PM PDT 24 |
5138225739 ps |
| T818 |
/workspace/coverage/default/42.sram_ctrl_executable.2268440936 |
|
|
Jun 09 01:03:05 PM PDT 24 |
Jun 09 01:10:52 PM PDT 24 |
28580013160 ps |
| T819 |
/workspace/coverage/default/4.sram_ctrl_regwen.196243030 |
|
|
Jun 09 12:56:57 PM PDT 24 |
Jun 09 01:05:18 PM PDT 24 |
33340032659 ps |
| T820 |
/workspace/coverage/default/46.sram_ctrl_bijection.534091884 |
|
|
Jun 09 01:03:49 PM PDT 24 |
Jun 09 01:19:37 PM PDT 24 |
53789144250 ps |
| T821 |
/workspace/coverage/default/38.sram_ctrl_max_throughput.737285204 |
|
|
Jun 09 01:02:08 PM PDT 24 |
Jun 09 01:02:16 PM PDT 24 |
2705032104 ps |
| T822 |
/workspace/coverage/default/25.sram_ctrl_max_throughput.2843383588 |
|
|
Jun 09 12:59:45 PM PDT 24 |
Jun 09 01:00:57 PM PDT 24 |
741869830 ps |
| T823 |
/workspace/coverage/default/3.sram_ctrl_regwen.561070988 |
|
|
Jun 09 12:56:54 PM PDT 24 |
Jun 09 12:57:08 PM PDT 24 |
823174927 ps |
| T824 |
/workspace/coverage/default/34.sram_ctrl_multiple_keys.1378157524 |
|
|
Jun 09 01:01:22 PM PDT 24 |
Jun 09 01:26:33 PM PDT 24 |
96608657302 ps |
| T825 |
/workspace/coverage/default/32.sram_ctrl_max_throughput.1955407955 |
|
|
Jun 09 01:01:02 PM PDT 24 |
Jun 09 01:03:32 PM PDT 24 |
784556649 ps |
| T826 |
/workspace/coverage/default/36.sram_ctrl_smoke.1418116788 |
|
|
Jun 09 01:01:45 PM PDT 24 |
Jun 09 01:01:51 PM PDT 24 |
420148679 ps |
| T827 |
/workspace/coverage/default/37.sram_ctrl_executable.3896402026 |
|
|
Jun 09 01:02:02 PM PDT 24 |
Jun 09 01:18:22 PM PDT 24 |
29440489292 ps |
| T828 |
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.3175020948 |
|
|
Jun 09 12:56:42 PM PDT 24 |
Jun 09 12:57:03 PM PDT 24 |
722085064 ps |
| T829 |
/workspace/coverage/default/19.sram_ctrl_multiple_keys.3780949345 |
|
|
Jun 09 12:58:42 PM PDT 24 |
Jun 09 01:04:58 PM PDT 24 |
38426147580 ps |
| T830 |
/workspace/coverage/default/26.sram_ctrl_regwen.4278970814 |
|
|
Jun 09 12:59:56 PM PDT 24 |
Jun 09 01:08:30 PM PDT 24 |
26438045481 ps |
| T831 |
/workspace/coverage/default/31.sram_ctrl_access_during_key_req.2566590288 |
|
|
Jun 09 01:00:54 PM PDT 24 |
Jun 09 01:32:14 PM PDT 24 |
28734960979 ps |
| T832 |
/workspace/coverage/default/25.sram_ctrl_access_during_key_req.3994662524 |
|
|
Jun 09 12:59:46 PM PDT 24 |
Jun 09 01:16:27 PM PDT 24 |
20064985292 ps |
| T833 |
/workspace/coverage/default/49.sram_ctrl_smoke.1641675554 |
|
|
Jun 09 01:04:23 PM PDT 24 |
Jun 09 01:06:54 PM PDT 24 |
483164587 ps |
| T834 |
/workspace/coverage/default/16.sram_ctrl_stress_all.502672569 |
|
|
Jun 09 12:58:14 PM PDT 24 |
Jun 09 01:43:26 PM PDT 24 |
29448437952 ps |
| T835 |
/workspace/coverage/default/37.sram_ctrl_max_throughput.3311720252 |
|
|
Jun 09 01:01:57 PM PDT 24 |
Jun 09 01:04:07 PM PDT 24 |
762328809 ps |
| T836 |
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.410754351 |
|
|
Jun 09 01:03:48 PM PDT 24 |
Jun 09 01:09:33 PM PDT 24 |
55905126884 ps |
| T837 |
/workspace/coverage/default/5.sram_ctrl_multiple_keys.4181662794 |
|
|
Jun 09 12:57:04 PM PDT 24 |
Jun 09 01:21:35 PM PDT 24 |
59248880610 ps |
| T838 |
/workspace/coverage/default/22.sram_ctrl_partial_access.515638241 |
|
|
Jun 09 12:59:18 PM PDT 24 |
Jun 09 12:59:31 PM PDT 24 |
507973990 ps |
| T839 |
/workspace/coverage/default/37.sram_ctrl_multiple_keys.2095634947 |
|
|
Jun 09 01:01:55 PM PDT 24 |
Jun 09 01:02:13 PM PDT 24 |
3956625453 ps |
| T840 |
/workspace/coverage/default/4.sram_ctrl_executable.1161375268 |
|
|
Jun 09 12:56:59 PM PDT 24 |
Jun 09 01:13:21 PM PDT 24 |
21602946110 ps |
| T841 |
/workspace/coverage/default/43.sram_ctrl_mem_walk.553963435 |
|
|
Jun 09 01:03:21 PM PDT 24 |
Jun 09 01:06:22 PM PDT 24 |
86445158631 ps |
| T842 |
/workspace/coverage/default/42.sram_ctrl_regwen.3745699083 |
|
|
Jun 09 01:03:04 PM PDT 24 |
Jun 09 01:13:27 PM PDT 24 |
12949441177 ps |
| T843 |
/workspace/coverage/default/43.sram_ctrl_stress_all.3642895624 |
|
|
Jun 09 01:03:26 PM PDT 24 |
Jun 09 02:20:26 PM PDT 24 |
140304769466 ps |
| T844 |
/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.1310980071 |
|
|
Jun 09 12:58:02 PM PDT 24 |
Jun 09 12:59:07 PM PDT 24 |
786735830 ps |
| T845 |
/workspace/coverage/default/31.sram_ctrl_max_throughput.3941641379 |
|
|
Jun 09 01:00:53 PM PDT 24 |
Jun 09 01:01:20 PM PDT 24 |
1496365088 ps |
| T846 |
/workspace/coverage/default/35.sram_ctrl_bijection.2411257463 |
|
|
Jun 09 01:01:31 PM PDT 24 |
Jun 09 01:11:57 PM PDT 24 |
97004860559 ps |
| T847 |
/workspace/coverage/default/27.sram_ctrl_partial_access_b2b.3357221097 |
|
|
Jun 09 01:00:03 PM PDT 24 |
Jun 09 01:06:26 PM PDT 24 |
58059640323 ps |
| T848 |
/workspace/coverage/default/39.sram_ctrl_alert_test.3896809992 |
|
|
Jun 09 01:02:28 PM PDT 24 |
Jun 09 01:02:29 PM PDT 24 |
23197233 ps |
| T849 |
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.3675565734 |
|
|
Jun 09 01:03:28 PM PDT 24 |
Jun 09 01:07:24 PM PDT 24 |
39697528384 ps |
| T850 |
/workspace/coverage/default/23.sram_ctrl_partial_access.2611525037 |
|
|
Jun 09 12:59:26 PM PDT 24 |
Jun 09 01:00:41 PM PDT 24 |
2608797811 ps |
| T851 |
/workspace/coverage/default/42.sram_ctrl_alert_test.1493902745 |
|
|
Jun 09 01:03:08 PM PDT 24 |
Jun 09 01:03:09 PM PDT 24 |
15276286 ps |
| T852 |
/workspace/coverage/default/16.sram_ctrl_alert_test.3548394465 |
|
|
Jun 09 12:58:19 PM PDT 24 |
Jun 09 12:58:19 PM PDT 24 |
35132151 ps |
| T853 |
/workspace/coverage/default/25.sram_ctrl_partial_access_b2b.2081231265 |
|
|
Jun 09 12:59:48 PM PDT 24 |
Jun 09 01:06:55 PM PDT 24 |
15654995998 ps |
| T854 |
/workspace/coverage/default/49.sram_ctrl_executable.1016059620 |
|
|
Jun 09 01:04:35 PM PDT 24 |
Jun 09 01:09:26 PM PDT 24 |
7864684382 ps |
| T855 |
/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.1039605145 |
|
|
Jun 09 01:02:38 PM PDT 24 |
Jun 09 01:04:34 PM PDT 24 |
786485547 ps |
| T856 |
/workspace/coverage/default/36.sram_ctrl_mem_walk.714640041 |
|
|
Jun 09 01:01:54 PM PDT 24 |
Jun 09 01:07:25 PM PDT 24 |
30782156997 ps |
| T857 |
/workspace/coverage/default/16.sram_ctrl_stress_pipeline.2211946383 |
|
|
Jun 09 12:58:08 PM PDT 24 |
Jun 09 01:02:23 PM PDT 24 |
14094743534 ps |
| T858 |
/workspace/coverage/default/9.sram_ctrl_stress_all.1780726056 |
|
|
Jun 09 12:57:19 PM PDT 24 |
Jun 09 02:16:08 PM PDT 24 |
160330881684 ps |
| T859 |
/workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.1928673027 |
|
|
Jun 09 01:01:02 PM PDT 24 |
Jun 09 01:01:10 PM PDT 24 |
2665036371 ps |
| T860 |
/workspace/coverage/default/33.sram_ctrl_mem_walk.2143568269 |
|
|
Jun 09 01:01:16 PM PDT 24 |
Jun 09 01:07:11 PM PDT 24 |
72819485185 ps |
| T861 |
/workspace/coverage/default/32.sram_ctrl_alert_test.255252049 |
|
|
Jun 09 01:01:10 PM PDT 24 |
Jun 09 01:01:11 PM PDT 24 |
48262515 ps |
| T862 |
/workspace/coverage/default/9.sram_ctrl_lc_escalation.180056246 |
|
|
Jun 09 12:57:19 PM PDT 24 |
Jun 09 12:58:14 PM PDT 24 |
9450931949 ps |
| T863 |
/workspace/coverage/default/48.sram_ctrl_stress_all.2046812264 |
|
|
Jun 09 01:04:17 PM PDT 24 |
Jun 09 01:58:42 PM PDT 24 |
309204817145 ps |
| T864 |
/workspace/coverage/default/16.sram_ctrl_lc_escalation.1884328857 |
|
|
Jun 09 12:58:09 PM PDT 24 |
Jun 09 12:59:17 PM PDT 24 |
29857707244 ps |
| T865 |
/workspace/coverage/default/7.sram_ctrl_bijection.1265897656 |
|
|
Jun 09 12:57:14 PM PDT 24 |
Jun 09 01:17:56 PM PDT 24 |
33471875464 ps |
| T866 |
/workspace/coverage/default/3.sram_ctrl_mem_partial_access.3303672668 |
|
|
Jun 09 12:56:52 PM PDT 24 |
Jun 09 12:58:35 PM PDT 24 |
3068432380 ps |
| T867 |
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.438099731 |
|
|
Jun 09 12:57:15 PM PDT 24 |
Jun 09 12:58:53 PM PDT 24 |
1911951443 ps |
| T868 |
/workspace/coverage/default/0.sram_ctrl_multiple_keys.3609762357 |
|
|
Jun 09 12:56:35 PM PDT 24 |
Jun 09 01:12:22 PM PDT 24 |
32738993400 ps |
| T869 |
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.1905055262 |
|
|
Jun 09 12:57:35 PM PDT 24 |
Jun 09 01:05:01 PM PDT 24 |
23021540468 ps |
| T870 |
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3184650048 |
|
|
Jun 09 12:57:15 PM PDT 24 |
Jun 09 12:59:08 PM PDT 24 |
3074487346 ps |
| T871 |
/workspace/coverage/default/25.sram_ctrl_bijection.588559452 |
|
|
Jun 09 12:59:47 PM PDT 24 |
Jun 09 01:29:41 PM PDT 24 |
141802532928 ps |
| T872 |
/workspace/coverage/default/30.sram_ctrl_access_during_key_req.859913135 |
|
|
Jun 09 01:00:35 PM PDT 24 |
Jun 09 01:15:20 PM PDT 24 |
9135514629 ps |
| T873 |
/workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.1160325415 |
|
|
Jun 09 12:56:51 PM PDT 24 |
Jun 09 12:57:27 PM PDT 24 |
7092349070 ps |
| T874 |
/workspace/coverage/default/13.sram_ctrl_stress_all.4134865439 |
|
|
Jun 09 12:57:54 PM PDT 24 |
Jun 09 01:39:50 PM PDT 24 |
40014574108 ps |
| T875 |
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.3481757632 |
|
|
Jun 09 12:56:34 PM PDT 24 |
Jun 09 01:00:45 PM PDT 24 |
3363678631 ps |
| T876 |
/workspace/coverage/default/19.sram_ctrl_stress_all.2445331739 |
|
|
Jun 09 12:58:53 PM PDT 24 |
Jun 09 03:18:14 PM PDT 24 |
1768148923084 ps |
| T877 |
/workspace/coverage/default/38.sram_ctrl_smoke.3945372023 |
|
|
Jun 09 01:02:01 PM PDT 24 |
Jun 09 01:02:20 PM PDT 24 |
1210793860 ps |
| T878 |
/workspace/coverage/default/24.sram_ctrl_alert_test.808356942 |
|
|
Jun 09 12:59:41 PM PDT 24 |
Jun 09 12:59:42 PM PDT 24 |
17364004 ps |
| T879 |
/workspace/coverage/default/31.sram_ctrl_alert_test.3562723353 |
|
|
Jun 09 01:00:59 PM PDT 24 |
Jun 09 01:01:00 PM PDT 24 |
16697711 ps |
| T880 |
/workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.2974615749 |
|
|
Jun 09 01:02:00 PM PDT 24 |
Jun 09 01:03:00 PM PDT 24 |
3083754815 ps |
| T881 |
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.1204119834 |
|
|
Jun 09 12:57:29 PM PDT 24 |
Jun 09 01:03:20 PM PDT 24 |
5690550387 ps |
| T882 |
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3708732411 |
|
|
Jun 09 12:56:47 PM PDT 24 |
Jun 09 12:57:57 PM PDT 24 |
1096078069 ps |
| T883 |
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.111832614 |
|
|
Jun 09 01:03:33 PM PDT 24 |
Jun 09 01:16:47 PM PDT 24 |
66187832379 ps |
| T884 |
/workspace/coverage/default/13.sram_ctrl_max_throughput.763126853 |
|
|
Jun 09 12:57:47 PM PDT 24 |
Jun 09 12:59:56 PM PDT 24 |
786320090 ps |
| T885 |
/workspace/coverage/default/15.sram_ctrl_mem_partial_access.640561934 |
|
|
Jun 09 12:58:03 PM PDT 24 |
Jun 09 01:00:33 PM PDT 24 |
5269876505 ps |
| T886 |
/workspace/coverage/default/48.sram_ctrl_alert_test.167461501 |
|
|
Jun 09 01:04:22 PM PDT 24 |
Jun 09 01:04:23 PM PDT 24 |
57736217 ps |
| T887 |
/workspace/coverage/default/24.sram_ctrl_mem_partial_access.1660789960 |
|
|
Jun 09 12:59:47 PM PDT 24 |
Jun 09 01:01:27 PM PDT 24 |
2948981231 ps |
| T888 |
/workspace/coverage/default/4.sram_ctrl_alert_test.4116754967 |
|
|
Jun 09 12:56:57 PM PDT 24 |
Jun 09 12:56:58 PM PDT 24 |
23566922 ps |
| T889 |
/workspace/coverage/default/32.sram_ctrl_access_during_key_req.2919283344 |
|
|
Jun 09 01:01:02 PM PDT 24 |
Jun 09 01:16:55 PM PDT 24 |
9774732922 ps |
| T890 |
/workspace/coverage/default/3.sram_ctrl_max_throughput.2419038307 |
|
|
Jun 09 12:56:51 PM PDT 24 |
Jun 09 12:59:07 PM PDT 24 |
3181111238 ps |
| T891 |
/workspace/coverage/default/19.sram_ctrl_access_during_key_req.3436024845 |
|
|
Jun 09 12:58:47 PM PDT 24 |
Jun 09 01:04:51 PM PDT 24 |
14588894483 ps |
| T892 |
/workspace/coverage/default/20.sram_ctrl_mem_partial_access.465671128 |
|
|
Jun 09 12:59:03 PM PDT 24 |
Jun 09 01:00:17 PM PDT 24 |
3033501797 ps |
| T893 |
/workspace/coverage/default/25.sram_ctrl_mem_walk.1072716158 |
|
|
Jun 09 12:59:53 PM PDT 24 |
Jun 09 01:05:28 PM PDT 24 |
25570764239 ps |
| T894 |
/workspace/coverage/default/4.sram_ctrl_stress_pipeline.518935502 |
|
|
Jun 09 12:57:04 PM PDT 24 |
Jun 09 01:03:10 PM PDT 24 |
10572984533 ps |
| T895 |
/workspace/coverage/default/44.sram_ctrl_smoke.3087654771 |
|
|
Jun 09 01:03:30 PM PDT 24 |
Jun 09 01:05:37 PM PDT 24 |
3079013591 ps |
| T896 |
/workspace/coverage/default/39.sram_ctrl_mem_walk.3603690917 |
|
|
Jun 09 01:02:23 PM PDT 24 |
Jun 09 01:08:39 PM PDT 24 |
94386684768 ps |
| T897 |
/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.2748926562 |
|
|
Jun 09 01:01:48 PM PDT 24 |
Jun 09 01:09:44 PM PDT 24 |
20705891632 ps |
| T898 |
/workspace/coverage/default/7.sram_ctrl_regwen.3835194519 |
|
|
Jun 09 12:57:08 PM PDT 24 |
Jun 09 01:01:18 PM PDT 24 |
39879047136 ps |
| T899 |
/workspace/coverage/default/31.sram_ctrl_mem_partial_access.2057506041 |
|
|
Jun 09 01:00:57 PM PDT 24 |
Jun 09 01:03:38 PM PDT 24 |
16168503072 ps |
| T900 |
/workspace/coverage/default/15.sram_ctrl_smoke.2085843738 |
|
|
Jun 09 12:58:08 PM PDT 24 |
Jun 09 12:58:18 PM PDT 24 |
369534974 ps |
| T901 |
/workspace/coverage/default/22.sram_ctrl_alert_test.2191087887 |
|
|
Jun 09 12:59:23 PM PDT 24 |
Jun 09 12:59:24 PM PDT 24 |
38159236 ps |
| T902 |
/workspace/coverage/default/44.sram_ctrl_alert_test.4204988189 |
|
|
Jun 09 01:03:32 PM PDT 24 |
Jun 09 01:03:33 PM PDT 24 |
14834065 ps |
| T903 |
/workspace/coverage/default/20.sram_ctrl_max_throughput.3788094303 |
|
|
Jun 09 12:58:57 PM PDT 24 |
Jun 09 12:59:11 PM PDT 24 |
732775041 ps |
| T904 |
/workspace/coverage/default/15.sram_ctrl_lc_escalation.2956825783 |
|
|
Jun 09 12:58:08 PM PDT 24 |
Jun 09 12:59:30 PM PDT 24 |
13026863847 ps |
| T905 |
/workspace/coverage/default/10.sram_ctrl_mem_walk.2210856396 |
|
|
Jun 09 12:57:29 PM PDT 24 |
Jun 09 01:00:15 PM PDT 24 |
14120780183 ps |
| T906 |
/workspace/coverage/default/18.sram_ctrl_max_throughput.258829026 |
|
|
Jun 09 12:58:30 PM PDT 24 |
Jun 09 12:58:38 PM PDT 24 |
1344300357 ps |
| T907 |
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.4125769441 |
|
|
Jun 09 01:03:42 PM PDT 24 |
Jun 09 01:03:48 PM PDT 24 |
299138665 ps |
| T908 |
/workspace/coverage/default/22.sram_ctrl_mem_partial_access.2414515393 |
|
|
Jun 09 12:59:26 PM PDT 24 |
Jun 09 01:00:43 PM PDT 24 |
4623441997 ps |
| T909 |
/workspace/coverage/default/15.sram_ctrl_max_throughput.919358633 |
|
|
Jun 09 12:58:08 PM PDT 24 |
Jun 09 12:58:29 PM PDT 24 |
745136812 ps |
| T910 |
/workspace/coverage/default/11.sram_ctrl_smoke.1507402053 |
|
|
Jun 09 12:57:29 PM PDT 24 |
Jun 09 12:57:54 PM PDT 24 |
4987305346 ps |
| T911 |
/workspace/coverage/default/36.sram_ctrl_mem_partial_access.4104622345 |
|
|
Jun 09 01:01:49 PM PDT 24 |
Jun 09 01:03:11 PM PDT 24 |
8316120214 ps |
| T912 |
/workspace/coverage/default/30.sram_ctrl_multiple_keys.1812254802 |
|
|
Jun 09 01:00:34 PM PDT 24 |
Jun 09 01:04:52 PM PDT 24 |
8787415188 ps |
| T913 |
/workspace/coverage/default/14.sram_ctrl_ram_cfg.3141240181 |
|
|
Jun 09 12:57:59 PM PDT 24 |
Jun 09 12:58:02 PM PDT 24 |
358306694 ps |
| T914 |
/workspace/coverage/default/11.sram_ctrl_mem_walk.4120220385 |
|
|
Jun 09 12:57:37 PM PDT 24 |
Jun 09 01:02:19 PM PDT 24 |
8047278407 ps |
| T915 |
/workspace/coverage/default/27.sram_ctrl_multiple_keys.2270193007 |
|
|
Jun 09 01:00:03 PM PDT 24 |
Jun 09 01:10:05 PM PDT 24 |
16702438147 ps |
| T916 |
/workspace/coverage/default/40.sram_ctrl_bijection.2993977911 |
|
|
Jun 09 01:02:29 PM PDT 24 |
Jun 09 01:31:15 PM PDT 24 |
104073849508 ps |
| T917 |
/workspace/coverage/default/18.sram_ctrl_smoke.1399025292 |
|
|
Jun 09 12:58:25 PM PDT 24 |
Jun 09 12:59:12 PM PDT 24 |
3906094318 ps |
| T918 |
/workspace/coverage/default/5.sram_ctrl_max_throughput.534598019 |
|
|
Jun 09 12:57:06 PM PDT 24 |
Jun 09 12:58:39 PM PDT 24 |
3479221504 ps |
| T919 |
/workspace/coverage/default/33.sram_ctrl_multiple_keys.17917299 |
|
|
Jun 09 01:01:14 PM PDT 24 |
Jun 09 01:08:27 PM PDT 24 |
13152272492 ps |
| T920 |
/workspace/coverage/default/27.sram_ctrl_stress_all.2606915784 |
|
|
Jun 09 01:00:10 PM PDT 24 |
Jun 09 01:39:10 PM PDT 24 |
96938974408 ps |
| T921 |
/workspace/coverage/default/29.sram_ctrl_lc_escalation.1115972567 |
|
|
Jun 09 01:00:31 PM PDT 24 |
Jun 09 01:01:04 PM PDT 24 |
19658043008 ps |
| T922 |
/workspace/coverage/default/15.sram_ctrl_ram_cfg.2661102354 |
|
|
Jun 09 12:58:09 PM PDT 24 |
Jun 09 12:58:13 PM PDT 24 |
353381429 ps |
| T923 |
/workspace/coverage/default/24.sram_ctrl_smoke.3808712764 |
|
|
Jun 09 12:59:34 PM PDT 24 |
Jun 09 12:59:53 PM PDT 24 |
561845804 ps |
| T924 |
/workspace/coverage/default/22.sram_ctrl_ram_cfg.1083374492 |
|
|
Jun 09 12:59:20 PM PDT 24 |
Jun 09 12:59:23 PM PDT 24 |
376654774 ps |
| T925 |
/workspace/coverage/default/19.sram_ctrl_mem_walk.409774440 |
|
|
Jun 09 12:58:48 PM PDT 24 |
Jun 09 01:04:17 PM PDT 24 |
172380012821 ps |
| T926 |
/workspace/coverage/default/37.sram_ctrl_stress_all.1608764025 |
|
|
Jun 09 01:02:02 PM PDT 24 |
Jun 09 01:49:01 PM PDT 24 |
31512345969 ps |
| T927 |
/workspace/coverage/default/14.sram_ctrl_alert_test.913390232 |
|
|
Jun 09 12:58:02 PM PDT 24 |
Jun 09 12:58:03 PM PDT 24 |
138838542 ps |
| T928 |
/workspace/coverage/default/27.sram_ctrl_partial_access.2371110212 |
|
|
Jun 09 01:00:06 PM PDT 24 |
Jun 09 01:00:17 PM PDT 24 |
1496240254 ps |
| T929 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1528677055 |
|
|
Jun 09 12:26:09 PM PDT 24 |
Jun 09 12:26:13 PM PDT 24 |
1041577077 ps |
| T53 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2622621504 |
|
|
Jun 09 12:26:13 PM PDT 24 |
Jun 09 12:26:16 PM PDT 24 |
115478661 ps |
| T57 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3210610687 |
|
|
Jun 09 12:26:11 PM PDT 24 |
Jun 09 12:27:14 PM PDT 24 |
28235446244 ps |
| T930 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.142551076 |
|
|
Jun 09 12:26:12 PM PDT 24 |
Jun 09 12:26:16 PM PDT 24 |
452372127 ps |
| T931 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.908195987 |
|
|
Jun 09 12:26:04 PM PDT 24 |
Jun 09 12:26:08 PM PDT 24 |
693012541 ps |
| T58 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1120067905 |
|
|
Jun 09 12:26:12 PM PDT 24 |
Jun 09 12:26:14 PM PDT 24 |
58335868 ps |
| T932 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.809519875 |
|
|
Jun 09 12:26:39 PM PDT 24 |
Jun 09 12:26:43 PM PDT 24 |
1449699228 ps |
| T933 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2747783414 |
|
|
Jun 09 12:26:42 PM PDT 24 |
Jun 09 12:26:46 PM PDT 24 |
68174060 ps |
| T934 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3125279931 |
|
|
Jun 09 12:26:13 PM PDT 24 |
Jun 09 12:26:17 PM PDT 24 |
68477051 ps |
| T935 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1907392746 |
|
|
Jun 09 12:26:00 PM PDT 24 |
Jun 09 12:26:03 PM PDT 24 |
66510869 ps |
| T65 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1623569410 |
|
|
Jun 09 12:26:37 PM PDT 24 |
Jun 09 12:26:38 PM PDT 24 |
23744048 ps |
| T66 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2332315812 |
|
|
Jun 09 12:26:01 PM PDT 24 |
Jun 09 12:26:31 PM PDT 24 |
7399843223 ps |
| T54 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2724911563 |
|
|
Jun 09 12:26:12 PM PDT 24 |
Jun 09 12:26:15 PM PDT 24 |
382009707 ps |
| T55 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.4157735013 |
|
|
Jun 09 12:26:09 PM PDT 24 |
Jun 09 12:26:11 PM PDT 24 |
138658252 ps |
| T936 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3078197277 |
|
|
Jun 09 12:26:46 PM PDT 24 |
Jun 09 12:26:50 PM PDT 24 |
2856323264 ps |
| T937 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1704945027 |
|
|
Jun 09 12:27:07 PM PDT 24 |
Jun 09 12:27:10 PM PDT 24 |
19603935 ps |
| T67 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3523938737 |
|
|
Jun 09 12:26:42 PM PDT 24 |
Jun 09 12:26:43 PM PDT 24 |
44741813 ps |
| T68 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.210346050 |
|
|
Jun 09 12:26:11 PM PDT 24 |
Jun 09 12:26:12 PM PDT 24 |
17214023 ps |
| T69 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2274321116 |
|
|
Jun 09 12:26:37 PM PDT 24 |
Jun 09 12:27:06 PM PDT 24 |
14799073515 ps |
| T109 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1830680359 |
|
|
Jun 09 12:26:05 PM PDT 24 |
Jun 09 12:26:08 PM PDT 24 |
614682507 ps |
| T70 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3638363969 |
|
|
Jun 09 12:26:15 PM PDT 24 |
Jun 09 12:26:44 PM PDT 24 |
15582556212 ps |
| T105 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1584092220 |
|
|
Jun 09 12:26:52 PM PDT 24 |
Jun 09 12:26:55 PM PDT 24 |
186197093 ps |
| T71 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1557314487 |
|
|
Jun 09 12:26:39 PM PDT 24 |
Jun 09 12:26:40 PM PDT 24 |
16155014 ps |
| T72 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2378616052 |
|
|
Jun 09 12:26:02 PM PDT 24 |
Jun 09 12:26:03 PM PDT 24 |
14441065 ps |
| T938 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.515102634 |
|
|
Jun 09 12:26:20 PM PDT 24 |
Jun 09 12:26:24 PM PDT 24 |
370318613 ps |
| T88 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3298383958 |
|
|
Jun 09 12:25:59 PM PDT 24 |
Jun 09 12:26:00 PM PDT 24 |
23491374 ps |
| T74 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2831480907 |
|
|
Jun 09 12:26:30 PM PDT 24 |
Jun 09 12:26:31 PM PDT 24 |
127741556 ps |
| T75 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3975383694 |
|
|
Jun 09 12:26:04 PM PDT 24 |
Jun 09 12:26:56 PM PDT 24 |
44380320915 ps |
| T939 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.4241079867 |
|
|
Jun 09 12:26:08 PM PDT 24 |
Jun 09 12:26:13 PM PDT 24 |
1667914740 ps |
| T940 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.868215865 |
|
|
Jun 09 12:26:45 PM PDT 24 |
Jun 09 12:26:46 PM PDT 24 |
11733090 ps |
| T941 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1163222202 |
|
|
Jun 09 12:26:12 PM PDT 24 |
Jun 09 12:26:18 PM PDT 24 |
139315400 ps |
| T942 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3503343856 |
|
|
Jun 09 12:26:52 PM PDT 24 |
Jun 09 12:26:55 PM PDT 24 |
313291372 ps |
| T943 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3579549511 |
|
|
Jun 09 12:26:04 PM PDT 24 |
Jun 09 12:26:05 PM PDT 24 |
19282647 ps |
| T76 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3201086435 |
|
|
Jun 09 12:26:51 PM PDT 24 |
Jun 09 12:27:42 PM PDT 24 |
7856223174 ps |
| T944 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.4074635988 |
|
|
Jun 09 12:26:12 PM PDT 24 |
Jun 09 12:26:17 PM PDT 24 |
736972721 ps |
| T945 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1743087893 |
|
|
Jun 09 12:26:06 PM PDT 24 |
Jun 09 12:26:07 PM PDT 24 |
41232551 ps |
| T77 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1819281669 |
|
|
Jun 09 12:26:05 PM PDT 24 |
Jun 09 12:26:34 PM PDT 24 |
3789955525 ps |
| T946 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1444017759 |
|
|
Jun 09 12:26:10 PM PDT 24 |
Jun 09 12:26:14 PM PDT 24 |
352260548 ps |
| T947 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.395090582 |
|
|
Jun 09 12:26:10 PM PDT 24 |
Jun 09 12:26:11 PM PDT 24 |
58171317 ps |
| T78 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3599519294 |
|
|
Jun 09 12:26:15 PM PDT 24 |
Jun 09 12:26:17 PM PDT 24 |
76194465 ps |
| T106 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.294942466 |
|
|
Jun 09 12:26:03 PM PDT 24 |
Jun 09 12:26:06 PM PDT 24 |
533716778 ps |
| T948 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.750582035 |
|
|
Jun 09 12:26:08 PM PDT 24 |
Jun 09 12:26:10 PM PDT 24 |
55314991 ps |
| T949 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3460898621 |
|
|
Jun 09 12:26:57 PM PDT 24 |
Jun 09 12:26:59 PM PDT 24 |
101643967 ps |
| T108 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2016440047 |
|
|
Jun 09 12:26:03 PM PDT 24 |
Jun 09 12:26:05 PM PDT 24 |
92899575 ps |
| T950 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1129331652 |
|
|
Jun 09 12:26:10 PM PDT 24 |
Jun 09 12:26:38 PM PDT 24 |
3879992794 ps |
| T951 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1161744231 |
|
|
Jun 09 12:26:02 PM PDT 24 |
Jun 09 12:26:06 PM PDT 24 |
1855901081 ps |
| T952 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1776855153 |
|
|
Jun 09 12:26:49 PM PDT 24 |
Jun 09 12:26:52 PM PDT 24 |
64550244 ps |
| T107 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3198768633 |
|
|
Jun 09 12:26:08 PM PDT 24 |
Jun 09 12:26:11 PM PDT 24 |
358835772 ps |
| T953 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1595438302 |
|
|
Jun 09 12:26:51 PM PDT 24 |
Jun 09 12:26:55 PM PDT 24 |
351838071 ps |
| T110 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.745115843 |
|
|
Jun 09 12:26:11 PM PDT 24 |
Jun 09 12:26:14 PM PDT 24 |
403740310 ps |
| T112 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.4266973008 |
|
|
Jun 09 12:26:11 PM PDT 24 |
Jun 09 12:26:13 PM PDT 24 |
206653370 ps |
| T954 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2291649243 |
|
|
Jun 09 12:26:11 PM PDT 24 |
Jun 09 12:26:16 PM PDT 24 |
36763307 ps |
| T955 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3579678301 |
|
|
Jun 09 12:26:08 PM PDT 24 |
Jun 09 12:26:13 PM PDT 24 |
1464250582 ps |
| T83 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.375526137 |
|
|
Jun 09 12:26:14 PM PDT 24 |
Jun 09 12:26:18 PM PDT 24 |
180554645 ps |
| T956 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.741505481 |
|
|
Jun 09 12:26:13 PM PDT 24 |
Jun 09 12:26:18 PM PDT 24 |
727355599 ps |
| T957 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2063916731 |
|
|
Jun 09 12:25:59 PM PDT 24 |
Jun 09 12:26:03 PM PDT 24 |
346815457 ps |
| T958 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1660108167 |
|
|
Jun 09 12:26:51 PM PDT 24 |
Jun 09 12:26:52 PM PDT 24 |
49769466 ps |
| T84 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.4266982575 |
|
|
Jun 09 12:26:01 PM PDT 24 |
Jun 09 12:26:02 PM PDT 24 |
40100768 ps |
| T959 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3465314651 |
|
|
Jun 09 12:26:00 PM PDT 24 |
Jun 09 12:26:02 PM PDT 24 |
119486849 ps |
| T960 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2338457730 |
|
|
Jun 09 12:26:06 PM PDT 24 |
Jun 09 12:26:10 PM PDT 24 |
86858600 ps |
| T961 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2277543510 |
|
|
Jun 09 12:26:00 PM PDT 24 |
Jun 09 12:26:03 PM PDT 24 |
135278637 ps |
| T962 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1931125365 |
|
|
Jun 09 12:26:13 PM PDT 24 |
Jun 09 12:26:15 PM PDT 24 |
69266536 ps |
| T963 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2898561852 |
|
|
Jun 09 12:26:07 PM PDT 24 |
Jun 09 12:26:08 PM PDT 24 |
217328127 ps |
| T85 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1673473139 |
|
|
Jun 09 12:26:03 PM PDT 24 |
Jun 09 12:26:58 PM PDT 24 |
17128924314 ps |
| T964 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2037613356 |
|
|
Jun 09 12:26:08 PM PDT 24 |
Jun 09 12:26:36 PM PDT 24 |
14847593903 ps |
| T965 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1144008284 |
|
|
Jun 09 12:25:58 PM PDT 24 |
Jun 09 12:25:59 PM PDT 24 |
15831082 ps |
| T966 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3860975701 |
|
|
Jun 09 12:26:17 PM PDT 24 |
Jun 09 12:26:18 PM PDT 24 |
18770639 ps |
| T967 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3639598147 |
|
|
Jun 09 12:27:07 PM PDT 24 |
Jun 09 12:27:10 PM PDT 24 |
14639335 ps |
| T968 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2732792233 |
|
|
Jun 09 12:26:11 PM PDT 24 |
Jun 09 12:26:13 PM PDT 24 |
11662610 ps |
| T969 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.250365020 |
|
|
Jun 09 12:26:05 PM PDT 24 |
Jun 09 12:26:09 PM PDT 24 |
489555988 ps |
| T970 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2809678206 |
|
|
Jun 09 12:26:11 PM PDT 24 |
Jun 09 12:26:41 PM PDT 24 |
9474208964 ps |
| T86 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1454222742 |
|
|
Jun 09 12:26:11 PM PDT 24 |
Jun 09 12:26:42 PM PDT 24 |
14794552337 ps |
| T971 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3672918817 |
|
|
Jun 09 12:26:40 PM PDT 24 |
Jun 09 12:26:44 PM PDT 24 |
150895028 ps |
| T972 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1173940752 |
|
|
Jun 09 12:25:55 PM PDT 24 |
Jun 09 12:26:00 PM PDT 24 |
224347649 ps |
| T973 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2759800810 |
|
|
Jun 09 12:26:07 PM PDT 24 |
Jun 09 12:26:09 PM PDT 24 |
22279223 ps |
| T974 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1935289760 |
|
|
Jun 09 12:27:19 PM PDT 24 |
Jun 09 12:27:23 PM PDT 24 |
350424712 ps |
| T975 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3524931495 |
|
|
Jun 09 12:26:16 PM PDT 24 |
Jun 09 12:26:17 PM PDT 24 |
20584707 ps |
| T976 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3318892087 |
|
|
Jun 09 12:26:04 PM PDT 24 |
Jun 09 12:26:05 PM PDT 24 |
40057844 ps |
| T113 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1776322433 |
|
|
Jun 09 12:26:10 PM PDT 24 |
Jun 09 12:26:13 PM PDT 24 |
358664835 ps |
| T87 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.589808149 |
|
|
Jun 09 12:26:49 PM PDT 24 |
Jun 09 12:27:16 PM PDT 24 |
7552026215 ps |
| T977 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3185992364 |
|
|
Jun 09 12:26:03 PM PDT 24 |
Jun 09 12:26:07 PM PDT 24 |
361882364 ps |
| T978 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2350700164 |
|
|
Jun 09 12:25:57 PM PDT 24 |
Jun 09 12:25:59 PM PDT 24 |
27685230 ps |
| T979 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1366315982 |
|
|
Jun 09 12:26:03 PM PDT 24 |
Jun 09 12:26:35 PM PDT 24 |
14794269018 ps |
| T980 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.825828141 |
|
|
Jun 09 12:26:47 PM PDT 24 |
Jun 09 12:27:43 PM PDT 24 |
14126706196 ps |
| T981 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.30524776 |
|
|
Jun 09 12:27:02 PM PDT 24 |
Jun 09 12:27:05 PM PDT 24 |
64604246 ps |
| T982 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3669474150 |
|
|
Jun 09 12:26:14 PM PDT 24 |
Jun 09 12:26:16 PM PDT 24 |
54532013 ps |
| T111 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2286162739 |
|
|
Jun 09 12:26:14 PM PDT 24 |
Jun 09 12:26:17 PM PDT 24 |
727026556 ps |
| T983 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3205689816 |
|
|
Jun 09 12:26:11 PM PDT 24 |
Jun 09 12:26:15 PM PDT 24 |
351692008 ps |
| T984 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2689574975 |
|
|
Jun 09 12:26:11 PM PDT 24 |
Jun 09 12:26:40 PM PDT 24 |
7620378915 ps |
| T985 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2931187499 |
|
|
Jun 09 12:26:08 PM PDT 24 |
Jun 09 12:26:10 PM PDT 24 |
44584257 ps |
| T986 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.683489206 |
|
|
Jun 09 12:26:26 PM PDT 24 |
Jun 09 12:26:27 PM PDT 24 |
50330187 ps |
| T987 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.108266061 |
|
|
Jun 09 12:26:41 PM PDT 24 |
Jun 09 12:26:43 PM PDT 24 |
82788574 ps |
| T988 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1485048976 |
|
|
Jun 09 12:26:09 PM PDT 24 |
Jun 09 12:26:13 PM PDT 24 |
686515024 ps |
| T989 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1610363139 |
|
|
Jun 09 12:26:07 PM PDT 24 |
Jun 09 12:26:11 PM PDT 24 |
38047306 ps |
| T990 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1033806952 |
|
|
Jun 09 12:26:12 PM PDT 24 |
Jun 09 12:26:19 PM PDT 24 |
6969216775 ps |
| T991 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3988951925 |
|
|
Jun 09 12:26:10 PM PDT 24 |
Jun 09 12:26:15 PM PDT 24 |
155150052 ps |
| T992 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.328600621 |
|
|
Jun 09 12:26:03 PM PDT 24 |
Jun 09 12:26:04 PM PDT 24 |
13628387 ps |
| T993 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2548628750 |
|
|
Jun 09 12:26:03 PM PDT 24 |
Jun 09 12:26:06 PM PDT 24 |
237316215 ps |
| T994 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2114954102 |
|
|
Jun 09 12:26:51 PM PDT 24 |
Jun 09 12:26:52 PM PDT 24 |
17317301 ps |
| T995 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.770655967 |
|
|
Jun 09 12:26:08 PM PDT 24 |
Jun 09 12:26:09 PM PDT 24 |
44747483 ps |
| T996 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3276673006 |
|
|
Jun 09 12:26:02 PM PDT 24 |
Jun 09 12:26:03 PM PDT 24 |
16384881 ps |
| T997 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2562350569 |
|
|
Jun 09 12:26:08 PM PDT 24 |
Jun 09 12:26:57 PM PDT 24 |
7884460307 ps |
| T998 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.33520671 |
|
|
Jun 09 12:26:10 PM PDT 24 |
Jun 09 12:26:37 PM PDT 24 |
3931968482 ps |
| T999 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2377149789 |
|
|
Jun 09 12:26:10 PM PDT 24 |
Jun 09 12:26:11 PM PDT 24 |
26169098 ps |
| T1000 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2044545930 |
|
|
Jun 09 12:25:58 PM PDT 24 |
Jun 09 12:26:01 PM PDT 24 |
257420534 ps |
| T1001 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2904075459 |
|
|
Jun 09 12:26:11 PM PDT 24 |
Jun 09 12:26:12 PM PDT 24 |
29125542 ps |
| T1002 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.498530227 |
|
|
Jun 09 12:26:05 PM PDT 24 |
Jun 09 12:26:06 PM PDT 24 |
62497866 ps |
| T1003 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.717381576 |
|
|
Jun 09 12:27:02 PM PDT 24 |
Jun 09 12:27:06 PM PDT 24 |
1935566170 ps |
| T1004 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.86583280 |
|
|
Jun 09 12:26:02 PM PDT 24 |
Jun 09 12:26:03 PM PDT 24 |
45908997 ps |