Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16527741	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

147310559

1

T1

9032

T2

7176

T3

2348

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	80584666	1			T1	4913		T2	3955		T3	1278
values[0x0]	39978936	1			T1	2351		T2	1920		T3	638
values[0x1]	43274698	1			T1	2650		T2	2037		T3	679

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8408498	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

155429802

1

T1

9491

T2

7530

T3

2455

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	513117	1			T2	17		T3	18		T4	1614
valid_sources[0x01]	601071	1			T2	47		T3	10		T4	1644
valid_sources[0x02]	533207	1			T2	40		T3	9		T4	1721
valid_sources[0x03]	534285	1			T2	31		T3	10		T4	1755
valid_sources[0x04]	543640	1			T2	67		T3	10		T4	1788
valid_sources[0x05]	553790	1			T2	32		T3	8		T4	1631
valid_sources[0x06]	562538	1			T2	36		T3	7		T4	1581
valid_sources[0x07]	541356	1			T2	24		T3	5		T4	1640
valid_sources[0x08]	570116	1			T2	23		T3	7		T4	1610
valid_sources[0x09]	542859	1			T2	35		T3	11		T4	1607
valid_sources[0x0a]	610639	1			T2	31		T3	8		T4	1695
valid_sources[0x0b]	545540	1			T2	25		T3	11		T4	1649
valid_sources[0x0c]	606108	1			T2	24		T3	9		T4	1685
valid_sources[0x0d]	522862	1			T2	12		T3	5		T4	1596
valid_sources[0x0e]	790969	1			T2	24		T3	5		T4	1646
valid_sources[0x0f]	553781	1			T2	38		T3	15		T4	1631
valid_sources[0x10]	546805	1			T2	31		T3	14		T4	1586
valid_sources[0x11]	530701	1			T2	29		T3	6		T4	1597
valid_sources[0x12]	1440162	1			T2	9		T3	10		T4	1683
valid_sources[0x13]	603225	1			T2	19		T3	8		T4	1607
valid_sources[0x14]	569581	1			T2	11		T3	20		T4	1557
valid_sources[0x15]	549770	1			T2	35		T3	7		T4	1668
valid_sources[0x16]	644590	1			T2	32		T3	13		T4	1595
valid_sources[0x17]	553398	1			T2	28		T3	12		T4	1643
valid_sources[0x18]	664786	1			T2	41		T3	7		T4	1588
valid_sources[0x19]	559864	1			T2	34		T3	8		T4	1649
valid_sources[0x1a]	557751	1			T2	34		T3	8		T4	1776
valid_sources[0x1b]	600358	1			T2	32		T3	18		T4	1666
valid_sources[0x1c]	516330	1			T2	43		T3	18		T4	1686
valid_sources[0x1d]	530450	1			T2	37		T3	13		T4	1686
valid_sources[0x1e]	637855	1			T2	32		T3	15		T4	1654
valid_sources[0x1f]	528453	1			T2	26		T3	6		T4	1696
valid_sources[0x20]	568218	1			T2	30		T3	14		T4	1792
valid_sources[0x21]	522587	1			T2	46		T3	11		T4	1606
valid_sources[0x22]	555939	1			T2	43		T3	6		T4	1585
valid_sources[0x23]	532232	1			T2	22		T3	9		T4	1657
valid_sources[0x24]	665052	1			T2	36		T3	17		T4	1645
valid_sources[0x25]	751953	1			T2	32		T3	13		T4	1603
valid_sources[0x26]	559558	1			T2	31		T3	11		T4	1609
valid_sources[0x27]	2108140	1			T2	32		T3	13		T4	1623
valid_sources[0x28]	552829	1			T2	26		T3	7		T4	1635
valid_sources[0x29]	534733	1			T2	35		T3	8		T4	1716
valid_sources[0x2a]	545767	1			T2	40		T3	5		T4	1645
valid_sources[0x2b]	554773	1			T2	35		T3	11		T4	1687
valid_sources[0x2c]	995713	1			T2	18		T3	16		T4	1676
valid_sources[0x2d]	577773	1			T2	26		T3	13		T4	1660
valid_sources[0x2e]	866193	1			T2	37		T3	17		T4	1712
valid_sources[0x2f]	540172	1			T2	29		T3	7		T4	1661
valid_sources[0x30]	556221	1			T2	21		T3	8		T4	1789
valid_sources[0x31]	528190	1			T2	34		T3	10		T4	1589
valid_sources[0x32]	572717	1			T2	40		T3	7		T4	1654
valid_sources[0x33]	608990	1			T2	16		T3	9		T4	1631
valid_sources[0x34]	523887	1			T2	29		T3	10		T4	1584
valid_sources[0x35]	525501	1			T2	49		T3	7		T4	1636
valid_sources[0x36]	550686	1			T2	23		T3	12		T4	1741
valid_sources[0x37]	529933	1			T2	34		T3	10		T4	1591
valid_sources[0x38]	512645	1			T2	31		T3	13		T4	1662
valid_sources[0x39]	532751	1			T2	43		T3	11		T4	1638
valid_sources[0x3a]	569252	1			T2	22		T3	8		T4	1669
valid_sources[0x3b]	795604	1			T2	23		T3	11		T4	1597
valid_sources[0x3c]	579329	1			T2	24		T3	7		T4	1728
valid_sources[0x3d]	536566	1			T2	25		T3	4		T4	1691
valid_sources[0x3e]	522908	1			T2	43		T3	10		T4	1709
valid_sources[0x3f]	526314	1			T2	31		T3	14		T4	1634
valid_sources[0x40]	527872	1			T2	30		T3	9		T4	1693
valid_sources[0x41]	519842	1			T2	25		T3	6		T4	1690
valid_sources[0x42]	553076	1			T2	32		T3	9		T4	1641
valid_sources[0x43]	541072	1			T2	42		T3	13		T4	1658
valid_sources[0x44]	738815	1			T2	17		T3	11		T4	1715
valid_sources[0x45]	570801	1			T2	31		T3	17		T4	1650
valid_sources[0x46]	600386	1			T2	29		T3	7		T4	1693
valid_sources[0x47]	600501	1			T2	28		T3	11		T4	1560
valid_sources[0x48]	544575	1			T2	37		T3	5		T4	1655
valid_sources[0x49]	555194	1			T2	20		T3	6		T4	1687
valid_sources[0x4a]	598094	1			T2	28		T3	8		T4	1695
valid_sources[0x4b]	540367	1			T2	27		T3	8		T4	1740
valid_sources[0x4c]	554289	1			T2	24		T3	12		T4	1615
valid_sources[0x4d]	516133	1			T2	22		T3	12		T4	1647
valid_sources[0x4e]	561580	1			T2	11		T3	10		T4	1583
valid_sources[0x4f]	625175	1			T2	18		T3	8		T4	1645
valid_sources[0x50]	512437	1			T2	38		T3	9		T4	1613
valid_sources[0x51]	539846	1			T2	30		T3	13		T4	1630
valid_sources[0x52]	522306	1			T2	29		T3	10		T4	1585
valid_sources[0x53]	514063	1			T2	34		T3	9		T4	1669
valid_sources[0x54]	547986	1			T2	34		T3	11		T4	1604
valid_sources[0x55]	521294	1			T2	34		T3	11		T4	1762
valid_sources[0x56]	602106	1			T2	28		T3	7		T4	1677
valid_sources[0x57]	700247	1			T2	34		T3	6		T4	1657
valid_sources[0x58]	527425	1			T2	31		T3	17		T4	1518
valid_sources[0x59]	1219791	1			T2	25		T3	9		T4	1641
valid_sources[0x5a]	614973	1			T2	32		T3	15		T4	1682
valid_sources[0x5b]	552975	1			T2	34		T3	3		T4	1689
valid_sources[0x5c]	537207	1			T2	45		T3	12		T4	1687
valid_sources[0x5d]	528350	1			T2	28		T3	3		T4	1689
valid_sources[0x5e]	509998	1			T2	38		T3	9		T4	1706
valid_sources[0x5f]	618607	1			T2	17		T3	7		T4	1683
valid_sources[0x60]	553709	1			T2	21		T3	10		T4	1608
valid_sources[0x61]	532509	1			T2	29		T3	7		T4	1652
valid_sources[0x62]	561961	1			T2	21		T3	6		T4	1630
valid_sources[0x63]	546718	1			T2	33		T3	13		T4	1732
valid_sources[0x64]	1436263	1			T2	22		T3	1		T4	1684
valid_sources[0x65]	2100849	1			T2	21		T3	20		T4	1631
valid_sources[0x66]	566970	1			T2	29		T3	11		T4	1633
valid_sources[0x67]	545869	1			T2	28		T3	16		T4	1648
valid_sources[0x68]	611608	1			T2	33		T3	11		T4	1680
valid_sources[0x69]	537100	1			T2	25		T3	4		T4	1724
valid_sources[0x6a]	1655811	1			T2	27		T3	16		T4	1641
valid_sources[0x6b]	583370	1			T2	27		T3	10		T4	1584
valid_sources[0x6c]	524670	1			T2	28		T3	4		T4	1622
valid_sources[0x6d]	503795	1			T2	39		T3	16		T4	1649
valid_sources[0x6e]	530001	1			T2	52		T3	10		T4	1683
valid_sources[0x6f]	586113	1			T2	26		T3	19		T4	1788
valid_sources[0x70]	588683	1			T2	40		T3	7		T4	1688
valid_sources[0x71]	531024	1			T2	38		T3	6		T4	1644
valid_sources[0x72]	547983	1			T2	41		T3	8		T4	1657
valid_sources[0x73]	542832	1			T2	33		T3	11		T4	1703
valid_sources[0x74]	1990644	1			T2	28		T3	9		T4	1820
valid_sources[0x75]	690936	1			T2	23		T3	13		T4	1644
valid_sources[0x76]	534114	1			T2	26		T3	4		T4	1686
valid_sources[0x77]	1337736	1			T2	35		T3	6		T4	1671
valid_sources[0x78]	588902	1			T2	37		T3	11		T4	1632
valid_sources[0x79]	615118	1			T2	30		T3	7		T4	1651
valid_sources[0x7a]	529793	1			T2	39		T3	14		T4	1558
valid_sources[0x7b]	590706	1			T2	25		T3	15		T4	1674
valid_sources[0x7c]	556376	1			T2	26		T3	9		T4	1645
valid_sources[0x7d]	559683	1			T2	24		T3	7		T4	1651
valid_sources[0x7e]	2213330	1			T2	36		T3	8		T4	1623
valid_sources[0x7f]	579884	1			T2	38		T3	16		T4	1716
valid_sources[0x80]	544790	1			T2	26		T3	12		T4	1605

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

72274166

1

T1

4481

T2

3607

T3

1167

values[0x0]

all_enables

biggest_size

37513123

1

T1

2225

T2

1790

T3

592

values[0x1]

all_enables

biggest_size

37523270

1

T1

2326

T2

1779

T3

589

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	44845	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

162843

1

T1

1

T3

19

T4

79

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	56046	1			T3	26		T4	55		T5	15
values[0x0]	73212	1			T1	1		T2	1		T3	9
values[0x1]	78430	1			T1	1		T2	1		T3	16

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34622	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

173066

1

T1

2

T3

21

T4

98

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1011	1			T4	2		T16	12		T23	8
valid_sources[0x01]	1135	1			T44	1		T16	16		T23	3
valid_sources[0x02]	728	1			T3	14		T5	1		T16	13
valid_sources[0x03]	865	1			T16	24		T23	5		T19	2
valid_sources[0x04]	668	1			T16	9		T23	4		T125	1
valid_sources[0x05]	830	1			T5	1		T16	9		T23	4
valid_sources[0x06]	838	1			T4	2		T16	15		T23	6
valid_sources[0x07]	739	1			T16	23		T23	3		T22	1
valid_sources[0x08]	814	1			T4	6		T16	23		T23	11
valid_sources[0x09]	870	1			T16	15		T23	5		T118	2
valid_sources[0x0a]	1020	1			T5	1		T16	7		T23	1
valid_sources[0x0b]	848	1			T4	1		T16	20		T23	1
valid_sources[0x0c]	912	1			T4	1		T16	17		T23	4
valid_sources[0x0d]	782	1			T16	12		T23	2		T21	1
valid_sources[0x0e]	832	1			T5	1		T16	20		T23	7
valid_sources[0x0f]	821	1			T16	17		T23	5		T21	1
valid_sources[0x10]	790	1			T5	3		T16	10		T23	3
valid_sources[0x11]	1072	1			T4	1		T16	18		T23	12
valid_sources[0x12]	696	1			T16	21		T33	2		T126	1
valid_sources[0x13]	798	1			T5	1		T16	19		T23	3
valid_sources[0x14]	905	1			T16	12		T23	5		T14	3
valid_sources[0x15]	1105	1			T5	1		T16	7		T23	4
valid_sources[0x16]	689	1			T16	12		T23	4		T22	2
valid_sources[0x17]	1312	1			T5	2		T16	14		T23	2
valid_sources[0x18]	624	1			T4	5		T9	1		T16	17
valid_sources[0x19]	856	1			T4	2		T5	2		T6	2
valid_sources[0x1a]	598	1			T4	4		T16	12		T23	6
valid_sources[0x1b]	1089	1			T16	16		T23	5		T21	1
valid_sources[0x1c]	825	1			T4	2		T5	1		T16	13
valid_sources[0x1d]	920	1			T16	17		T23	3		T24	1
valid_sources[0x1e]	692	1			T16	7		T23	2		T21	2
valid_sources[0x1f]	731	1			T4	1		T16	16		T23	2
valid_sources[0x20]	672	1			T9	1		T5	1		T16	20
valid_sources[0x21]	837	1			T5	1		T16	16		T23	2
valid_sources[0x22]	663	1			T16	16		T23	2		T124	1
valid_sources[0x23]	767	1			T4	1		T16	14		T23	11
valid_sources[0x24]	707	1			T16	26		T23	7		T124	1
valid_sources[0x25]	623	1			T4	3		T16	13		T23	1
valid_sources[0x26]	784	1			T4	8		T16	15		T23	4
valid_sources[0x27]	601	1			T4	2		T16	12		T23	7
valid_sources[0x28]	1090	1			T4	1		T5	1		T16	14
valid_sources[0x29]	578	1			T16	11		T23	4		T58	1
valid_sources[0x2a]	640	1			T16	18		T23	7		T72	1
valid_sources[0x2b]	1143	1			T16	14		T23	3		T22	1
valid_sources[0x2c]	769	1			T16	11		T23	6		T24	14
valid_sources[0x2d]	713	1			T4	2		T16	25		T23	8
valid_sources[0x2e]	986	1			T2	1		T5	1		T16	13
valid_sources[0x2f]	737	1			T16	13		T23	3		T21	1
valid_sources[0x30]	1091	1			T16	15		T23	4		T24	9
valid_sources[0x31]	625	1			T16	10		T23	3		T14	1
valid_sources[0x32]	853	1			T16	8		T23	5		T22	2
valid_sources[0x33]	759	1			T16	21		T23	2		T22	3
valid_sources[0x34]	1037	1			T5	1		T16	15		T23	3
valid_sources[0x35]	708	1			T3	1		T5	1		T16	6
valid_sources[0x36]	744	1			T4	1		T9	2		T16	20
valid_sources[0x37]	805	1			T5	1		T16	23		T23	4
valid_sources[0x38]	920	1			T4	5		T5	3		T16	17
valid_sources[0x39]	730	1			T16	12		T23	7		T24	4
valid_sources[0x3a]	600	1			T3	5		T16	11		T23	5
valid_sources[0x3b]	809	1			T16	15		T23	3		T124	1
valid_sources[0x3c]	886	1			T10	4		T16	13		T23	5
valid_sources[0x3d]	905	1			T4	2		T16	17		T23	3
valid_sources[0x3e]	872	1			T16	17		T23	3		T21	3
valid_sources[0x3f]	773	1			T26	1		T16	6		T23	10
valid_sources[0x40]	940	1			T16	13		T23	8		T21	1
valid_sources[0x41]	684	1			T16	18		T23	8		T124	1
valid_sources[0x42]	754	1			T16	5		T23	6		T24	7
valid_sources[0x43]	677	1			T3	4		T16	10		T23	3
valid_sources[0x44]	749	1			T16	17		T23	4		T21	1
valid_sources[0x45]	751	1			T16	28		T23	1		T39	2
valid_sources[0x46]	613	1			T15	3		T16	12		T23	3
valid_sources[0x47]	1041	1			T4	1		T16	18		T23	1
valid_sources[0x48]	1147	1			T16	22		T23	4		T21	1
valid_sources[0x49]	750	1			T5	1		T16	16		T23	6
valid_sources[0x4a]	882	1			T16	32		T23	8		T126	2
valid_sources[0x4b]	786	1			T4	12		T16	21		T23	2
valid_sources[0x4c]	669	1			T5	2		T44	1		T16	11
valid_sources[0x4d]	806	1			T16	17		T23	5		T118	1
valid_sources[0x4e]	1048	1			T16	16		T23	1		T21	1
valid_sources[0x4f]	621	1			T4	2		T5	1		T16	17
valid_sources[0x50]	1180	1			T16	13		T23	2		T126	1
valid_sources[0x51]	760	1			T4	2		T16	10		T23	6
valid_sources[0x52]	1607	1			T4	4		T44	1		T16	13
valid_sources[0x53]	887	1			T16	12		T23	5		T118	2
valid_sources[0x54]	797	1			T4	2		T44	1		T16	15
valid_sources[0x55]	739	1			T6	2		T16	14		T23	13
valid_sources[0x56]	662	1			T4	2		T6	5		T16	20
valid_sources[0x57]	695	1			T16	25		T23	1		T118	3
valid_sources[0x58]	731	1			T16	8		T23	7		T118	1
valid_sources[0x59]	908	1			T16	22		T23	2		T126	1
valid_sources[0x5a]	759	1			T4	6		T16	9		T23	8
valid_sources[0x5b]	637	1			T16	8		T23	6		T21	2
valid_sources[0x5c]	662	1			T4	8		T16	19		T23	7
valid_sources[0x5d]	738	1			T27	1		T16	9		T23	4
valid_sources[0x5e]	793	1			T16	16		T23	5		T24	4
valid_sources[0x5f]	982	1			T5	1		T16	8		T23	6
valid_sources[0x60]	812	1			T4	2		T16	7		T23	9
valid_sources[0x61]	626	1			T16	17		T23	6		T118	2
valid_sources[0x62]	679	1			T5	1		T16	15		T23	2
valid_sources[0x63]	824	1			T16	13		T23	5		T14	6
valid_sources[0x64]	947	1			T16	15		T23	1		T34	5
valid_sources[0x65]	728	1			T5	1		T16	23		T23	4
valid_sources[0x66]	703	1			T5	1		T16	16		T23	3
valid_sources[0x67]	636	1			T8	1		T16	14		T23	4
valid_sources[0x68]	780	1			T16	15		T23	6		T22	1
valid_sources[0x69]	891	1			T16	15		T23	5		T21	1
valid_sources[0x6a]	665	1			T16	17		T23	3		T24	4
valid_sources[0x6b]	899	1			T3	3		T5	1		T16	9
valid_sources[0x6c]	796	1			T4	2		T16	12		T23	7
valid_sources[0x6d]	689	1			T16	14		T23	4		T19	3
valid_sources[0x6e]	852	1			T3	2		T16	10		T23	1
valid_sources[0x6f]	1189	1			T16	15		T23	6		T21	1
valid_sources[0x70]	750	1			T4	1		T5	1		T16	14
valid_sources[0x71]	935	1			T16	12		T23	2		T14	3
valid_sources[0x72]	744	1			T5	1		T16	17		T23	6
valid_sources[0x73]	657	1			T5	1		T16	16		T23	6
valid_sources[0x74]	842	1			T16	12		T23	4		T124	1
valid_sources[0x75]	605	1			T16	19		T23	3		T14	1
valid_sources[0x76]	865	1			T5	1		T44	1		T45	1
valid_sources[0x77]	836	1			T16	17		T23	3		T21	1
valid_sources[0x78]	822	1			T4	4		T16	9		T23	7
valid_sources[0x79]	786	1			T16	8		T23	5		T24	5
valid_sources[0x7a]	697	1			T4	1		T16	8		T23	7
valid_sources[0x7b]	893	1			T7	2		T16	25		T23	2
valid_sources[0x7c]	1058	1			T4	2		T16	11		T23	4
valid_sources[0x7d]	780	1			T16	10		T23	3		T34	3
valid_sources[0x7e]	827	1			T16	16		T23	6		T21	1
valid_sources[0x7f]	635	1			T4	1		T6	3		T16	13
valid_sources[0x80]	912	1			T4	3		T16	18		T23	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

43442

1

T3

13

T4

31

T5

10

values[0x0]

all_enables

biggest_size

61173

1

T1

1

T3

5

T4

32

values[0x1]

all_enables

biggest_size

58228

1

T3

1

T4

16

T9

1