Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16419634

1

T1

882

T2

736

T3

24

full_word

144012424

1

T1

9032

T2

7176

T3

196

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	160431788	1			T1	9914		T2	7912		T3	220
auto[TlIntgErrCmd]	100	1			T52	3		T53	5		T54	8
auto[TlIntgErrData]	84	1			T52	4		T53	4		T54	8
auto[TlIntgErrBoth]	86	1			T52	3		T53	1		T54	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

77085596

1

T1

4913

T2

3955

T3

100

auto[1]

83346462

1

T1

5001

T2

3957

T3

120

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	8033164	1			T1	432		T2	348		T3	13
auto[TlIntgErrNone]	partial	auto[1]	8386223	1			T1	450		T2	388		T3	11
auto[TlIntgErrNone]	full_word	auto[0]	69052307	1			T1	4481		T2	3607		T3	87
auto[TlIntgErrNone]	full_word	auto[1]	74960094	1			T1	4551		T2	3569		T3	109
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T53	2		T54	4		T112	1
auto[TlIntgErrCmd]	partial	auto[1]	55	1			T52	3		T53	2		T54	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T113	1		T115	1		T116	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T53	1		T113	1		T111	1
auto[TlIntgErrData]	partial	auto[0]	41	1			T52	3		T53	1		T54	4
auto[TlIntgErrData]	partial	auto[1]	37	1			T52	1		T53	2		T54	2
auto[TlIntgErrData]	full_word	auto[0]	2	1			T54	1		T116	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	4	1			T53	1		T54	1		T117	1
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T52	1		T54	2		T113	3
auto[TlIntgErrBoth]	partial	auto[1]	39	1			T52	2		T53	1		T54	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T54	1		T113	2		T110	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T112	1		T113	1		T109	1