Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	873190	1			T28	5259		T21	12570		T33	1970
auto[1]	10937072	1			T2	3880		T3	5		T4	3201
auto[2]	679092	1			T28	3248		T21	8161		T33	1129
auto[3]	10639684	1			T2	3882		T3	4		T4	3112

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14686216	1			T2	6431		T3	6		T4	4441
auto[1]	2180284	1			T2	654		T3	3		T4	905
auto[2]	2186326	1			T2	628		T4	836		T7	983
auto[3]	4076212	1			T2	49		T4	131		T7	207

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9559534

1

T2

7762

T3

9

T4

6313

auto[1]

13569504

1

T10

137989

T25

1

T44

79386

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	321971	1			T28	4351		T21	10337		T33	1653
auto[0]	auto[0]	auto[1]	33427	1			T28	424		T21	1061		T33	157
auto[0]	auto[0]	auto[2]	33234	1			T28	430		T21	1060		T33	137
auto[0]	auto[0]	auto[3]	64138	1			T28	54		T21	112		T33	22
auto[0]	auto[1]	auto[0]	3483001	1			T2	3241		T3	3		T4	2236
auto[0]	auto[1]	auto[1]	367941	1			T2	298		T3	2		T4	685
auto[0]	auto[1]	auto[2]	366474	1			T2	318		T4	208		T7	487
auto[0]	auto[1]	auto[3]	287452	1			T2	23		T4	72		T7	117
auto[0]	auto[2]	auto[0]	232342	1			T28	2685		T21	6378		T33	965
auto[0]	auto[2]	auto[1]	28535	1			T28	279		T21	632		T33	80
auto[0]	auto[2]	auto[2]	23810	1			T28	255		T21	1064		T33	77
auto[0]	auto[2]	auto[3]	45272	1			T28	29		T21	87		T33	7
auto[0]	auto[3]	auto[0]	3300645	1			T2	3190		T3	3		T4	2205
auto[0]	auto[3]	auto[1]	348110	1			T2	356		T3	1		T4	220
auto[0]	auto[3]	auto[2]	365670	1			T2	310		T4	628		T7	496
auto[0]	auto[3]	auto[3]	257512	1			T2	26		T4	59		T7	90
auto[1]	auto[0]	auto[0]	13679	1			T33	1		T94	627		T97	539
auto[1]	auto[0]	auto[1]	62216	1			T94	2643		T97	2531		T122	3116
auto[1]	auto[0]	auto[2]	62197	1			T94	2574		T97	2533		T122	3039
auto[1]	auto[0]	auto[3]	282328	1			T94	12257		T97	11056		T73	5
auto[1]	auto[1]	auto[0]	3661546	1			T10	57053		T25	1		T44	33113
auto[1]	auto[1]	auto[1]	666499	1			T10	5744		T44	2993		T45	11543
auto[1]	auto[1]	auto[2]	626236	1			T10	5838		T44	3233		T45	12845
auto[1]	auto[1]	auto[3]	1477923	1			T10	579		T44	285		T45	52042
auto[1]	auto[2]	auto[0]	12246	1			T94	536		T97	332		T123	1
auto[1]	auto[2]	auto[1]	55120	1			T94	2550		T97	1489		T122	2936
auto[1]	auto[2]	auto[2]	51201	1			T94	1778		T97	2308		T122	2134
auto[1]	auto[2]	auto[3]	230566	1			T94	8297		T97	10702		T122	9392
auto[1]	auto[3]	auto[0]	3660786	1			T10	56728		T44	33234		T45	2863
auto[1]	auto[3]	auto[1]	618436	1			T10	5758		T44	3278		T45	12970
auto[1]	auto[3]	auto[2]	657504	1			T10	5741		T44	2952		T45	11550
auto[1]	auto[3]	auto[3]	1431021	1			T10	548		T44	298		T45	52136