Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
85.78	100.00	81.82	100.00		100.00	47.06	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1077884192	237048	0	0
ctrl_regwen_rd_A	1077884192	4488	0	0
exec_rd_A	1077884192	4263	0	0
exec_regwen_rd_A	1077884192	4774	0	0
readback_rd_A	1077884192	3157	0	0
readback_regwen_rd_A	1077884192	3054	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1077884192	237048	0	0
T14	546451	0	0	0
T16	156505	5474	0	0
T17	260647	0	0	0
T21	551781	0	0	0
T22	704446	0	0	0
T23	16069	1046	0	0
T24	0	2304	0	0
T28	233683	0	0	0
T35	0	4633	0	0
T48	0	7636	0	0
T50	0	7677	0	0
T51	0	7620	0	0
T57	146177	0	0	0
T58	0	4446	0	0
T59	0	3452	0	0
T60	0	7503	0	0
T61	34526	0	0	0
T62	68466	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1077884192	4488	0	0
T14	546451	0	0	0
T16	156505	434	0	0
T17	260647	0	0	0
T21	551781	0	0	0
T22	704446	0	0	0
T23	16069	0	0	0
T28	233683	0	0	0
T37	0	287	0	0
T57	146177	0	0	0
T61	34526	0	0	0
T62	68466	0	0	0
T98	0	90	0	0
T99	0	106	0	0
T100	0	226	0	0
T101	0	232	0	0
T102	0	329	0	0
T103	0	87	0	0
T104	0	42	0	0
T105	0	396	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1077884192	4263	0	0
T14	546451	0	0	0
T16	156505	377	0	0
T17	260647	0	0	0
T21	551781	0	0	0
T22	704446	0	0	0
T23	16069	0	0	0
T28	233683	0	0	0
T37	0	249	0	0
T57	146177	0	0	0
T61	34526	0	0	0
T62	68466	0	0	0
T98	0	136	0	0
T99	0	84	0	0
T100	0	136	0	0
T101	0	226	0	0
T102	0	274	0	0
T103	0	102	0	0
T104	0	70	0	0
T105	0	360	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1077884192	4774	0	0
T14	546451	0	0	0
T16	156505	381	0	0
T17	260647	0	0	0
T21	551781	0	0	0
T22	704446	0	0	0
T23	16069	0	0	0
T28	233683	0	0	0
T37	0	453	0	0
T57	146177	0	0	0
T61	34526	0	0	0
T62	68466	0	0	0
T98	0	145	0	0
T99	0	125	0	0
T100	0	210	0	0
T101	0	228	0	0
T102	0	356	0	0
T103	0	94	0	0
T104	0	93	0	0
T105	0	347	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1077884192	3157	0	0
T14	546451	0	0	0
T16	156505	384	0	0
T17	260647	0	0	0
T21	551781	0	0	0
T22	704446	0	0	0
T23	16069	0	0	0
T28	233683	0	0	0
T37	0	322	0	0
T57	146177	0	0	0
T61	34526	0	0	0
T62	68466	0	0	0
T98	0	80	0	0
T99	0	68	0	0
T100	0	118	0	0
T101	0	211	0	0
T102	0	350	0	0
T103	0	81	0	0
T104	0	44	0	0
T105	0	325	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1077884192	3054	0	0
T14	546451	0	0	0
T16	156505	358	0	0
T17	260647	0	0	0
T21	551781	0	0	0
T22	704446	0	0	0
T23	16069	0	0	0
T28	233683	0	0	0
T37	0	220	0	0
T57	146177	0	0	0
T61	34526	0	0	0
T62	68466	0	0	0
T98	0	115	0	0
T99	0	87	0	0
T100	0	97	0	0
T101	0	197	0	0
T102	0	348	0	0
T103	0	52	0	0
T104	0	27	0	0
T105	0	343	0	0