Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16123301	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

144385049

1

T1

196606

T2

228290

T4

4343

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	78846612	1			T1	65536		T2	125500		T4	2420
values[0x0]	39225363	1			T1	65212		T2	60218		T4	1157
values[0x1]	42436375	1			T1	65858		T2	65152		T4	1226

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8203067	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

152305283

1

T1

196606

T2

239570

T4

4579

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	588160	1			T1	806		T2	973		T4	33
valid_sources[0x01]	608115	1			T1	901		T2	1042		T4	16
valid_sources[0x02]	599243	1			T1	863		T2	982		T4	23
valid_sources[0x03]	1519226	1			T1	814		T2	992		T4	2
valid_sources[0x04]	526012	1			T1	753		T2	980		T4	32
valid_sources[0x05]	566885	1			T1	711		T2	990		T4	8
valid_sources[0x06]	524435	1			T1	483		T2	1014		T4	17
valid_sources[0x07]	607063	1			T1	464		T2	1040		T4	18
valid_sources[0x08]	550363	1			T1	759		T2	990		T4	10
valid_sources[0x09]	994049	1			T1	512		T2	1006		T4	19
valid_sources[0x0a]	621443	1			T1	887		T2	977		T4	35
valid_sources[0x0b]	591968	1			T1	936		T2	1061		T4	40
valid_sources[0x0c]	581085	1			T1	551		T2	1040		T4	22
valid_sources[0x0d]	514437	1			T1	652		T2	1019		T4	22
valid_sources[0x0e]	579737	1			T1	756		T2	958		T4	16
valid_sources[0x0f]	539684	1			T1	481		T2	936		T4	19
valid_sources[0x10]	529797	1			T1	969		T2	992		T4	5
valid_sources[0x11]	529255	1			T1	641		T2	972		T4	14
valid_sources[0x12]	518094	1			T1	472		T2	908		T4	29
valid_sources[0x13]	557629	1			T1	592		T2	990		T4	36
valid_sources[0x14]	526426	1			T1	546		T2	981		T4	31
valid_sources[0x15]	537762	1			T1	762		T2	977		T4	18
valid_sources[0x16]	541111	1			T1	712		T2	990		T4	30
valid_sources[0x17]	532787	1			T1	752		T2	988		T4	24
valid_sources[0x18]	520768	1			T1	776		T2	944		T4	24
valid_sources[0x19]	515007	1			T1	759		T2	939		T4	19
valid_sources[0x1a]	529158	1			T1	881		T2	1028		T4	31
valid_sources[0x1b]	563582	1			T1	478		T2	979		T4	7
valid_sources[0x1c]	534848	1			T1	956		T2	965		T4	18
valid_sources[0x1d]	536692	1			T1	1087		T2	946		T4	4
valid_sources[0x1e]	648421	1			T1	422		T2	987		T4	13
valid_sources[0x1f]	545295	1			T1	836		T2	973		T4	9
valid_sources[0x20]	547478	1			T1	866		T2	958		T4	14
valid_sources[0x21]	540237	1			T1	954		T2	995		T4	24
valid_sources[0x22]	528098	1			T1	759		T2	955		T4	14
valid_sources[0x23]	540283	1			T1	582		T2	990		T4	33
valid_sources[0x24]	553601	1			T1	817		T2	970		T4	10
valid_sources[0x25]	537753	1			T1	847		T2	1024		T4	9
valid_sources[0x26]	524121	1			T1	819		T2	924		T4	21
valid_sources[0x27]	599640	1			T1	1002		T2	966		T4	19
valid_sources[0x28]	560245	1			T1	801		T2	943		T4	22
valid_sources[0x29]	521292	1			T1	729		T2	976		T4	24
valid_sources[0x2a]	565103	1			T1	1047		T2	937		T4	16
valid_sources[0x2b]	546103	1			T1	751		T2	979		T4	31
valid_sources[0x2c]	551909	1			T1	482		T2	937		T4	11
valid_sources[0x2d]	526767	1			T1	835		T2	981		T4	29
valid_sources[0x2e]	587559	1			T1	674		T2	978		T4	6
valid_sources[0x2f]	541014	1			T1	620		T2	1012		T4	10
valid_sources[0x30]	575218	1			T1	867		T2	955		T4	19
valid_sources[0x31]	557506	1			T1	962		T2	973		T4	29
valid_sources[0x32]	540295	1			T1	781		T2	978		T4	30
valid_sources[0x33]	509639	1			T1	1013		T2	993		T4	15
valid_sources[0x34]	639363	1			T1	1088		T2	983		T4	9
valid_sources[0x35]	543376	1			T1	1067		T2	970		T4	37
valid_sources[0x36]	523326	1			T1	707		T2	1068		T4	3
valid_sources[0x37]	660908	1			T1	596		T2	969		T4	29
valid_sources[0x38]	538472	1			T1	976		T2	994		T4	18
valid_sources[0x39]	538254	1			T1	919		T2	950		T4	30
valid_sources[0x3a]	516629	1			T1	501		T2	938		T4	12
valid_sources[0x3b]	515344	1			T1	1100		T2	969		T4	18
valid_sources[0x3c]	539505	1			T1	823		T2	981		T4	21
valid_sources[0x3d]	507202	1			T1	647		T2	1020		T4	24
valid_sources[0x3e]	1202454	1			T1	627		T2	978		T4	37
valid_sources[0x3f]	524161	1			T1	624		T2	974		T4	17
valid_sources[0x40]	588802	1			T1	702		T2	1004		T4	17
valid_sources[0x41]	632791	1			T1	734		T2	1033		T4	38
valid_sources[0x42]	557764	1			T1	696		T2	1002		T4	12
valid_sources[0x43]	531114	1			T1	910		T2	944		T4	25
valid_sources[0x44]	546389	1			T1	725		T2	958		T4	27
valid_sources[0x45]	546258	1			T1	741		T2	993		T4	21
valid_sources[0x46]	524950	1			T1	1086		T2	918		T4	15
valid_sources[0x47]	1655868	1			T1	788		T2	998		T4	19
valid_sources[0x48]	512946	1			T1	762		T2	1021		T4	22
valid_sources[0x49]	572171	1			T1	898		T2	975		T4	18
valid_sources[0x4a]	538239	1			T1	623		T2	1031		T4	12
valid_sources[0x4b]	607561	1			T1	786		T2	1027		T4	10
valid_sources[0x4c]	513754	1			T1	1215		T2	991		T4	22
valid_sources[0x4d]	1198764	1			T1	811		T2	947		T4	21
valid_sources[0x4e]	518152	1			T1	505		T2	978		T4	18
valid_sources[0x4f]	529983	1			T1	757		T2	1008		T4	33
valid_sources[0x50]	536959	1			T1	636		T2	994		T4	20
valid_sources[0x51]	536818	1			T1	688		T2	981		T4	15
valid_sources[0x52]	507625	1			T1	556		T2	1029		T4	21
valid_sources[0x53]	586353	1			T1	731		T2	982		T4	10
valid_sources[0x54]	528446	1			T1	936		T2	934		T4	7
valid_sources[0x55]	568163	1			T1	532		T2	968		T4	8
valid_sources[0x56]	537067	1			T1	820		T2	1036		T4	13
valid_sources[0x57]	533214	1			T1	999		T2	989		T4	24
valid_sources[0x58]	600074	1			T1	821		T2	978		T4	26
valid_sources[0x59]	532525	1			T1	439		T2	980		T4	6
valid_sources[0x5a]	561476	1			T1	845		T2	951		T4	28
valid_sources[0x5b]	1700655	1			T1	803		T2	990		T4	12
valid_sources[0x5c]	566746	1			T1	676		T2	937		T4	13
valid_sources[0x5d]	521139	1			T1	982		T2	971		T4	34
valid_sources[0x5e]	563793	1			T1	718		T2	996		T4	16
valid_sources[0x5f]	524809	1			T1	770		T2	995		T4	22
valid_sources[0x60]	532534	1			T1	466		T2	941		T4	35
valid_sources[0x61]	523736	1			T1	773		T2	996		T4	16
valid_sources[0x62]	585013	1			T1	685		T2	1036		T4	21
valid_sources[0x63]	557169	1			T1	934		T2	988		T4	28
valid_sources[0x64]	542086	1			T1	589		T2	1007		T4	10
valid_sources[0x65]	554678	1			T1	769		T2	969		T4	31
valid_sources[0x66]	547379	1			T1	840		T2	987		T4	28
valid_sources[0x67]	618867	1			T1	802		T2	1001		T4	24
valid_sources[0x68]	579836	1			T1	477		T2	994		T4	15
valid_sources[0x69]	527571	1			T1	796		T2	920		T4	23
valid_sources[0x6a]	566517	1			T1	736		T2	1004		T4	21
valid_sources[0x6b]	531153	1			T1	835		T2	930		T4	35
valid_sources[0x6c]	1520257	1			T1	651		T2	1013		T4	14
valid_sources[0x6d]	528008	1			T1	865		T2	985		T4	14
valid_sources[0x6e]	510932	1			T1	762		T2	967		T4	19
valid_sources[0x6f]	528060	1			T1	680		T2	988		T4	30
valid_sources[0x70]	546044	1			T1	733		T2	993		T4	23
valid_sources[0x71]	2168320	1			T1	1079		T2	991		T4	28
valid_sources[0x72]	566155	1			T1	765		T2	955		T4	11
valid_sources[0x73]	564545	1			T1	661		T2	1048		T4	34
valid_sources[0x74]	542478	1			T1	1002		T2	971		T4	17
valid_sources[0x75]	605612	1			T1	780		T2	959		T4	5
valid_sources[0x76]	551636	1			T1	665		T2	1006		T4	19
valid_sources[0x77]	540933	1			T1	479		T2	1023		T4	12
valid_sources[0x78]	551655	1			T1	976		T2	938		T4	26
valid_sources[0x79]	570119	1			T1	767		T2	1009		T4	12
valid_sources[0x7a]	528525	1			T1	990		T2	959		T4	41
valid_sources[0x7b]	512478	1			T1	507		T2	964		T4	4
valid_sources[0x7c]	529586	1			T1	482		T2	961		T4	9
valid_sources[0x7d]	541233	1			T1	605		T2	973		T4	9
valid_sources[0x7e]	557084	1			T1	674		T2	980		T4	13
valid_sources[0x7f]	537488	1			T1	741		T2	955		T4	18
valid_sources[0x80]	566456	1			T1	734		T2	962		T4	27

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

70741796

1

T1

65536

T2

114193

T4

2178

values[0x0]

all_enables

biggest_size

36817798

1

T1

65212

T2

56854

T4

1092

values[0x1]

all_enables

biggest_size

36825455

1

T1

65858

T2

57243

T4

1073

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	48742	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

168887

1

T1

108

T2

1

T3

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	59362	1			T4	44		T23	17		T18	26
values[0x0]	76259	1			T1	216		T2	2		T3	7
values[0x1]	82008	1			T1	207		T2	4		T3	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	37691	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

179938

1

T1

139

T2

1

T3

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	802	1			T1	2		T18	1		T22	10
valid_sources[0x01]	1029	1			T1	1		T22	6		T26	31
valid_sources[0x02]	870	1			T1	1		T42	13		T22	8
valid_sources[0x03]	913	1			T1	5		T18	1		T22	8
valid_sources[0x04]	984	1			T4	1		T18	5		T22	12
valid_sources[0x05]	1062	1			T1	2		T22	9		T26	23
valid_sources[0x06]	1265	1			T1	1		T4	2		T42	1
valid_sources[0x07]	646	1			T18	2		T22	9		T26	20
valid_sources[0x08]	690	1			T3	1		T18	1		T22	7
valid_sources[0x09]	820	1			T9	1		T18	3		T22	11
valid_sources[0x0a]	1152	1			T1	3		T12	4		T22	8
valid_sources[0x0b]	721	1			T1	1		T18	1		T22	4
valid_sources[0x0c]	812	1			T1	2		T22	9		T26	31
valid_sources[0x0d]	850	1			T1	4		T22	13		T26	15
valid_sources[0x0e]	801	1			T1	3		T4	1		T23	1
valid_sources[0x0f]	707	1			T1	4		T4	1		T22	8
valid_sources[0x10]	978	1			T1	2		T22	5		T26	17
valid_sources[0x11]	652	1			T1	1		T22	9		T26	19
valid_sources[0x12]	686	1			T1	3		T18	2		T22	7
valid_sources[0x13]	698	1			T1	4		T3	1		T22	9
valid_sources[0x14]	1292	1			T22	8		T26	31		T27	6
valid_sources[0x15]	854	1			T1	6		T18	3		T22	7
valid_sources[0x16]	710	1			T1	2		T18	1		T22	13
valid_sources[0x17]	988	1			T1	4		T3	1		T23	1
valid_sources[0x18]	826	1			T1	3		T22	14		T26	32
valid_sources[0x19]	698	1			T1	1		T42	12		T22	7
valid_sources[0x1a]	715	1			T1	2		T22	8		T26	21
valid_sources[0x1b]	775	1			T1	3		T22	13		T26	24
valid_sources[0x1c]	687	1			T1	1		T42	8		T18	1
valid_sources[0x1d]	796	1			T1	2		T23	1		T18	2
valid_sources[0x1e]	847	1			T1	4		T3	1		T4	1
valid_sources[0x1f]	800	1			T1	1		T4	1		T22	8
valid_sources[0x20]	657	1			T1	3		T23	1		T42	3
valid_sources[0x21]	1301	1			T1	3		T18	4		T22	5
valid_sources[0x22]	851	1			T1	1		T4	3		T22	7
valid_sources[0x23]	1273	1			T1	2		T23	2		T22	7
valid_sources[0x24]	721	1			T1	2		T18	1		T22	15
valid_sources[0x25]	738	1			T1	1		T42	4		T18	1
valid_sources[0x26]	972	1			T1	3		T23	1		T42	7
valid_sources[0x27]	621	1			T1	5		T3	1		T23	1
valid_sources[0x28]	1004	1			T23	1		T22	11		T26	14
valid_sources[0x29]	932	1			T22	12		T26	21		T48	5
valid_sources[0x2a]	686	1			T1	2		T23	1		T18	3
valid_sources[0x2b]	747	1			T23	2		T18	2		T22	11
valid_sources[0x2c]	883	1			T1	5		T18	1		T22	5
valid_sources[0x2d]	671	1			T1	3		T24	3		T18	5
valid_sources[0x2e]	698	1			T23	1		T22	8		T26	32
valid_sources[0x2f]	1005	1			T1	1		T4	2		T22	7
valid_sources[0x30]	904	1			T3	1		T22	5		T26	40
valid_sources[0x31]	1132	1			T1	2		T23	1		T42	3
valid_sources[0x32]	927	1			T1	1		T9	1		T22	13
valid_sources[0x33]	694	1			T1	1		T3	1		T22	6
valid_sources[0x34]	806	1			T1	2		T42	7		T18	2
valid_sources[0x35]	745	1			T23	1		T42	5		T18	1
valid_sources[0x36]	668	1			T2	3		T22	8		T26	29
valid_sources[0x37]	646	1			T4	1		T23	1		T22	12
valid_sources[0x38]	591	1			T22	12		T26	27		T55	1
valid_sources[0x39]	875	1			T10	1		T42	14		T22	9
valid_sources[0x3a]	677	1			T1	1		T22	11		T26	25
valid_sources[0x3b]	786	1			T1	2		T3	1		T17	1
valid_sources[0x3c]	793	1			T1	3		T17	1		T22	8
valid_sources[0x3d]	883	1			T1	2		T13	10		T22	12
valid_sources[0x3e]	567	1			T1	3		T22	7		T26	18
valid_sources[0x3f]	684	1			T1	1		T22	12		T26	31
valid_sources[0x40]	808	1			T1	2		T4	1		T22	14
valid_sources[0x41]	905	1			T1	1		T17	4		T22	7
valid_sources[0x42]	729	1			T1	3		T4	1		T23	1
valid_sources[0x43]	738	1			T1	2		T22	10		T26	20
valid_sources[0x44]	712	1			T1	4		T4	1		T42	4
valid_sources[0x45]	862	1			T22	7		T26	26		T27	9
valid_sources[0x46]	1537	1			T1	1		T18	2		T22	14
valid_sources[0x47]	758	1			T1	3		T4	2		T22	8
valid_sources[0x48]	1165	1			T1	4		T12	1		T18	1
valid_sources[0x49]	898	1			T4	1		T23	1		T22	15
valid_sources[0x4a]	870	1			T1	3		T4	1		T18	2
valid_sources[0x4b]	615	1			T24	1		T18	4		T22	14
valid_sources[0x4c]	936	1			T1	1		T4	2		T23	2
valid_sources[0x4d]	1625	1			T1	2		T2	3		T23	1
valid_sources[0x4e]	737	1			T18	1		T22	11		T26	20
valid_sources[0x4f]	761	1			T1	1		T3	1		T42	5
valid_sources[0x50]	975	1			T1	1		T22	7		T26	15
valid_sources[0x51]	709	1			T1	1		T4	1		T22	7
valid_sources[0x52]	945	1			T1	1		T22	5		T26	25
valid_sources[0x53]	813	1			T23	1		T18	2		T22	6
valid_sources[0x54]	760	1			T1	4		T4	1		T42	4
valid_sources[0x55]	728	1			T1	1		T22	8		T26	25
valid_sources[0x56]	1166	1			T1	2		T23	2		T22	17
valid_sources[0x57]	656	1			T1	2		T4	1		T22	17
valid_sources[0x58]	633	1			T1	4		T23	2		T18	2
valid_sources[0x59]	707	1			T23	1		T18	2		T22	11
valid_sources[0x5a]	721	1			T1	2		T42	2		T18	2
valid_sources[0x5b]	830	1			T1	2		T9	1		T18	2
valid_sources[0x5c]	662	1			T1	2		T23	1		T18	2
valid_sources[0x5d]	708	1			T42	3		T18	2		T22	7
valid_sources[0x5e]	765	1			T1	1		T42	12		T18	2
valid_sources[0x5f]	798	1			T1	1		T18	7		T22	7
valid_sources[0x60]	893	1			T1	1		T4	1		T22	8
valid_sources[0x61]	851	1			T1	1		T18	4		T22	9
valid_sources[0x62]	868	1			T1	1		T23	1		T22	15
valid_sources[0x63]	678	1			T1	2		T4	1		T23	1
valid_sources[0x64]	851	1			T4	1		T22	10		T26	28
valid_sources[0x65]	746	1			T1	4		T23	1		T18	5
valid_sources[0x66]	962	1			T18	1		T22	13		T26	18
valid_sources[0x67]	855	1			T1	1		T42	18		T22	9
valid_sources[0x68]	681	1			T1	2		T22	8		T26	25
valid_sources[0x69]	685	1			T1	1		T22	12		T26	24
valid_sources[0x6a]	630	1			T3	1		T23	1		T22	6
valid_sources[0x6b]	845	1			T1	1		T18	1		T22	10
valid_sources[0x6c]	1082	1			T1	2		T23	1		T42	3
valid_sources[0x6d]	747	1			T4	1		T22	12		T26	18
valid_sources[0x6e]	1101	1			T1	1		T23	2		T18	5
valid_sources[0x6f]	747	1			T1	3		T23	1		T22	11
valid_sources[0x70]	867	1			T4	1		T17	1		T22	15
valid_sources[0x71]	755	1			T4	1		T23	1		T22	7
valid_sources[0x72]	869	1			T4	2		T23	1		T18	1
valid_sources[0x73]	1067	1			T1	1		T18	2		T22	15
valid_sources[0x74]	1133	1			T1	1		T22	5		T26	29
valid_sources[0x75]	811	1			T1	1		T42	1		T22	9
valid_sources[0x76]	997	1			T1	3		T25	2		T23	1
valid_sources[0x77]	797	1			T1	1		T22	12		T26	30
valid_sources[0x78]	733	1			T1	2		T23	1		T42	2
valid_sources[0x79]	869	1			T18	1		T22	9		T26	32
valid_sources[0x7a]	970	1			T1	2		T4	1		T22	7
valid_sources[0x7b]	720	1			T22	11		T26	24		T55	3
valid_sources[0x7c]	947	1			T23	1		T22	10		T26	30
valid_sources[0x7d]	792	1			T23	1		T42	1		T18	1
valid_sources[0x7e]	745	1			T1	2		T4	1		T22	14
valid_sources[0x7f]	682	1			T1	1		T42	5		T18	2
valid_sources[0x80]	853	1			T1	1		T22	13		T26	22

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

45123

1

T4

21

T23

12

T18

17

values[0x0]

all_enables

biggest_size

63219

1

T1

75

T2

1

T3

1

values[0x1]

all_enables

biggest_size

60545

1

T1

33

T3

2

T4

2