Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16018943

1

T2

22580

T4

35

T5

30367

full_word

141030587

1

T1

196606

T2

228290

T4

340

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	157049220	1			T1	196606		T2	250870		T4	375
auto[TlIntgErrCmd]	105	1			T69	10		T70	3		T71	3
auto[TlIntgErrData]	110	1			T69	8		T70	3		T71	5
auto[TlIntgErrBoth]	95	1			T69	2		T70	4		T71	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

75286838

1

T1

65536

T2

125500

T4

199

auto[1]

81762692

1

T1

131070

T2

125370

T4

176

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7824208	1			T2	11307		T4	17		T5	15693
auto[TlIntgErrNone]	partial	auto[1]	8194451	1			T2	11273		T4	18		T5	14674
auto[TlIntgErrNone]	full_word	auto[0]	67462489	1			T1	65536		T2	114193		T4	182
auto[TlIntgErrNone]	full_word	auto[1]	73568072	1			T1	131070		T2	114097		T4	158
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T69	7		T71	2		T133	2
auto[TlIntgErrCmd]	partial	auto[1]	50	1			T69	3		T70	2		T71	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T140	1		T141	1		T142	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T70	1		T143	1		T144	1
auto[TlIntgErrData]	partial	auto[0]	47	1			T69	3		T70	2		T133	3
auto[TlIntgErrData]	partial	auto[1]	54	1			T69	5		T71	4		T133	7
auto[TlIntgErrData]	full_word	auto[0]	3	1			T71	1		T142	1		T145	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T70	1		T133	1		T136	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T71	1		T133	2		T135	3
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T69	2		T70	3		T71	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T70	1		T146	1		T137	1
auto[TlIntgErrBoth]	full_word	auto[1]	1	1			T133	1		-	-		-	-