Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	943984	1			T4	23		T12	96		T23	2389
auto[1]	10227435	1			T2	104503		T4	21		T5	15001
auto[2]	727250	1			T4	12		T12	71		T23	879
auto[3]	9968141	1			T2	104434		T4	9		T5	15307

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14152771	1			T2	174756		T4	53		T5	153
auto[1]	2011780	1			T2	16310		T4	4		T5	1423
auto[2]	2055808	1			T2	16361		T4	7		T5	2620
auto[3]	3646451	1			T2	1510		T4	1		T5	26112

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8756694

1

T4

65

T5

30307

T10

9132

auto[1]

13110116

1

T2

208937

T5

1

T11

120544

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	400831	1			T4	19		T12	83		T23	1960
auto[0]	auto[0]	auto[1]	41031	1			T4	1		T12	5		T23	197
auto[0]	auto[0]	auto[2]	41090	1			T4	3		T12	7		T23	206
auto[0]	auto[0]	auto[3]	38161	1			T12	1		T23	26		T18	3
auto[0]	auto[1]	auto[0]	3042391	1			T4	18		T5	13		T10	4527
auto[0]	auto[1]	auto[1]	326166	1			T4	2		T5	110		T12	124
auto[0]	auto[1]	auto[2]	331133	1			T5	1387		T11	2		T12	75
auto[0]	auto[1]	auto[3]	318378	1			T4	1		T5	13490		T11	11
auto[0]	auto[2]	auto[0]	289197	1			T4	11		T23	684		T28	2632
auto[0]	auto[2]	auto[1]	31121	1			T4	1		T23	67		T28	259
auto[0]	auto[2]	auto[2]	32782	1			T12	64		T23	114		T24	3
auto[0]	auto[2]	auto[3]	30273	1			T12	7		T23	14		T18	18
auto[0]	auto[3]	auto[0]	2894001	1			T4	5		T5	140		T10	4605
auto[0]	auto[3]	auto[1]	312631	1			T5	1313		T11	1		T12	55
auto[0]	auto[3]	auto[2]	334367	1			T4	4		T5	1233		T11	1
auto[0]	auto[3]	auto[3]	293141	1			T5	12621		T11	4		T12	13
auto[1]	auto[0]	auto[0]	14053	1			T111	291		T66	140		T113	515
auto[1]	auto[0]	auto[1]	63356	1			T111	1297		T66	661		T113	2342
auto[1]	auto[0]	auto[2]	62677	1			T111	1292		T28	1		T66	644
auto[1]	auto[0]	auto[3]	282785	1			T111	5750		T66	2926		T113	10211
auto[1]	auto[1]	auto[0]	3754103	1			T2	87390		T11	1971		T81	50324
auto[1]	auto[1]	auto[1]	617136	1			T2	7739		T11	8948		T81	4294
auto[1]	auto[1]	auto[2]	593420	1			T2	8640		T11	8999		T81	5057
auto[1]	auto[1]	auto[3]	1244708	1			T2	734		T5	1		T11	40094
auto[1]	auto[2]	auto[0]	9833	1			T111	159		T28	1		T113	464
auto[1]	auto[2]	auto[1]	44615	1			T111	758		T113	2120		T151	4503
auto[1]	auto[2]	auto[2]	52487	1			T111	1384		T66	575		T113	1902
auto[1]	auto[2]	auto[3]	236942	1			T111	6241		T66	2524		T113	8852
auto[1]	auto[3]	auto[0]	3748362	1			T2	87366		T11	2003		T81	49954
auto[1]	auto[3]	auto[1]	575724	1			T2	8571		T11	9046		T81	4986
auto[1]	auto[3]	auto[2]	607852	1			T2	7721		T11	9033		T81	4452
auto[1]	auto[3]	auto[3]	1202063	1			T2	776		T11	40450		T81	427