Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1157747709	257165	0	0
ctrl_regwen_rd_A	1157747709	4893	0	0
exec_rd_A	1157747709	4636	0	0
exec_regwen_rd_A	1157747709	4938	0	0
readback_rd_A	1157747709	3022	0	0
readback_regwen_rd_A	1157747709	2793	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157747709	257165	0	0
T22	76159	4299	0	0
T26	203173	10918	0	0
T27	0	3976	0	0
T41	0	5443	0	0
T48	263510	0	0	0
T49	0	4698	0	0
T55	138229	0	0	0
T56	73337	0	0	0
T61	0	16596	0	0
T72	79032	0	0	0
T75	0	2592	0	0
T76	0	3235	0	0
T77	0	2216	0	0
T78	0	5424	0	0
T79	76388	0	0	0
T80	78518	0	0	0
T81	235387	0	0	0
T82	1514	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157747709	4893	0	0
T51	0	397	0	0
T115	225382	612	0	0
T116	0	365	0	0
T117	0	110	0	0
T118	0	156	0	0
T119	0	240	0	0
T120	0	80	0	0
T121	0	300	0	0
T122	0	349	0	0
T123	0	195	0	0
T124	819871	0	0	0
T125	394243	0	0	0
T126	100474	0	0	0
T127	39384	0	0	0
T128	120715	0	0	0
T129	72920	0	0	0
T130	242995	0	0	0
T131	34061	0	0	0
T132	145889	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157747709	4636	0	0
T51	0	448	0	0
T115	225382	447	0	0
T116	0	334	0	0
T117	0	49	0	0
T118	0	81	0	0
T119	0	163	0	0
T120	0	110	0	0
T121	0	298	0	0
T122	0	338	0	0
T123	0	174	0	0
T124	819871	0	0	0
T125	394243	0	0	0
T126	100474	0	0	0
T127	39384	0	0	0
T128	120715	0	0	0
T129	72920	0	0	0
T130	242995	0	0	0
T131	34061	0	0	0
T132	145889	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157747709	4938	0	0
T51	0	503	0	0
T115	225382	571	0	0
T116	0	316	0	0
T117	0	101	0	0
T118	0	195	0	0
T119	0	212	0	0
T120	0	97	0	0
T121	0	380	0	0
T122	0	321	0	0
T123	0	160	0	0
T124	819871	0	0	0
T125	394243	0	0	0
T126	100474	0	0	0
T127	39384	0	0	0
T128	120715	0	0	0
T129	72920	0	0	0
T130	242995	0	0	0
T131	34061	0	0	0
T132	145889	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157747709	3022	0	0
T51	0	401	0	0
T115	225382	490	0	0
T116	0	296	0	0
T117	0	76	0	0
T118	0	155	0	0
T119	0	171	0	0
T120	0	71	0	0
T121	0	276	0	0
T122	0	316	0	0
T123	0	105	0	0
T124	819871	0	0	0
T125	394243	0	0	0
T126	100474	0	0	0
T127	39384	0	0	0
T128	120715	0	0	0
T129	72920	0	0	0
T130	242995	0	0	0
T131	34061	0	0	0
T132	145889	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157747709	2793	0	0
T51	0	439	0	0
T115	225382	378	0	0
T116	0	236	0	0
T117	0	106	0	0
T118	0	107	0	0
T119	0	171	0	0
T120	0	73	0	0
T121	0	285	0	0
T122	0	308	0	0
T123	0	137	0	0
T124	819871	0	0	0
T125	394243	0	0	0
T126	100474	0	0	0
T127	39384	0	0	0
T128	120715	0	0	0
T129	72920	0	0	0
T130	242995	0	0	0
T131	34061	0	0	0
T132	145889	0	0	0