Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

---

Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	338532608	1			T1	10848		T2	2834		T3	127784
instr_valid_dis	300364206	1			T1	10848		T2	2834		T3	127784
instr_en	26516063	1			T5	80624		T26	202790		T44	200288

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	13142739	1			T5	13346		T26	82180		T21	98340
sram_ifetch_valid_disable	300341887	1			T1	10848		T2	2834		T3	127784
sram_ifetch_enable	25047982	1			T5	18826		T26	190534		T21	140208

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	338532608	1			T1	10848		T2	2834		T3	127784
hw_debug_en_valid_off	298888911	1			T1	10848		T2	2834		T3	127784
hw_debug_en_on	28063299	1			T5	44024		T26	117496		T21	92314

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	300341887	1			T1	10848		T2	2834		T3	127784
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	286348950	1			T1	10848		T2	2834		T3	127784
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9638884	1			T5	61798		T26	11250		T44	52534
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	6052283	1			T26	27346		T21	78832		T44	55090
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	2099000	1			T21	78832		T139	12280		T85	9130
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2524653	1			T26	21930		T44	55090		T85	24538
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4119822	1			T18	17616		T19	9618		T139	64130
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1593802	1			T18	17616		T19	9618		T139	20000
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1609174	1			T143	20000		T141	29792		T147	16450
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	14288669	1			T5	44024		T26	117496		T21	24800
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	8448806	1			T26	106246		T21	24800		T18	6606
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3990681	1			T5	44024		T26	11250		T44	25312

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	11276442	1			T5	18826		T26	114776		T44	92664
lc_exec_en	9654808	1			T21	67514		T44	13670		T18	66418
valid_exec_dis	290985708	1			T1	10848		T2	2834		T3	127784
invalid_exec_dis	38190721	1			T5	32172		T26	272714		T21	238548