Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

---

Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	138637134	1			T1	1002		T2	462		T3	3208
triple_byte_access	2889593	1			T1	880		T2	8		T3	7239
halfword_access	4429893	1			T1	1305		T2	15		T3	13217
byte_access	6196777	1			T1	1787		T2	18		T3	25284
zero_access	1879546	1			T1	450		T2	3		T3	14944

---

Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

76850590

1

T1

2738

T2

249

T3

31732

auto[1]

77182353

1

T1

2686

T2

257

T3

32160

---

Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	69005121	1			T1	493		T2	235		T3	279
auto[0]	triple_byte_access	1379108	1			T1	440		T2	3		T3	1302
auto[0]	halfword_access	2163240	1			T1	687		T2	8		T3	4608
auto[0]	byte_access	3178692	1			T1	892		T2	3		T3	13578
auto[0]	zero_access	1124429	1			T1	226		T3	11965		T4	1
auto[1]	word_access	69632013	1			T1	509		T2	227		T3	2929
auto[1]	triple_byte_access	1510485	1			T1	440		T2	5		T3	5937
auto[1]	halfword_access	2266653	1			T1	618		T2	7		T3	8609
auto[1]	byte_access	3018085	1			T1	895		T2	15		T3	11706
auto[1]	zero_access	755117	1			T1	224		T2	3		T3	2979